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NEC, Corp.
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| Part No. |
UPD68011 UPD68070 UPD68041 UPD68001
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| OCR Text |
asic mixed signal asic mixed signal asic ma-8a, ma-9 family ma-8a, ma-9 family june 2003
nec electronics |
| Description |
Mixed Analog/Digital asic Mixed Signal asicMA-8A. MA-9 Family Pamphlet | Pamphlet[06/2003] 混合模拟/数字混合信号asic的asicMA - 8A型。马- 9系列单张|小册子[06/2003]
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| File Size |
381.35K /
44 Page |
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List of Unclassifed Manufacturers
ETC[ETC]
Electronic Theatre Controls, Inc.
QuickLogic Corp.
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| Part No. |
QL2009 QL2009-0PB256C QL2009-0PB256I QL2009-0PF144C QL2009-0PF144I QL2009-0PQ208C QL2009-0PQ208I QL2009-1PB256C QL2009-1PB256I QL2009-1PF144C QL2009-1PF144I QL2009-1PQ208C QL2009-1PQ208I QL2009-2PB256C QL2009-2PB256I QL2009-2PF144C QL2009-2PF144I QL2009-2PQ208C QL2009-2PQ208I QL2009-XPB256C QL2009-XPB256I QL2009-XPF144C QL2009-XPF144I QL2009-XPQ208C QL2009-XPQ208I QUICKLOGICCORP.-QL2009
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| OCR Text |
...in One Device
... 9,000 usable asic gates, 225 I/O pins
-16-bit counter speeds exceeding 200 MHz -9,000 usable asic gates, 16,000 usable PLD gates, 225 I/Os -3-layer metal ViaLink(R) process for small die sizes -100% routable and pin-out ... |
| Description |
3.3V and 5.0V pasic 2 FPGA combining speed, density, low cost and flexibility.
3.3V and 5.0V pasic? 2 FPGA Combining Speed Density Low Cost and Flexibility
3.3V and 5.0V pasicò 2 FPGA
3.3V and 5.0V pasic? 2 FPGA Combining Speed, Density, Low Cost and Flexibility
3.3V and 5.0V pasic 2 FPGA Combining Speed/ Density/ Low Cost and Flexibility
3.3V and 5.0V pasic 2 FPGA Combining Speed, Density, Low Cost and Flexibility(高速，高可用密度，低成本、可适应性强.3V.0V pasic 2系列场可编程逻辑器件)
PT 6C 6#20 PIN RECP
PT 8C 8#20 PIN RECP
3.3V and 5.0V pasic 2 FPGA Combining Speed, Density, Low Cost and Flexibility 3.3V.0V帕希奇？ 2 FPGA的结合速度，密度，低成本和灵活
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| File Size |
271.17K /
12 Page |
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it Online |
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Cypress Semiconductor, Corp.
CYPRESS SEMICONDUCTOR CORP
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| Part No. |
CY2509ZXC-1 CY25010 CY250911 CY2510ZXC-1 CY2510ZXC-1T
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| OCR Text |
... can be applied to any device (asic, multiple output clock buffe r/driver, etc.) which is put into the feedback path. referring to figure 2 , if the traces between the asic/buffer and the destination of the clock signal(s) (a) are equa... |
| Description |
Spread Aware(TM), Ten/Eleven Output Zero Delay Buffer; Voltage (V): 3.3 V; Frequency Range: 40 MHz to 140 MHz; Outputs: 10; Operating Range: 0 to 70 C 2509 SERIES, PLL BASED CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24
Spread Aware? Ten/Eleven Output Zero Delay Buffer
Spread Aware(TM), Ten/Eleven Output Zero Delay Buffer; Voltage (V): 3.3 V; Frequency Range: 40 MHz to 140 MHz; Outputs: 11; Operating Range: 0 to 70 C 2510 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24
Spread Aware(TM), Ten/Eleven Output Zero Delay Buffer; Voltage (V): 3.3 V; Frequency Range: 40 MHz to 140 MHz; Outputs: 11; Operating Range: 0 to 70 C
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| File Size |
201.39K /
11 Page |
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it Online |
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Price and Availability
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