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ICS
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| Part No. |
M2006-03
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| OCR Text |
...-ended reference inputs support LVCMOS, LVTTL All output clocks are differential LVPECL compatible Two downstream clocks, frequency-select...to within 1nsec of selected input reference rising edge (unless M2_SEL= 1) Output duty cycle 47-53%... |
| Description |
SAW PLL for Frequency Translation with Add/Drop feature and Hitless Switching option
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| File Size |
223.26K /
6 Page |
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ICS
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| Part No. |
M2006-04
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| OCR Text |
...LVPECL, as well as single-ended LVCMOS, LVTTL Power-up frequency translation ratio of x32 useful for 19.44MHz input and 155.52 or 622.08MHz...to +3.3V. Clock output pairs. Differential LVPECL. P Divider control. LVCMOS/LVTTL. For P1: Logic 1 ... |
| Description |
VCSO Frequency Translator
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| File Size |
300.56K /
12 Page |
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it Online |
Download Datasheet |
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ICS
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| Part No. |
M2006-11 M2006-21 M2006-11-622.0800
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| OCR Text |
...LVPECL, as well as single-ended LVCMOS, LVTTL
Figure 1: Pin Assignment
Example Input / Output Frequency Combinations
Input Clock VCSO...to +3.3V. Clock output pairs. Differential LVPECL. P Divider control. LVCMOS/LVTTL. For P1: Logic 1 ... |
| Description |
PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), CQCC36
SAW PLL for Frequency Translation with Add/Drop feature and Hitless Switching option
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| File Size |
312.67K /
14 Page |
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it Online |
Download Datasheet |
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Integrated Circuit System
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| Part No. |
M2006-12
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| OCR Text |
...ial LVPECL. P Divider controls. LVCMOS/LVTTL. (For P0_SEL, P1_SEL, see Table 5 on pg. 3. Reference clock input pair 1. Differential LVPECL o...to these pins can cause erratic device operation.
Table 2: Pin Descriptions
Input Input
Inter... |
| Description |
VCSO BASED FEC CLOCK PLL
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| File Size |
262.41K /
8 Page |
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it Online |
Download Datasheet |
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Price and Availability
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