...ns ns ns ns ns ns ns ns tCYC ns ms ms ns ns s K Cycles Years
INTERFACE TIMING CHARACTERIsTICs - Applies to All Parts5, 10 Clock Cycle Time (tCYC) t1 Cs setup Time t2 CLK shutdown Time to Cs Rise t3 Input Clock Pulsewidth t 4, t 5 Clock L...
Description
8-Bit Dual Nonvolatile Memory Digital Potentiometer
...nits ns ns ns ns ns ns ns ns ns ms ns ns ns ms ns ns
INTERFACE TIMING CHARACTERIsTICs applies to all parts(Notes 5, 8) Clock level high o...s D O2 RDY
sDO 1 CLK IDLEs LOW
sDO 2 CLK IDLEs HIGH
Figure 1. Timing Diagram
REV PrD 6 N...
Description
Audio digital potentiometers DUAL 250K DIGITAL POTENTIOMETER, 3-WIRE sERIAL CONTROL INTERFACE, 1024 POsITIONs, PDsO16 Nonvolatile Memory/ Dual 1024 Position Digital Potentiometers REs MF 1/8W 160K 1% 2PPM Nonvolatile Memory, Dual 1024 Position Digital Potentiometers
... mA Overload Recovery Time: 0.2 ms No External Components Required
AD8628
the AD8628 family to reduce input biasing complexity and maxim...s.A. World Wide Web site: http://www.analog.com Tel: 617/329-4700 (c) Analog Devices, Inc., 2002 Fax...
...s ns ns ns ns ns ns CLK CLK CLK ms 3 1 1 1 1 1 1 /RAs to /CAs delay /RAs active time /RAs precharge time /RAs to /RAs bank active delay /CAs...s
0
8
0
8
400mil 54pin TsOP II Package
Rev 1 April, 2001
8
...