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For low-latency Found Datasheets File :: 10494 Search Time::4.047ms
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				ICST[Integrated Circuit Systems] Integrated Device Technology, Inc. ADDtek, Corp.
Part No.	ICS9248-77 ICS9248YF-77 ICS9248YF-77LF AV9248F-77
OCR Text	...down the chip when drive active(Low). The internal PLLs are disabled and all the output clocks are held at a Low state. 24 or 48MHz output s...latency requirement next page. 2. On means active. 3. PD# pulled Low, impacts all outputs including ...
Description	Frequency timing generator for Pentium II system 820 Single Chip Clock, Supports 66.6 - 150MHz Frequency Timing Generator for PENTIUM II Systems 20-Bit Buffers/Drivers With 3-State Outputs 56-SSOP -40 to 85 150 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 SSOP-48 Replaced by SN74ABT16373A : 16-Bit Transparent D-Type Latches With 3-State Outputs 48-SSOP -40 to 85 频率的奔腾II系统时序发生
File Size	311.66K / 14 Page	View it Online	Download Datasheet

				ICST[Integrated Circuit Systems]
Part No.	ICS9248-78 ICS9248YF-78
OCR Text	...ous CPUCLKS Asynchronous active low input pin used to power down the device into a low power state. The internal clocks are disabled and the VCO and the crystal are stopped. The latency of the power down will not be greater than 3ms. Clock ...
Description	810 Single Chip Clock, Supports 66.6 - 150MHz Frequency Timing Generator for Pentium II Systems
File Size	573.87K / 13 Page	View it Online	Download Datasheet

				ICST[Integrated Circuit Systems] Integrated Device Technology, Inc.
Part No.	ICS9248-81 ICS9248YF-81 AV9248F-81
OCR Text	...ched input. Asynchronous active low input pin used to stop the CPUCLK in low state, all other clocks will continue to run. The CPUCLK will have a "Turnon" latency of at least 3 CPU clocks. SDRAM clock outputs. Frequency is selected by SD-SE...
Description	Frequency generator and integrated buffer Single Chip, SIS 530/620 133MHz System Clock with AGP Clocks Frequency Generator & Integrated Buffers 133.3 MHz, OTHER CLOCK GENERATOR, PDSO48 0.300 INCH, SSOP-48
File Size	541.76K / 18 Page	View it Online	Download Datasheet

				Integrated Device Technology, Inc. ICST[Integrated Circuit Systems] Integrated Circuit Syst...
Part No.	ICS9248-87 ICS9248YF-87 ICS9248YF-87LF AV9248F-87
OCR Text	...erant input Asynchronous active low input pin used to power down the device into a low power state. The internal clocks are disabled and the VCO and the crystal are stopped. The latency of the power down will not be greater than 3ms. 2 SDRA...
Description	Frequency generator and integrated buffer for Celeron and PII/III 150 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 0.300 INCH, SSOP-48 16-Bit Transparent D-Type Latches With 3-State Outputs 48-TSSOP -40 to 85 810E Single Chip Clock, Supports 66 - 155MHz (P) Frequency Generator & Integrated Buffers for Celeron & PII/III⑩ Frequency Generator & Integrated Buffers for Celeron & PII/III?
File Size	359.72K / 13 Page	View it Online	Download Datasheet

				Integrated Circuit Systems
Part No.	ICS9248-96
OCR Text	...ck outputs. Asynchronous active low input pin used to power down the device into a low power state. The internal clocks are disabled and the VCO and the crystal are stopped. The latency of the power down will not be greater than 3ms. Clock ...
Description	20-Bit Bus-Interface D-Type Latches With 3-State Outputs 56-SSOP -40 to 85 Frequency Generator & Integrated Buffers for Celeron & PII/III
File Size	385.82K / 12 Page	View it Online	Download Datasheet

				ICST[Integrated Circuit Systems] Integrated Device Technology, Inc.
Part No.	ICS9248-99 ICS9248YF-99 AV9248F-99
OCR Text	...erant input Asynchronous active low input pin used to power down the device into a low power state. The internal clocks are disabled and the VCO and the crystal are stopped. The latency of the power down will not be greater than 3ms. SDRAM ...
Description	Frequency generator and integrated buffer for Celeron and PII/III Frequency Generator & Integrated Buffers for Celeron & PII/III?/a> Frequency Generator & Integrated Buffers for Celeron & PII/III⑩ 16-Bit Transparent D-Type Latches With 3-State Outputs 48-SSOP -40 to 85 频率发生
File Size	448.05K / 13 Page	View it Online	Download Datasheet

				Elite Semiconductor Memory Technology Inc. ETC
Part No.	M12L16161A M12L16161A-4.3T M12L16161A-5.5T M12L16161A-5T M12L16161A-6T M12L16161A-7T M12L16161A-8T
OCR Text	... going edge of the CLK with RAS low. Enables row access & precharge. Latches column addresses on the positive going edge of the CLK with CAS...Latency -4.3 -5 -5.5 -6 -7 -8 Unit Note 1 Burst Length = 1 tRC tRC (min), tCC tCC (min), IOL= 0...
Description	512K x 16Bit x 2Banks Synchronous DRAM
File Size	564.61K / 27 Page	View it Online	Download Datasheet

				Mitsubishi Electric Corporation Mitsubishi Electric Semiconductor
Part No.	M5M4V16169DRT-10 M5M4V16169DRT-15 M5M4V16169DRT-7 M5M4V16169DRT-8 M5M4V16169DTP M5M4V16169RT-15 M5M4V16169RT-10 M5M4V16169RT-8 M5M4V16169RT-7 M5M4V16169DTP-15 M5M4V16169DTP-10 M5M4V16169DTP-7 M5M4V16169DTP-8
OCR Text	...emory systems where high speed, low power dissipation, and low cost are essential. The use of quadruple-layer polysilicon process combined w...latency. # Synchronous design for precise control with an external clock (K). # Output retention by ...
Description	16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
File Size	733.86K / 64 Page	View it Online	Download Datasheet

				MITSUBISHI[Mitsubishi Electric Semiconductor]
Part No.	M5M4V16G50DFP-10 M5M4V16G50DFP-12 M5M4V16G50DFP-8 16MSGRAMFP
OCR Text	...ols internal clock. When CKE is low, internal clock for the following cycle is stopped. CKE is also used to select auto / self refresh. Afte...latency. When A9 = H at this command, the bank is deactivated after the burst read (auto-precharge, ...
Description	From old datasheet system 16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM
File Size	165.49K / 33 Page	View it Online	Download Datasheet

				Mitsubishi Electric Corporation MITSUBISHI[Mitsubishi Electric Semiconductor]
Part No.	M5M4V4S40CTP-12 M5M4V4S40CTP-15 4MX16SDRAMTP
OCR Text	...the internal clock. When CKE is low, the internal clock for the following cycle is disabled. CKE is also used to select auto and self refres...latency. If A8 =H when READ is issued the bank is automatically precharged after the last burst read...
Description	4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM From old datasheet system
File Size	1,456.01K / 45 Page	View it Online	Download Datasheet

For low-latency Found Datasheets File :: 10494 Search Time::4.047ms
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