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  auto-transfer Datasheet PDF File

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    IDT77V107 IDT77V107L25PF IDT77V107L25PFI

IDT[Integrated Device Technology]
Part No. IDT77V107 IDT77V107L25PF IDT77V107L25PFI
OCR Text ...ansmit & Receive FIFOs Receiver Auto-Synchronization and Good Signal Indication Supports UTP Category 3 physical media Interfaces to standar...Transfer Mode (ATM) data communications and networking. The IDT77V107 implements the physical layer ...
Description 3.3V ATM PHY for 25.6 and 51.2 Mbps Applications with UTOPIA level 2 Interface
Single ATM PHY for 25.6 and 51.2 Mbps with Utopia Level 2

File Size 174.29K  /  24 Page

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    MPXV5004DP MPXV5004G MPXV5004G6T1 MPXV5004G6U MPXV5004G7U MPXV5004GC6T1 MPXV5004GC7U MPXV5004GP MPXV5004GVP MPXV5004

Freescale (Motorola)
ETC[ETC]
Part No. MPXV5004DP MPXV5004G MPXV5004G6T1 MPXV5004G6U MPXV5004G7U MPXV5004GC6T1 MPXV5004GC7U MPXV5004GP MPXV5004GVP MPXV5004
OCR Text ...s a percent of VFSS, at 25C. 5. Auto Zero at Factory Installation: Due to the sensitivity of the MPXV5004G, external mechanical stresses and...TRANSFER FUNCTION: Vout = VS*[(0.2*P) + 0.2] 1.5% VFSS VS = 5.0 V 0.25 Vdc 4.0 TEMP = 10 to 60C OU...
Description Integrated Pressure Sensor
Integrated Silicon Pressure Sensor On-Chip Signal Conditioned Temperature Compensated and Calibrated
Integrated Silicon Pressure Sensor On-Chip Signal Conditioned, Temperature Compensated and Calibrated

File Size 263.36K  /  12 Page

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    MTV003 MTV003N

ETC[ETC]
Part No. MTV003 MTV003N
OCR Text ...f0 = 0,0 or 1,1 -> Hpol = x, by auto detection. = 0,1 -> force Hpol = 1. = 1,0 -> force Hpol = 0. 5. Vpf1, Vpf0 = 0,0 or 1,1 -> Vpol = x, by auto detection. MTV003 Revision 2.3 07/01/1998 6/13 MYSON TECHNOLOGY Reg 2 (read) Reg 2 (write...
Description Microprocessor Compatible Monitor Controller

File Size 68.57K  /  13 Page

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    UCB1500

PHILIPS[Philips Semiconductors]
Part No. UCB1500
OCR Text ...on 1 Bit 1: 1=enable function 0 auto-loading from address 04-9Dh Bit 2: 1=enable function 0 auto-loading from address 0A-11h Bit 3: 1=enable...transfer right after an aborted DMA transfer. 14 DTP Invalid Bit Mask If this bit is set to `1', the...
Description PCI to AC97 bridge/host controller

File Size 255.21K  /  58 Page

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    V58C2128 V58C2128164S V58C2128404S V58C2128804S

MOSEL[Mosel Vitelic, Corp]
Part No. V58C2128 V58C2128164S V58C2128404S V58C2128804S
OCR Text ...harge Command Power Down Mode Auto Refresh and Self Refresh Refresh Interval: 4096 cycles/64 ms Available in 66-pin 400 mil TSOP SSTL-2...transfer rates by employing a chip architecture that prefetches multiple bits and then synchronizes ...
Description HIGH PERFORMANCE 2.5 VOLT 128 Mbit DDR SDRAM

File Size 719.10K  /  59 Page

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    V58C2256 V58C2256164S V58C2256404S V58C2256804S

MOSEL[Mosel Vitelic, Corp]
Part No. V58C2256 V58C2256164S V58C2256404S V58C2256804S
OCR Text ...harge Command Power Down Mode Auto Refresh and Self Refresh Refresh Interval: 8192 cycles/64 ms Available in 66-pin 400 mil TSOP or 60 B...transfer rates by employing a chip architecture that prefetches multiple bits and then synchronizes ...
Description HIGH PERFORMANCE 2.5 VOLT 256 Mbit DDR SDRAM

File Size 795.11K  /  61 Page

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    V58C265164S

Mosel Vitelic Corp
MOSEL[Mosel Vitelic, Corp]
Part No. V58C265164S
OCR Text ...pend Mode and Power Down Mode I Auto Refresh and Self Refresh I Refresh Interval: 4096 cycles/64 ms I Available in 66-pin 400 mil TSOP-II I ...transfer rates by employing a chip architecture that prefetches multiple bits and then synchronizes ...
Description 64 Mbit DDR SDRAM 2.5 VOLT 4M X 16

File Size 448.59K  /  44 Page

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    V58C265404S

MOSEL[Mosel Vitelic, Corp]
Part No. V58C265404S
OCR Text ...pend Mode and Power Down Mode s Auto Refresh and Self Refresh s Refresh Interval: 4096 cycles/64 ms s Available in 66-pin 400 mil TSOP-II s ...transfer rates by employing a chip architecture that prefetches multiple bits and then synchronizes ...
Description HIGH PERFORMANCE 2.5 VOLT 16M X 4 DDR SDRAM 4 BANKS X 4Mbit X 4

File Size 389.22K  /  44 Page

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    V58C265804S

MOSEL[Mosel Vitelic, Corp]
Part No. V58C265804S
OCR Text ...pend Mode and Power Down Mode s Auto Refresh and Self Refresh s Refresh Interval: 4096 cycles/64 ms s Available in 66-pin 400 mil TSOP-II s ...transfer rates by employing a chip architecture that prefetches multiple bits and then synchronizes ...
Description HIGH PERFORMANCE 2.5 VOLT 8M X 8 DDR SDRAM 4 BANKS X 2Mbit X 8

File Size 455.31K  /  44 Page

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    V58C3643204SAT

Mosel Vitelic, Corp.
MOSEL[Mosel Vitelic, Corp]
Part No. V58C3643204SAT
OCR Text ...pend Mode and Power Down Mode s Auto Refresh and Self Refresh s Refresh Interval: 2048 cycles/16ms s Available in 100-pin TQFP s SSTL-2 Comp...transfer rates by employing a chip architecture that prefetches multiple bits and then synchronizes ...
Description HIGH PERFORMANCE 3.3 VOLT 2M X 32 DDR SDRAM 4 X 512K X 32

File Size 94.83K  /  12 Page

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