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For clocked Found Datasheets File :: 9104 Search Time::0.812ms
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				FAIRCHILD[Fairchild Semiconductor]
Part No.	74ALVC16601 74ALVC16601GX 74ALVC16601MTD 74ALVC16601MTDX
OCR Text	...ow in transparent, latched, and clocked modes. Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. The clock can be controlled by the clock-enable (CL...
Description	Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs
File Size	99.88K / 8 Page	View it Online	Download Datasheet

				NXP Semiconductors PHILIPS[Philips Semiconductors]
Part No.	74ALVC16834A 74ALVC16834ADGG
OCR Text	... Output enabled Output disabled clocked mode Output enabled Output disabled CONDITIONS TYPICAL 2.3 2.6 2.5 350 4.0 8.0 13 3 pF 22 15 UNIT tPHL/tPLH fmax CI CI/O VCC = 3.3 V, CL = 50 pF VCC = 3.3 V, CL = 50 pF ns MHz pF pF CPD...
Description	18-bit registered driver with inverted register enable 3-State
File Size	121.53K / 12 Page	View it Online	Download Datasheet

				NXP Semiconductors PHILIPS[Philips Semiconductors]
Part No.	74ALVC16835A 74ALVC16835ADGG
OCR Text	... Output enabled Output disabled clocked mode Output enabled Output disabled CONDITIONS VCC = 3.3 V, CL = 50 pF VCC = 3.3 V, CL = 50 pF TYPICAL 2.3 2.6 2.5 350 4.0 8.0 13 3 pF 22 15 UNIT ns MHz pF pF CPD Power dissipation capacitance p...
Description	18-bit registered driver 3-State
File Size	119.05K / 12 Page	View it Online	Download Datasheet

				FAIRCHILD[Fairchild Semiconductor]
Part No.	74ALVC16835 74ALVC16835MTD
OCR Text	...low in transparent, latched and clocked modes. Data flow is controlled by output-enable (OE), latch-enable (LE), and clock (CLK) inputs. The device operates in Transparent Mode when LE is held HIGH. The device operates in clocked mode when ...
Description	Low Voltage 18-Bit Universal Bus Driver with 3.6V Tolerant Inputs and Outputs From old datasheet system
File Size	87.61K / 7 Page	View it Online	Download Datasheet

				PHILIPS[Philips Semiconductors] NXP Semiconductors
Part No.	74ALVC16836A 74ALVC16836ADGG
OCR Text	... Output enabled Output disabled clocked mode Output enabled Output disabled CONDITIONS TYPICAL 2.3 2.6 2.5 350 4.0 8.0 13 3 pF 22 15 UNIT tPHL/tPLH fmax CI CI/O VCC = 3.3 V, CL = 50 pF VCC = 3.3 V, CL = 50 pF ns MHz pF pF CPD...
Description	20-bit registered driver with inverted register enable 3-State
File Size	121.92K / 12 Page	View it Online	Download Datasheet

				PHILIPS[Philips Semiconductors] NXP Semiconductors N.V.
Part No.	74HC160 74HC160PW 74HC160D 74HC160DB 74HC160N 74HCT160 74HCT160D 74HCT160DB 74HCT160N 74HCT160PW 74HC160U
OCR Text	...ovided by having all flip-flops clocked simultaneously on the positive-going edge of the clock (CP). The outputs (Q0 to Q3) of the counters may be preset to a HIGH or LOW level. A LOW level at the parallel enable QUICK REFERENCE DATA GND = ...
Description	Presettable synchronous BCD decade counter asynchronous reset CAP 2700UF 6.3V ELECT FC RADIAL HCT SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP DECADE COUNTER, PDSO16 74HC/HCT160; Presettable synchronous BCD decade counter; asynchronous reset
File Size	63.62K / 9 Page	View it Online	Download Datasheet

				PHILIPS[Philips Semiconductors] NXP Semiconductors
Part No.	74HC161 74HC161N 74HC161D 74HC161DB 74HC161PW 74HCT161 74HCT161D 74HCT161DB 74HCT161N 74HCT161PW 74HC161NB
OCR Text	...ovided by having all flip-flops clocked simultaneously on the positive-going edge of the clock (CP). The outputs (Q0 to Q3) of the counters may be preset to a HIGH or LOW level. A LOW level at the parallel enable 74HC/HCT161 input (PE...
Description	Presettable synchronous 4-bit binary counter asynchronous reset Presettable synchronous 4-bit binary counter; asynchronous reset
File Size	83.50K / 12 Page	View it Online	Download Datasheet

				NXP Semiconductors PHILIPS[Philips Semiconductors]
Part No.	74HC162 74HCT162
OCR Text	...ovided by having all flip-flops clocked simultaneously on the positive-going edge of the clock (CP). The outputs (Q0 to Q3) of the counters may be preset to a HIGH or LOW level. A LOW level at the parallel enable input (PE) disables the cou...
Description	Presettable synchronous BCD decade counter; synchronous reset Presettable synchronous BCD decade counter synchronous reset
File Size	78.98K / 11 Page	View it Online	Download Datasheet

				NXP Semiconductors PHILIPS[Philips Semiconductors]
Part No.	74HC163 74HC163D 74HC163PW 74HC163DB 74HC163N 74HCT163 74HCT163D 74HCT163DB 74HCT163N 74HCT163PW 74HC163NB 74HC163U
OCR Text	...ovided by having all flip-flops clocked simultaneously on the positive-going edge of the clock (CP). The outputs (Q0 to Q3) of the counters may be preset to a HIGH or LOW level. A LOW level at the parallel enable input (PE) disables the cou...
Description	Presettable synchronous 4-bit binary counter; synchronous reset Presettable synchronous 4-bit binary counter synchronous reset
File Size	86.62K / 11 Page	View it Online	Download Datasheet

				PHILIPS[Philips Semiconductors] NXP Semiconductors
Part No.	74HCT356 74HC356
OCR Text	...the 8 input lines (D0 to D7) is clocked into a edge-triggered data register by a LOW-to-HIGH transition of the clock (CP). When the output enable input OE1 = HIGH, OE2 = HIGH or OE3 = LOW, the outputs go to the high impedance OFF-state. Ope...
Description	8-input multiplexer/register 3-state 8-input multiplexer/register; 3-state
File Size	74.78K / 13 Page	View it Online	Download Datasheet

For clocked Found Datasheets File :: 9104 Search Time::0.812ms
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