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  lvpecl Datasheet PDF File

For lvpecl Found Datasheets File :: 4819    Search Time::2.375ms    
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    CY2DL814 CY2DL814SCT CY2DL814ZCT CY2DL814ZI CY2DL814ZIT CY2DL814SC CY2DL814SI CY2DL814SIT CY2DL814ZC

CYPRESS[Cypress Semiconductor]
CYPRESS SEMICONDUCTOR CORP
Part No. CY2DL814 CY2DL814SCT CY2DL814ZCT CY2DL814ZI CY2DL814ZIT CY2DL814SC CY2DL814SI CY2DL814SIT CY2DL814ZC
OCR Text ...input configurable for -- LVDS, lvpecl, or LVTTL -- Four differential pairs of LVDS outputs Drives 50- or 100-ohm load (selectable) Low input capacitance Low output skew Does not exceed Bellcore 802.3 standards Operation at 350 MHz - 700 M...
Description Low-voltage operation
1:4 Clock Fanout Buffer

File Size 110.23K  /  8 Page

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    Maxim
Part No. MAX19541
OCR Text ...est performance, a differential lvpecl sampling clock is recommended. The digital outputs are CMOS compatible and the data format can be selected to be either two's complement or offset binary. A pin-compatible, 12-bit, 170Msps version of t...
Description 12-Bit, 125Msps ADC with CMOS Outputs for Wideband Applications

File Size 266.72K  /  23 Page

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    NB4N855S NB4N855SMR4 NB4N855SMR4G

ONSEMI[ON Semiconductor]
Part No. NB4N855S NB4N855SMR4 NB4N855SMR4G
OCR Text ...lating AnyLevelTM input signal (lvpecl, CML, HSTL, LVDS, or LVTTL/LVCMOS) to LVDS. Depending on the distance, noise immunity of the system design, and transmission line media, this device will receive, drive or translate data or clock signa...
Description 3.3 V, 1.5 Gb/s Dual AnyLevelTM to LVDS Receiver/Driver/Buffer/ Translator

File Size 130.78K  /  10 Page

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    SY10ELT23L SY10ELT23LZCTR SY10ELT23LZC SY100ELT23L SY100ELT23LZC SY100ELT23LZCTR

Micrel Semiconductor, Inc.
MICREL[Micrel Semiconductor]
Part No. SY10ELT23L SY10ELT23LZCTR SY10ELT23LZC SY100ELT23L SY100ELT23LZC SY100ELT23LZCTR
OCR Text lvpecl-to-LVTTL TRANSLATOR FEATURES s s s s s s s 3.3V power supply 2.0ns typical propagation delay <500ps typical output-to-output skew Differential lvpecl inputs 24mA LVTTL outputs Flow-through pinouts Available in 8-pin SOIC package ...
Description 3.3V DUAL DIFFERENTIAL lvpecl-to-LVTTL TRANSLATOR DUAL PECL TO TTL TRANSLATOR, TRUE OUTPUT, PDSO8

File Size 50.18K  /  4 Page

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    FG324 IO96PDB2V1 IO99NDB2V2 IO99PDB2V2 IO83PSB2V0 A3P3000L VQ100

Microsemi Corporation
Part No. FG324 IO96PDB2V1 IO99NDB2V2 IO99PDB2V2 IO83PSB2V0 A3P3000L VQ100
OCR Text ... ? differential i/o standards: lvpecl, lvds, b-lvds, and m-lvds ? voltage-referenced i/o standards: gtl+ 2.5 v / 3.3 v, gtl 2.5 v / 3.3 v, hstl class i and ii, sstl2 class i and ii, sstl3 class i and ii (a3pe3000l only) ? wide range power...
Description ProASIC3L Low Power Flash FPGAs with Flash*Freeze Technology

File Size 11,714.05K  /  242 Page

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    MPC92432 MPC92432FA

Motorola, Inc
MOTOROLA[Motorola Inc]
Part No. MPC92432 MPC92432FA
OCR Text ...ct Preview 1360 MHz Dual Output lvpecl Clock Synthesizer The MPC92432 is a 3.3V compatible, PLL based clock synthesizer targeted for high performance clock generation in mid-range to high-performance telecom, networking, and computing appl...
Description 1360 MHz Dual Output lvpecl Clock Synthesizer

File Size 447.23K  /  20 Page

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    PI90LV03TX PI90LV03 PI90LVB03TX PI90LV03TEX PI90LVB03 PI90LVB03TEX

PERICOM[Pericom Semiconductor Corporation]
Pericom Technology
Part No. PI90LV03TX PI90LV03 PI90LVB03TX PI90LV03TEX PI90LVB03 PI90LVB03TEX
OCR Text ...ard LVDS receiver inputs accept lvpecl signals Low jitter 660 Mbps fully differential data path Bus-Terminal ESD exceeds 2kV Single +3.3V supply voltage operation Receiver Differential Input Voltage Threshold < 100mV Receiver open-circuit f...
Description SOTiny LVDS Repeater

File Size 209.86K  /  7 Page

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For lvpecl Found Datasheets File :: 4819    Search Time::2.375ms    
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