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Rochester Electronics, LLC
PHILIPS[Philips Semiconductors]
NXP Semiconductors
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| Part No. |
74ALS109AN 74ALS109A 74ALS109AD
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| OCR Text |
...nput current High-level Jn, Kn, cpn SDn, RDn Jn, Kn, cpn IIH SDn, RDn Jn, Kn, cpn IIL IO ICC Low-level Low level input current Output current3 (total)4 SDn, RDn VCC = MAX, VI = 0 4V MAX 0.4V VCC = MAX, VO = 2.25V VCC = MAX -30 3.0 VCC = MAX... |
| Description |
Dual J-K positive edge-triggered flip-flop with set and reset ALS SERIES, DUAL POSITIVE EDGE TRIGGERED J-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP16
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| File Size |
87.67K /
9 Page |
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it Online |
Download Datasheet
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Fairchild
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| Part No. |
74LVX74
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| OCR Text |
...PHL Parameter Propagation Delay cpn to Qn or Qn 3.3 0.3 tPLH tPHL Propagation Delay CDn to SDn to Qn or Qn 3.3 0.3 tW tS tH tREC fMAX cpn or CDn or SDn Pulse Width Setup Time Dn to cpn Hold Time Dn to cpn Recovery Time cpn or SDn to cpn M... |
| Description |
Low Voltage Dual D-Type Positive Edge-Triggered
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| File Size |
71.99K /
6 Page |
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it Online |
Download Datasheet |
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MICREL[Micrel Semiconductor]
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| Part No. |
SY100S331FC SY100S331JCTR SY100S331JC SY100S331
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| OCR Text |
...as well as its own clock pulse (cpn). The resultant clock signal controlling the flip-flop is the logical OR operation of these two clock signals. Data enters the master when both CPc and cpn are LOW and enters the slave on the rising edge ... |
| Description |
TRIPLE D FLIP-FLOP
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| File Size |
109.31K /
7 Page |
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it Online |
Download Datasheet |
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Price and Availability
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