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Integrated Device Techn...
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Part No. |
IDT72T72105
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OCR Text |
... ? ? ? read enable & read clock echo outputs aid high speed operation ? ? ? ? ? user selectable asynchronous read and/or write port timing ? ? ? ? ? 2.5v lvttl or 1.8v, 1.5v hstl port selectable input/ouput voltage ? ? ? ? ? 3.3v input tole... |
Description |
2.5 VOLT HIGH-SPEED TeraSyncTM FIFO 72-BIT CONFIGURATIONS
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File Size |
374.80K /
54 Page |
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it Online |
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Integrated Device Techn...
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Part No. |
IDT72T51553L5BB IDT72T51553L5BBI IDT72T51553L6BB
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OCR Text |
...? ? 3.6ns access time ? ? ? ? ? echo read enable & echo read clock outputs ? ? ? ? ? individual, active queue flags ( ov , ff , pae , paf ) ? ? ? ? ? 8 bit parallel flag status on both read and write ports ? ? ? ? ? shows pae and paf ... |
Description |
2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 18 BIT WIDE CONFIGURATION
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File Size |
541.19K /
57 Page |
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it Online |
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Cypress
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Part No. |
CY7C2268KV18-550BZC CY7C2270KV18-400BZXC CY7C2270KV18-550BZXC
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OCR Text |
... ? sram uses rising edges only echo clocks (cq and cq ) simplify data capture in high speed systems data valid pin (qvld) to indicate valid data on the output on-die termination (odt) feature ? supported for d [x:0] , bws [x:0] , and k/k... |
Description |
36-Mbit DDR II SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT
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File Size |
631.40K /
30 Page |
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it Online |
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Cypress
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Part No. |
CY7C2168KV18-550BZC CY7C2170KV18-400BZXC CY7C2170KV18-550BZXC
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OCR Text |
... ? sram uses rising edges only echo clocks (cq and cq ) simplify data capture in high-speed systems data valid pin (qvld) to indicate valid data on the output on-die termination (odt) feature ? supported for d [x:0] , bws [x:0] , and k/k... |
Description |
18-Mbit DDR II SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT
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File Size |
634.53K /
30 Page |
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it Online |
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Cypress
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Part No. |
CY7C1668KV18-450BZXC CY7C1668KV18-550BZXC
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OCR Text |
... ? sram uses rising edges only echo clocks (cq and cq ) simplify data capture in high-speed systems data valid pin (qvld) to indicate valid data on the output synchronous internally self-timed writes ddr ii+ operates with 2.5-cycle rea... |
Description |
144-Mbit DDR II SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency)
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File Size |
610.95K /
30 Page |
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it Online |
Download Datasheet |
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Price and Availability
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