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White Electronic Design...
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| Part No. |
W3EG72128S-D3
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| OCR Text |
...re ddr200, ddr266, ddr333 and ddr400 ? jedec design speci? cations bi-directional data strobes (dqs) differential clock inputs (ck & ck#) programmable read latency 2,2.5 (clock) programmable burst length (2,4,8) programmable b... |
| Description |
1GB - 2x64Mx72 DDR SDRAM UNBUFFERED
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| File Size |
232.31K /
12 Page |
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it Online |
Download Datasheet
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White Electronic Design...
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| Part No. |
W3EG2128M72AFSR-D3
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| OCR Text |
...hitecture ddr266, ddr333, and ddr400 bi-directional data strobes (dqs) phase-lock loop (pll) clock driver to reduce loading differential clock inputs (ck & ck#) ecc error detection and correction programmable read latency 2, 2... |
| Description |
2GB - 2x128Mx72 DDR SDRAM REGISTERED ECC, w/PLL, FBGA
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| File Size |
272.42K /
13 Page |
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it Online |
Download Datasheet |
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DFI
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| Part No. |
K8M800-MLV
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| OCR Text |
...66), pc2700 (ddr333) or pc3200 (ddr400) unbuffered ddr sdram dimm note: if you are installing double rank ddr400 on both ddr 1 and ddr 2 sockets, the maximum dram speed will automatically be limited to the speed of a ddr333. however, the bi... |
| Description |
System Board User Manual
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| File Size |
4,028.94K /
119 Page |
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it Online |
Download Datasheet |
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Integrated Circuit Solu...
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| Part No. |
IC43R16160-7T
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| OCR Text |
...ial clock inputs ck and ck 56 7 ddr400 ddr333 ddr266 clock cycle time (t ck2 ) 7.5ns 7.5ns 7.5ns clock cycle time (t ck2.5 ) 6ns 6ns 7ns clock cycle time (t ck3 ) 5ns - - system frequency (f ck max ) 200mhz 166mhz 143mhz package outline j... |
| Description |
4M x 16 Bit x 4 Banks (256-MBIT) DDR SDRAM
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| File Size |
1,338.14K /
56 Page |
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it Online |
Download Datasheet |
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Price and Availability
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