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Cypress
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| Part No. |
CY7C924DX 7C924DX
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| OCR Text |
...ronous TTL parallel interface * utopia compatible host bus interface * Embedded/Bypassable 256-character synchronous FIFOs * Integrated support for daisy-chain and ring topologies * Domain or individual destination device addressing * 50- t... |
| Description |
200-MBaud HOTLink Transceiver
From old datasheet system
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| File Size |
634.17K /
58 Page |
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it Online |
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意法半导
??????浣?
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| Part No. |
ST70135 ST70135A
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| OCR Text |
...(g.lite) n supports either atm (utopia level 1 & 2) or bitstream interface n 16 bit multiplexed microprocessor interface (little and big endian compatibility) n analog front end management n dual latency paths: fast and interleaved n atm's ... |
| Description |
ASCOTTM DMT TRANSCEIVER
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| File Size |
202.71K /
29 Page |
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it Online |
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IDT
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| Part No. |
79RC32355
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| OCR Text |
...nels
GPIO Pins
TDM Bus
utopia 1 / 2
Figure 1 RC32355 Internal Block Diagram
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
1 of 47
2002 Integrated Device Technology, Inc.
December 1... |
| Description |
Integrated Communications Processor
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| File Size |
576.00K /
47 Page |
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it Online |
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Motorola
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| Part No. |
MPC8260AED MPC8260AEC
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| OCR Text |
...8 TDM Ports
3 MII Ports
2 utopia Ports
Non-Multiplexed I/O
Notes: 1. MPC8264A 2. MPC8265A 3. MPC8266A
Figure 1. MPC8266A Block Diagram
1.1
*
Features
Dual-issue integer core -- A core version of the EC603e microproces... |
| Description |
(HiP4) Family Hardware Specifications
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| File Size |
329.64K /
48 Page |
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it Online |
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Zarlink
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| Part No. |
MT90222 MT90223 MT90224
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| OCR Text |
...
RX External Static RAM
RX utopia Level 2 BUS TX
Rx utopia FIFo
Internal IMA Processors (1 per group)
TDM Ring Control S/P
T1/E1/DSL
utopia I/F CTRL
Cell Delineator CD Circuits (1 per link)
T1/E1/DSL
P/S Tx Utop... |
| Description |
4/8/16 Port IMA/TC PHY Device
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| File Size |
1,124.49K /
160 Page |
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it Online |
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PMC
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| Part No. |
PM5945
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| OCR Text |
...side signals to comply with the utopia like signals of the Vicksburg motherboard. The receive drop side also incorporates an additional FIFO, as the internal 4 cell FIFO of the SUNI device is insufficient to handle the latency time between ... |
| Description |
SAPI DAUGHTERBOARD
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| File Size |
1,440.04K /
75 Page |
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it Online |
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Price and Availability
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