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Cypress
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Part No. |
CY7C25682KV18-400BZXC CY7C25682KV18-500BZC CY7C25682KV18-550BZXI
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OCR Text |
... ? sram uses rising edges only echo clocks (cq and cq ) simplify data capture in high speed systems data valid pin (qvld) to indicate valid data on the output on-die termination (odt) feature ? supported for d [x:0] , bws [x:0] , and k/k... |
Description |
72-Mbit DDR II SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT
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File Size |
612.03K /
29 Page |
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it Online |
Download Datasheet |
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Cypress
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Part No. |
CY7C1248KV18-400BZC CY7C1250KV18-400BZC
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OCR Text |
... ? sram uses rising edges only echo clocks (cq and cq ) simplify data capture in high speed systems data valid pin (qvld) to indicate valid data on the output synchronous internally self-timed writes ddr ii+ operates with 2.0 cycle read... |
Description |
36-Mbit DDR II SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency)
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File Size |
618.67K /
28 Page |
View
it Online |
Download Datasheet |
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Price and Availability
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