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(R)
July 1999
Features
U C T ME N T R OD E TE P EPLAC nter at E S OL D E D R t Ce m/tsc OB or ME N Supp il.co COM chnical w.inters RE e NO rT ww ct ou IL or onta INTERS c 81-88
ICL8049
Antilog Amplifier
Description
The ICL8049 is a monolithic antilogarithmic amplifier that is fully temperature compensated and is nominally designed to provide 1 decade of output voltage for each 1V change of input voltage. For increased flexibility, the scale factor, reference current and offset voltage are externally adjustable.
* Full Scale Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . 0.5% * Temperature Compensated Operation . . . . 0o C to 70 C
o
* Scale Factor, Adjustable . . . . . . . . . . . . . . . . 1V/Decade * Dynamic Voltage Range . . . . . . . . . . . . . . . . . . . . .60dB * Dual JFET Input Op Amps
Part Number Information
PART NUMBER ICL8049BCJE ICL8049CCJE ERROR (25oC) 10mV 25mV TEMPERATURE RANGE (o C) 0 to 70 0 to 70 PACKAGE 16 Ld CERDIP 16 Ld CERDIP
Pinout
ICL8049 (CERDIP) TOP VIEW
A1 INPUT GAIN IREF A1 OFFSET NULL A1 OFFSET NULL VA1 OUTPUT NC 1 2 3 4 5 6 7 8 16 VIN 15 GND 14 A2 INPUT A2 OFFSET NULL 12 A2 OFFSET NULL 11 V+ 13 10 VOUT 9 NC
Functional Diagram
ICL8049
VREF 3 IREF A2 INPUT Q1 Q2 14 fOUT
VIN 16 GAIN 2
-
A1 + 1 A1 INPUT 7 A1 OUTPUT 15 GND
-
A2 +
10 VOUT
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2002. All Rights Reserved 1
File Number
4768
ICL8049
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18V VIN (Input Current) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15V IREF (Reference Current) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2mA Voltage Between Offset Null and V+ . . . . . . . . . . . . . . . . . . . 0.5V Output Short Circuit Duration . . . . . . . . . . . . . . . . . . . . . . . Indefinite Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750mW Lead Temperature (Soldering 10 Sec.) . . . . . . . . . . . . . . . . . 300oC
Operating Conditions
Operating Temperature Range . . . . . . . . . . . . . . . . . . . 0oC to 70oC Storage Temperature Range . . . . . . . . . . . . . . . . . . -65oC to 150oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Electrical Specifications
VS = 15V, TA = 25oC, IREF = 1mA, Scale Factor Adjusted for 1 Decade (Out) per Volt (In), Unless Otherwise Specified ICL4049BC ICL8049CC MAX 15 75 25 200 6.7 MIN 60 12 10 TYP 5 30 0.55 2.0 15 26 14 13 150 5 MAX 25 150 50 200 6.7 UNITS dB mV mV mV/oC V/V mV VRMS V V mW mA
PARAMETERS Dynamic Range (VOUT) Error, Absolute Value
TEST CONDITIONS VOUT = 10mV to 10V 0V VIN 2V TA = 0oC to 70oC, 0V VIN 3V
MIN 60 12 10 -
TYP 3 20 0.38 2.0 15 26 14 13 150 5
Temperature Coefficient, Referred to VIN Power Supply Rejection Ratio Offset Voltage (A1 and A2) Wideband Noise Output Voltage Swing
VIN = 3V Referred to Input, for VIN = 0V Before Nulling Referred to Input, for VIN = 0V RL = 10k RL = 2k
Power Consumption Supply Current
2
ICL8049
V+ VREF (+15V) RREF 15k IREF 3 14 IOUT Q1 Q2 ROUT 10k R2
R3 15k
C1 VIN R1 15.9k 2 16 7 200pF
R4 2k
R6 100k 680 (LOW T.C.) R5 15k 1k
A1 +
+
15 12
A2
10 VOUT
V-
1
R7 2k
13
V+
FIGURE 1. ICL8049 OFFSET AND SCALE FACTOR ADJUSTMENT
ICL8049 Detailed Description
The ICL8049 relies on the same logarithmic properties of the transistor as the ICL8048. The input voltage forces a specific VBE between Q 1 and Q2 (Figure 1). This VBE difference is converted into a difference of collector currents by the transistor pair. The equation governing the behavior of the transistor pair is derived from (2) on the previous page and is as follows:
I C1 I C2
For voltage references Equation 3 becomes
V OUT
=
V
R -R2 qV IN OUT x ----------- exp --------------------- x -------REF R ( R 1 + R 2 ) kT REF
(4)
ICL8049 Offset and Scale Factor Adjustment
As with the log amplifier, the antilog amplifier requires three adjustments. The first step is to null out the offset voltage of A2. This is accomplished by reverse biasing the base-emitter of Q2. A2 then operates as a unity gain buffer with a grounded input. The second step forces VIN = 0; the output is adjusted for V OUT = 10V. This step essentially "anchors" one point on the transfer function. The third step applies a specific input and adjusts the output to the correct voltage. This sets the scale factor. Referring to Figure 1 the exact procedure for 1 decade/volt is as follows: 1. Connect the input (pin #16) to +15V. This reverse biases the base-emitter of Q2. Adjust R7 for VOUT = 0V. Disconnect the input from +15V. 2. Connect the input to Ground. Adjust R4 for VOUT = 10V. Disconnect the input from Ground. 3. Connect the input to a precise 2V supply and adjust R2 for VOUT = 100mV. The procedure outlined above optimizes the performance over a 3 decade range at the output (i.e., VOUT from 10mV) to 10V). For a more limited range of output voltages, for example 1V to 10V, it would be better to use a precise 1V supply and adjust for VOUT = 1V. For other scale factors and/ or starting points, different values for R2 and RREF will be needed, but the same basic procedure applies.
-------- = exp ----------------kT
qVBE
(1)
When numerical values for q/kT are put into this equation, it is found that a VBE of 59mV (at +25oC) is required to change the collector current ratio by a factor of ten. But for ease of application, it is desirable that a 1V change at the input generate a tenfold change at the output. The required input attenuation is achieved by the network comprising R1 and R 2. In order that scale factors other than one decade per volt may be selected, R2 is external to the chip. It should have a value of 1k, adjustable 20%, for one decade per volt. R1 is a thin film resistor deposited on the monolithic chip; its temperature characteristics are chosen to compensate the temperature dependence of Equation 1, as explained on the previous page. The overall transfer function is as follows:
I OUT --------- = I REF ex p
--------------------- x -------kT ( R1 + R2 )
-R 2
qV IN
(2)
Substituting VOUT = IOUT x ROUT gives: -R2 qV IN V OUT = R OUT IREF exp ------------------------ x -----------kT ( R1 + R2 ) (3)
3

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