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74AC821 * 74ACT821 10-Bit D-Type Flip-Flop with 3-STATE Outputs
November 1988 Revised August 2000
74AC821 * 74ACT821 10-Bit D-Type Flip-Flop with 3-STATE Outputs
General Description
The AC/ACT821 is a 10-bit D-type flip-flop with 3-STATE outputs arranged in a broadside pinout.
Features
s 3-STATE outputs for bus interfacing s Noninverting outputs s Outputs source/sink 24 mA s TTL compatible inputs
Ordering Code:
Order Number 74AC821SC 74AC821SPC 74ACT821SC 74ACT821MTC 74ACT821SPC Package Number M24B N24C M24B MTC24 N24C Package Description 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code. (SPC not available in Tape and Reel.)
Logic Symbols
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names D0-D9 O0-O9 OE CP Description Data Inputs Data Outputs Output Enable Input Clock Input
FACT is a trademark of Fairchild Semiconductor Corporation.
(c) 2000 Fairchild Semiconductor Corporation
DS010139
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74AC821 * 74ACT821
Functional Description
The AC/ACT821 consists of ten D-type edge-triggered flipflops. The buffered Clock (CP) and buffered Output Enable (OE) are common to all flip-flops. The flip-flops will store the state of their individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH CP transition. With OE LOW the contents of the flip-flops are available at the outputs. When OE is HIGH the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flip-flops.
Function Table
Inputs OE H H L L
H = HIGH Voltage Level L = LOW Voltage Level Z = HIGH Impedance = LOW-to-HIGH Clock Transition
Internal D L H L H Q L H L H
Outputs Function O Z Z L H High Z High Z Load Load
CP

Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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74AC821 * 74ACT821
Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC) DC Input Diode Current (IIK) VI = - 0.5V VI = VCC + 0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO = -0.5V VO = VCC + 0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current per Output Pin (ICC or IGND) Storage Temperature (TSTG) Junction Temperature (TJ) PDIP 140C
- 0.5V to + 7.0V - 20 mA + 20 mA - 0.5V to VCC + 0.5V - 20 mA + 20 mA - 0.5V to VCC + 0.5V 50 mA 50 mA - 65C to + 150C
Recommended Operating Conditions
Supply Voltage (VCC) AC ACT Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) Minimum Input Edge Rate (V/t) AC Devices VIN from 30% to 70% of VCC VCC @ 3.3V, 4.5V, 5.5V Minimum Input Edge Rate (V/t) ACT Devices VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V 125 mV/ns
Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications.
2.0V to 6.0V 4.5V to 5.5V 0V to VCC 0V to VCC
- 40C to + 85C
125 mV/ns
DC Electrical Characteristics for AC
Symbol VIH Parameter Minimum HIGH Level Input Voltage VIL Maximum LOW Level Input Voltage VOH Minimum HIGH Level Output Voltage VCC (V) 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 VOL Maximum LOW Level Output Voltage 3.0 4.5 5.5 3.0 4.5 5.5 IIN (Note 4) IOZ Maximum Input Leakage Current Maximum 3-STATE Current 5.5 IOLD IOHD ICC (Note 4) Minimum Dynamic Output Current (Note 3) Maximum Quiescent Supply Current 5.5 5.5 5.5 8.0 0.5 5.0 75 -75 80.0 A mA mA A 5.5 0.002 0.001 0.001 TA = +25C Typ 1.5 2.25 2.75 1.5 2.25 2.75 2.99 4.49 5.49 2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4 2.56 3.86 4.86 0.1 0.1 0.1 0.36 0.36 0.36 0.1 TA = -40C to +85C Guaranteed Limits 2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4 VIN = VIL or VIH 2.46 3.76 4.76 0.1 0.1 0.1 VIN = VIL or VIH 0.44 0.44 0.44 1.0 A V IOL = 12 mA IOL = 24 mA IOL = 24 mA (Note 2) VI = VCC, GND VI (OE) = V IL, VIH VI = VCC, GND VO = VCC, GND VOLD = 1.65V Max VOHD = 3.85V Min VIN = VCC or GND V IOUT = 50 A V IOH = - 12 mA IOH = - 24 mA IOH = - 24 mA (Note 2) V IOUT = - 50 A V VOUT = 0.1V or VCC - 0.1V V Units Conditions VOUT = 0.1V or VCC - 0.1V
Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time. Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC.
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74AC821 * 74ACT821
DC Electrical Characteristics for ACT
Symbol VIH VIL VOH Parameter Minimum HIGH Level Input Voltage Maximum LOW Level Input Voltage Minimum HIGH Level Output Voltage VCC (V) 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 VOL Maximum LOW Level Output Voltage 4.5 5.5 4.5 5.5 IIN (Note 4) IOZ ICCT IOLD IOHD ICC Maximum Input Leakage Current Maximum 3-STATE Current Maximum ICC/Input Minimum Dynamic Output Current (Note 6) Maximum Quiescent Supply Current 5.5 5.5 5.5 5.5 5.5 5.5 8.0 0.6 0.001 0.001 TA = +25C Typ 1.5 1.5 1.5 1.5 4.49 5.49 2.0 2.0 0.8 0.8 4.4 5.4 3.86 4.86 0.1 0.1 0.36 0.36 0.1 0.5 TA = -40C to +85C Guaranteed Limits 2.0 2.0 0.8 0.8 4.4 5.4 3.76 4.76 0.1 0.1 0.44 0.44 1.0 5.0 1.5 75 -75 80.0 A A mA mA mA A V Units V V V Conditions VOUT = 0.1V or VCC - 0.1V VOUT = 0.1V or VCC - 0.1V IOUT = - 50 A VIN = VIL or VIH V IOH = - 24 mA IOH = - 24 mA (Note 5) IOUT = 50 A VIN = VIL or VIH V IOL = 24 mA IOL = 24 mA (Note 5) VI = VCC, GND VI = VIL, VIH VO = VCC, GND VI = VCC - 2.1V VOLD = 1.65V Max VOHD = 3.85V Min VIN = VCC or GND
Note 5: All outputs loaded; thresholds on input associated with output under test. Note 6: Maximum test duration 2.0 ms, one output loaded at a time.
AC Electrical Characteristics for AC
VCC Symbol fMAX tPLH tPHL tPZH tPZL tPHZ tPLZ Parameter Maximum Clock Frequency Propagation Delay CP to On Propagation Delay CP to On Output Enable Time OE to On Output Enable Time OE to On Output Disable Time OE to On Output Disable Time OE to On
Note 7: Voltage Range 3.3 is 3.3V 0.3V Voltage Range 5.0 is 5.0V 0.5V
TA = +25C CL = 50 pF Min 110 120 3.0 2.0 3.0 2.0 2.5 1.5 2.5 1.5 2.5 1.5 2.5 1.5 Typ 145 160 8.0 6.0 8.0 5.5 6.0 4.5 6.5 5.0 6.5 5.0 6.0 4.5 13.0 9.5 13.0 9.5 11.0 8.0 11.0 8.0 10.5 8.0 10.5 8.0 Max
TA = -40C to +85C CL = 50 pF Min 100 110 3.0 2.0 3.0 2.0 2.5 1.5 2.5 1.5 2.5 1.5 2.5 1.5 15.0 10.5 15.0 10.5 12.0 9.0 12.0 9.0 11.0 8.5 11.0 8.5 Max MHz ns ns ns ns ns ns Units
(V) (Note 7) 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0
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74AC821 * 74ACT821
AC Operating Requirements for AC
VCC Symbol tS tH tW Parameter Setup Time, HIGH or LOW Dn to CP Hold Time, HIGH or LOW Dn to CP CP Pulse Width HIGH or LOW
Note 8: Voltage Range 3.3 is 3.3V 0.3V Voltage Range 5.0 is 5.0V 0.5V
TA = +25C CL = 50 pF Typ -1.0 -1.0 -1.0 -1.0 3.5 2.5 1.5 1.5 3.5 3.5 5.0 4.0
TA = -40C to +85C CL = 50 pF Guaranteed Minimum 1.5 1.5 4.0 4.0 5.5 4.0 ns ns ns Units
(V) (Note 8) 3.3 5.0 3.3 5.0 3.3 5.0
AC Electrical Characteristics for ACT
VCC Symbol Parameter (V) (Note 9) fMAX tPLH tPHL tPZH tPZL tPHZ tPLZ Maximum Clock Frequency Propagation Delay CP to On Propagation Delay CP to On Output Enable Time OE to On Output Enable Time OE to On Output Disable Time OE to On Output Disable Time OE to On
Note 9: Voltage Range 5.0 is 5.0V 0.5V
TA = +25C CL = 50 pF Min 120 2.0 2.5 2.5 2.5 1.5 1.5 Typ 150 6.0 6.0 7.0 7.0 7.5 7.0 9.5 9.5 10.5 10.5 12.0 10.5 Max
TA = -40C to +85C CL = 50 pF Min 110 1.5 2.0 2.0 2.0 1.0 1.0 10.5 10.5 11.5 12.0 13.0 11.5 Max MHz ns ns ns ns ns ns Units
5.0 5.0 5.0 5.0 5.0 5.0 5.0
AC Operating Requirements for ACT
VCC Symbol tS tH tW Parameter Setup Time, HIGH or LOW Dn to CP Hold Time, HIGH or LOW Dn to CP CP Pulse Width HIGH or LOW
Note 10: Voltage Range 5.0 is 5.0V 0.5V
TA = +25C CL = 50 pF Typ 2.5 -0.5 3.0 2.0 2.0 4.5
TA = -40C to +85C CL = 50 pF Guaranteed Minimum 2.5 2.5 5.5 ns ns ns Units
(V) (Note 10) 5.0 5.0 5.0
Capacitance
Symbol CIN CPD Parameter Input Capacitance Power Dissipation Capacitance Typ 4.5 35.0 Units pF pF VCC = OPEN VCC = 5.0V Conditions
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74AC821 * 74ACT821
Physical Dimensions inches (millimeters) unless otherwise noted
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M24B
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74AC821 * 74ACT821
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC24
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74AC821 * 74ACT821 10-Bit D-Type Flip-Flop with 3-STATE Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N24C
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 8 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

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