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E2I0029-17-Y1 Semiconductor
Semiconductor MSM521218
65,536-Word 18-Bit CMOS STATIC RAM
This version: Jan. 1998 MSM521218 Previous version: Aug. 1996
Pr el im in ar y
DESCRIPTION
The MSM521218 is a 65,536-word by 18-bit CMOS fast static RAM featuring a single 3.3 V power supply operation and direct LVTTL input/output compatibility. Since the circuitry is completely static, external clock and refreshing operations are unnecessary, making this device very easy to use. The MSM521218 can be used in the high-speed operation of an access time 20 ns due to adopting a high-performance CMOS technology. In addition, the MSM521218 is provided with a chip enable signal (CE) suited to the power-down function, an output enable signal (OE) suited to the I/O bus line control, and a byte select signal (LB, UB) that can independently control the input/output of a lower byte and an upper byte.
FEATURES
* 65,536-word 18-bit configuration * Single 3.3 V power supply * Fully static operation * Operating temperature range: Ta = 0C to 70C * Power dissipation Standby: 2 mA (Max.) Operation: - 20 230 mA (Max.) - 25 210 mA (Max.) - 30 190 mA (Max.) * Access time: - 20 20 ns (Max.) - 25 25 ns (Max.) - 30 30 ns (Max.) * (Input/Output) LVTTL compatible * Power-down function by chip enable signal * 3-state output * Lower and upper bytes can be controlled independently * Package: 44-pin 400 mil plastic TSOP (Type II) (TSOPII44-P-400-0.80-K) (Product : MSM521218-xxTS-K) xx indicates speed rank.
PRODUCT FAMILY
Family MSM521218-20 MSM521218-25 MSM521218-30 Access Time (Max.) 20 ns 25 ns 30 ns 400 mil 44-pin TSOP(II) Package
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Semiconductor
PIN CONFIGURATION (TOP VIEW)
A4 1 A3 2 A2 3 A1 4 A0 5 CE 6 I/O1 7 I/O2 8 I/O3 9
,
44-Pin Plastic TSOP (II) (K Type)
Pin Name A0 - A15 I/O1 - I/O18 CE WE OE LB, UB VCC, VSS NC Function Address Input Data Input/Output Chip Enable Write Enable Output Enable Byte Data Select Power Supply No Connection
MSM521218
44 A5 43 A6 42 A7 41 OE 40 UB 39 LB 38 I/O18 37 I/O17 36 I/O16 35 I/O15 34 VSS 33 VCC 32 I/O14 31 I/O13 30 I/O12 29 I/O11 28 I/O10 27 NC 26 A8 25 A9 24 A10 23 A11
I/O4 10 VCC 11 VSS 12 I/O5 13 I/O6 14 I/O7 15 I/O8 16 I/O9 17 WE 18 A15 19 A14 20 A13 21 A12 22
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Semiconductor
MSM521218
BLOCK DIAGRAM
A11 A12 A13 A14 A15 A5 A6 A7 I/O1 : : I/O9 I/O10 : : I/O18
Row Select
Memory Array 256 Rows 256 Columns 18 Blocks
V CC V SS
Input Data Control
Column I/O Circuits Column Select
A0 A1
A2 A3
A4 A8
A9 A10
: WE CE LB UB OE :
FUNCTION TABLE
Operating Mode Non Selectable CE H L L Read Cycle L L L L Write Cycle L L L WE X H H H H H L L L L OE X H L L L L X X X X LB X X L L H H L L H H UB X X L H L H L H L H I/O1 - I/O9 High-Z High-Z Data Read Data Read High-Z High-Z Data Write Data Write High-Z High-Z I/O10 - I/O18 High-Z High-Z Data Read High-Z Data Read High-Z Data Write High-Z Data Write High-Z Power Mode Standby Active Active Active Active Active Active Active Active Active
*Don't Care ("H" or "L")
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Semiconductor
MSM521218
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter Power Supply Voltage Pin Voltage Power Dissipation Operating Temperature Storage Temperature Symbol VCC VT PD Topr Tstg Condition Ta = 25C, for VSS Ta = 25C -- -- Rating -0.5 to 4.6 -0.5* to VCC + 0.5 1.0 0 to 70 -55 to 125 Unit V V W C C
* -2.0 V Min. for pulse width less than 10 ns. Recommended Operating Conditions
Parameter Power Supply Voltage Input High Voltage Input Low Voltage Load Capacitance Symbol VCC VSS VIH VIL CL Condition -- VCC = 3.3 V 0.3 V -- Min. 3.0 0 2.0 -0.3* -- Typ. 3.3 0 -- -- -- Max. 3.6 0 VCC + 0.3 0.8 30 Unit V V V V pF
* -2.0 V Min. for pulse width less than 10 ns. Capacitance
(Ta = 25C, f = 1 MHz) Parameter Input Capacitance Input/Output Capacitance Symbol CI CI/O Condition VIN = 0 V VI/O = 0 V Min. -- -- Max. 8 8 Unit pF pF
Note:
This parameter is periodically sampled and not 100% tested.
4/11
Semiconductor DC Characteristics
Parameter Input Leakage Current Symbol ILI Condition VIN = 0 to VCC CE = VIH or OE = VIH or WE = VIL or UB = VIH or LB = VIH, VOUT = 0 to VCC IOH = -2.0 mA IOL = 2.0 mA CE VCC - 0.2 V, VIN 0.2 V or VIN VCC - 0.2 V CE = VIH, Min. cycle CE = VIL, Min. cycle, IOUT = 0 mA
MSM521218
(VCC = 3.3 V 0.3 V, Ta = 0C to 70C) Min. -10 MSM521218 Typ. Max. -- 10 Unit mA
Output Leakage Current
ILO
-10
--
10
mA
Output High Voltage Output Low Voltage Standby Power Supply Current
VOH VOL ICCS ICCS1
2.4 -- -- -- --
-- -- -- -- --
-- 0.4 2 20 q
V V mA mA mA 230 mA 210 mA 190 mA
Operating Power Supply Current
ICCA
q 521218-20 521218-25 521218-30
AC Characteristics Test Conditions
Parameter Input Pulse Level Input Rise and Fall Times Input/Output Timing Level Output Load Condition VIH = 3 V, VIL = 0 V 3 ns 1.4 V See Figures
1.4 V 500 W DOUT 30 pF (Including scope and jig) DOUT
1.4 V 500 W
5 pF (Including scope and jig)
Figure 1 Output Load
Figure 2 Output Load (tOLZ, tOHZ, tCLZ, tCHZ, tLBLZ, tLBHZ, tUBLZ, tUBHZ, tWLZ, tWHZ)
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Semiconductor Read Cycle
MSM521218
(VCC = 3.3 V 0.3 V, Ta = 0C to 70C) MSM521218-20 Parameter Read Cycle Time Address Access Time CE Access Time OE Access Time LB, UB Access Time CE to Output in Low-Z OE to Output in Low-Z LB, UB to Output in Low-Z Output Hold Time from Address Change CE to Output in High-Z OE to Output in High-Z LB, UB to Output in High-Z Symbol tRC tAA tCO tOE tLB, tUB tCLZ tOLZ tLBLZ, tUBLZ tOH tCHZ tOHZ tLBHZ, tUBHZ Min. 20 -- -- -- -- 3 0 0 3 -- -- -- Max. -- 20 20 10 10 -- -- -- -- 8 8 8 MSM521218-25 Min. 25 -- -- -- -- 3 0 0 3 -- -- -- Max. -- 25 25 12 12 -- -- -- -- 10 10 10 MSM521218-30 Min. 30 -- -- -- -- 3 0 0 3 -- -- -- Max. -- 30 30 15 15 -- -- -- -- 12 12 12 Unit ns ns ns ns ns ns ns ns ns ns ns ns
Address Controlled Read (WE = H, CE = L, OE = L, LB = L or UB = L)
tRC ADDRESS tAA tOH DOUT Dataout Valid
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, ,
Semiconductor MSM521218 CE, OE, LB, UB Controlled Read (WE = H)
tRC ADDRESS tAA tCHZ CE tCO tCLZ OE tOE tOHZ LB, UB tOLZ tLB, tUB tLBHZ, tUBHZ DOUT Dataout Valid tLBLZ, tUBLZ tOH
Notes :
1. A read cycle occurs during the overlap of CE = "L", OE = "L", LB = "L" (or UB = "L") and WE = "H". 2. tCHZ, tOHZ, tLBHZ and tUBHZ are specified by the time when DATA is floating, not defined by the output level.
7/11
Semiconductor Write Cycle
Parameter Write Cycle Time Address Setup Time Write Pulse Width Write Recovery Time Data Setup Time Data Hold Time WE to Output in High-Z CE to End of Write Symbol tWC tAS tWP tWR tDS tDH tWHZ tCW tAW
MSM521218
(VCC = 3.3 V 0.3 V, Ta = 0C to 70C) MSM521218-20 MSM521218-25 MSM521218-30 Min. 20 0 15 0 10 0 -- 15 15 0 Max. -- -- -- -- -- -- 8 -- Min. 25 0 20 0 12 0 -- 20 Max. -- -- -- -- -- -- 10 -- Min. 30 0 25 0 14 0 -- 25 Max. -- -- -- -- -- -- 12 -- Unit ns ns ns ns ns ns ns ns
, ,
Address Valid to End of Write LB, UB to End of Write 15 -- 20 0 -- 25 0 -- ns tLBW, tUBW tWLZ -- 20 -- 25 -- ns Output Active from End of Write -- -- -- ns
WE Controlled Write (OE = L)
tWC
ADDRESS
tCW
CE
tAW
WE
tAS
tWP
tWR
tLBW, tUBW
LB, UB
tWLZ
DOUT
tDS
tDH
tWHZ
DIN
Data In
8/11
Semiconductor CE Controlled Write (OE = H)
tWC ADDRESS tAS CE tCW
MSM521218
WE
LB, UB
DIN
DOUT
LB, UB Controlled Write (OE = H)
ADDRESS
CE
WE
LB, UB
DIN
DOUT
,,,,
tAW tWR tWP tLBW, tUBW tDS tDH Data In High Impedance tWC tAW tCW tWP tAS tLBW, tUBW tWR tDS tDH Data In High Impedance
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Semiconductor Notes:
MSM521218
1. A write cycle occurs during the overlap of CE = "L", WE = "L" and LB = "L" (or UB = "L"). 2. OE may be either of "H" or "L" in the write cycle. 3. tAS is specified from CE = "L", WE = "L" or LB = "L" (or UB = "L") whichever occurs last. 4. tWP is an overlap time of CE = "L", WE = "L" and LB = "L" (or UB = "L"). 5. tWR, tDS and tDH are specified from CE = "H", WE = "H" or LB = "H" (or UB = "H") whichever occurs first. 6. tWHZ is specified by the time when DATA output is floating, not defined by the output level. 7. When I/O pins are in the output mode, don't apply the inverted input signal to the output pins.
10/11
Semiconductor
MSM521218
PACKAGE DIMENSIONS
(Unit : mm)
TSOPII44-P-400-0.80-K
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 0.54 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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