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| PMC-Sierra, Inc. STANDARD PRODUCT ISSUE 2 PM5543 SARD SONET/SDH 155Mbit/s ADM Reference Design PM5543 ADM155_REF SONET/SDH 155 Mbit/s ADD/DROP MULTIPLEXOR WITH SINGLE MODE OPTICAL INTERFACE REFERENCE DESIGN (SARD) Issue 2: July, 1996 PMC-Sierra, Inc. 105 8555 Baxter Place, Burnaby, BC Canada V5A 4V7, 604 415 6000 PMC-Sierra, Inc. STANDARD PRODUCT ISSUE 2 PM5543 SARD SONET/SDH 155Mbit/s ADM Reference Design TABLE OF CONTENTS FEATURES................................................................................................... 1 OVERVIEW .................................................................................................. 2 FUNCTIONAL DESCRIPTION ..................................................................... 4 PM5101 Motherboard Interface ............................................................ 5 Optical Interface.................................................................................... 5 CY7B951 .............................................................................................. 5 Reference Clock ................................................................................... 6 System Clock........................................................................................ 6 STXC .................................................................................................... 6 SPTX ................................................................................................... 7 TUPP & TUPP-Plus .............................................................................. 8 TUDX ................................................................................................... 10 Timing Control ..................................................................................... 11 Ring Expansion Interface ....................................................................12 Mapper Interface ................................................................................. 12 LED Displays ....................................................................................... 13 Configuration Headers/Jumpers .......................................................... 13 INTERFACE SIGNAL DESCRIPTION ........................................................14 Microprocessor Interface (Connector P1) ............................................ 14 Microprocessor Interface Signal Description. ......................................14 Decoded Microprocessor Signal to Stel/ar chipset Interface ............... 15 Prototyping Jumper Interface ..............................................................17 SPTX ADD Bus Clock & Signal Select Interface ................................. 18 HP SDX1155 Optics to/from Cypress CY7B951 Interface .................. 19 Cypress CY7B951 to/from STXC Interface ......................................... 20 STXC to/from SPTX Interface..............................................................20 SPTX to/from TUPP/TUPP-Plus Interface........................................... 21 SPTX to/from TIMING CONTROL(TC) block Interface ....................... 21 TUPP/TUPP-Plus to/from TUDX1 Interface ........................................ 21 TUPP/TUPP-Plus to/from TUDX2 Interface ........................................ 22 TUPP from TIMING CONTROL(TC) Interface .................................... 22 i PMC-Sierra, Inc. STANDARD PRODUCT ISSUE 2 PM5543 SARD SONET/SDH 155Mbit/s ADM Reference Design TUDX1 from TIMING CONTROL(TC) Interface .................................. 23 TUDX2 from TIMING CONTROL(TC) Interface .................................. 23 19.44MHz System Clock Distribution Interface ...................................23 TIMING CONTROL(TC) Interface ....................................................... 23 Ring Expansion Interface ....................................................................24 Mapper Interface ................................................................................. 26 STXC and TUPP-Plus Status LED Display ......................................... 29 SPTX status LED Display ....................................................................29 SOFTWARE INTERFACE DESCRIPTION ................................................. 30 SARD General Registers..................................................................... 31 STXC Registers ................................................................................... 33 SPTX Registers ................................................................................... 34 TUPP & TUPP-Plus Registers............................................................. 36 TUDX1 Registers................................................................................. 38 TUDX2 Registers................................................................................. 38 On Board PROM ......................................................................................... 40 D.C. CHARACTERISTICS .......................................................................... 53 REFERENCES ............................................................................................54 APPENDIX 1: SPECIAL LAYOUT CONSIDERATIONS ............................. 55 High Speed Signal Termination ...........................................................55 Trace Impedance Control .................................................................... 55 Routing ................................................................................................ 57 Termination.......................................................................................... 57 Power and Ground Plane Noise Decoupling ....................................... 59 APPENDIX 2: BILL OF MATERIAL ............................................................. 61 APPENDIX 3: SCHEMATICS ...................................................................... 65 APPENDIX 4: OTHER LAYOUT DRAWINGS............................................. 66 ii PMC-Sierra, Inc. STANDARD PRODUCT ISSUE 2 PM5543 SARD SONET/SDH 155Mbit/s ADM Reference Design FEATURES * Receives an OC-1/OC-3 optical signal and processes section, line and path SONET overhead. * Performs arbitrary tributary cross-connection to produce a byte serial STS-1, STS-3 (STM-1, AU3), STS-3c (STM-1, AU4) signal. * Transmits an OC-1/OC-3 [STS-1/STS-3 (STM-1)] stream with an option to overwrite all section, line and path overhead. * Provides for loop back of both line-side and drop-side signals. * Recovers line-side receive signal clock. * Drop-side receive clock may be pleisiochronous to the line-side receive clock. * Provides on board line-side transmit clock synthesis. * Drop-side transmit clock may be pleisiochronous to the line-side transmit clock. * Optionally translates received pointer justification events at the SPE level to tributary pointer justifications, thus locking the SONET SPE to accomplish tributary switching. * Optionally cross-connects tributaries mapped in the receive stream to any arbitrary time slots in the drop-side stream. * Allows broadcasting of tributaries over multiple tributaries. * Provides line side OC-1/OC-3 transmit and receive signals on SC type optical single mode connectors. * Provides an interface to a proprietary external mapping-demapping function via a 100-pin connector. * Provides a 100-pin connector for ring expansion and ring control for connection to another PM5543 SARD board. * Provides a 132-pin connector for microprocessor interface to a PM1501 EVMB motherboard. 1 PMC-Sierra, Inc. STANDARD PRODUCT ISSUE 2 PM5543 SARD SONET/SDH 155Mbit/s ADM Reference Design OVERVIEW The SONET/SDH 155 Mbit/s Add-Drop Multiplexor Single Mode Optical Reference Design allows for the evaluation, and demonstration of the PMC SONET/SDH adddrop multiplexor chipset. This reference design illustrates how to implement the front end optics and clock/ data recovery using the CY97B951 and the HP SDX1155 single mode transceiver. This design has been especially designed to mate with itself, the PMC PM1501 EVMB evaluation motherboard and an asynchronous system mapper/demapper daughter board (as yet unspecified) to form a complete add drop node for use in an ADM ring network. This document describes the function of this reference design and also provides complete layout information so that it can be easily duplicated or used as a part of another proprietary design. This board utilizes four of the five PMC's Stel/ar (SONET Telecom Architecture) chipset together with the commercially available HP optical transceiver and the Cypress CY7B951 to make up a complete ADM ring node element. The SONET/SDH transport overhead, pointer processing (at the SONET/SDH SPE and VT/TU level) and tributary cross connection are completely handled by the Stel/ar chipset; the section and line is handled by the SONET/SDH Transport Overhead Transceiver (STXC), the path overhead and SPE pointer interpretation is handled by the SONET/SDH Path Overhead Terminating Transceiver (SPTX), the SPE pointer justifications are translated to VT/TU level justifications by the SONET/SDH Tributary Unit Payload Processor (TUPP or TUPP-Plus) and the tributary cross connection is handled by the SONET/SDH Tributary Unit Cross-Connect (TUDX1 and TUDX2). In the receive direction, the HP optical transceiver receives the OC-1 (or OC-3) optical signal and performs optical to electrical conversion to a differential serial STS1 (or STS-3) stream. This serial stream is processed by the CY7B951 to extract clock and data before they are passed on to the inputs of the STXC. The STXC performs serial to parallel conversion and terminates the section and line transport overhead and passes the byte serial data to the SPTX. Besides termination of the path overhead, the SPTX supports decoupling of the line side synchronous timing to the system side synchronous timing, the differing rates (19.44MHz 20ppm) being adapted by SPE pointer justifications. Received pointer justifications at the system side are compensated by tributary pointer justifications while allowing the SPE envelope to be locked at offset 522 using the TUPP device or at an offset of 0 or 522 using the TUPP-Plus. The data outputs from the TUPP/TUPP-Plus are directly connected to the data inputs of the tributary cross-connect device, TUDX2. The TUPP/TUPP-Plus tributary SPE and tributary V5 position signals, OTSPE and OTV5 respectively, are sent to another TUDX, TUDX1 and TUPP-Plus OTPOH, AIS, IDLE, LC1J1V1, LPL and COUT signals also to be sent to TUDX1. These tributary and frame signals are cross-connected to arbitrary time slots by the two TUDX devices and the cross connected frame is presented to the ADD/DROP Mapper I/F or the Ring Expansion I/F for possible processing by an external mapper or second ADM function. 2 PMC-Sierra, Inc. STANDARD PRODUCT ISSUE 2 PM5543 SARD SONET/SDH 155Mbit/s ADM Reference Design In the transmit direction, the reverse process to the receive direction is implemented. The SPTX receives an STS-3 (STM-1) or STS-1 byte serial stream from either the on board TUDX cross connect or the Ring Expansion Interface and inserts the path overhead. The STXC serializes the data to STS-1 or STS-3 rate and transfers the data to the HP optics via the cypress CY7B951. The OC-1/OC-3 signal is then transmitted out to the line. The SARD board requires an external evaluation motherboard (PM1501 EVMB) for configuration and control. The PM1501 EVMB Evaluation Motherboard, based on a 68HC11 microcontroller, provides processing and communication capability with the daughterboard. The SARD board is connected with the microprocessor motherboard through a 96-pin edge connector. The microcontroller can be connected to a VT100-type terminal through an RS-232 interface. For details on the operation of the Stel/ar chips or the PM1501 microprocessor motherboard, please consult their respective data sheets as listed in the reference section at the end of this document. 3 ISSUE 2 STANDARD PRODUCT PM1501 EVBD MOTHERBOARD ADDRESS [C200-C2FF] ADDRESS [A000-AFFF] ADDRESS [C300-C4FF] ADDRESS [9000-9FFF] MICROPROCESSOR INTERFACE ADDRESS [C600-C6FF] ADDRESS [C700-C7FF] LED DISPLAY 19.44MHz CLOCK (CMOS) SCLK TUDX1 DINT[0] DINT[1] DOUTL[0] DINT[6] DINT[7] DOUTL[8] SFP OTV5 PM5362 OTPL TUPP+ LC1J1 LPL POH[3:1], POHFP[3:1], POHEN[3:1] IC1J1 IPL OPL ID[7:0] OC1J1 DDP IDP LPL OTMF LC1J1V1 TOUT+/TSER+/TCLK+/TXD+/TXCI+/OD[7:0]/ODP POHCK, RAD COUTL LED DISPLAY PM5371 FUNCTIONAL DESCRIPTION 19.44MHz Ref.CLOCK (ECLFP5Q) OC-3/OC-1 OPTICAL SIGNAL GTICLK TCK DC1J1V1 FPOUT TD[7:0] DD[7:0] DPL DCK REFCLK+/MODE LOOPB TIN[7:0] SCPO[0] SCPO[1] TICLK TIFP SCLK MAPPER INTERFACE ROUT[7:0] RD[7:0] J3 J3 AD[7:0]/ADP J3 J4 APL AC1J1V1 SARD Block Diagram CY7B951 RIN+/CD GRICLK PICLK IFP ACK RICLK ROFP DIN[7:0] LFIB RSER J1 J2 DFP DC1J1V1 DPL DFP RCLK+/RSER+/RXC+/RXD+/OTMF APL OC1J1 OC1 ADD/DROP MAPPER BOARD 4 PM5343 STXC PM5344 SPTX TIMING CONTROL AC1J1V1 RRCPFP/ RRCPDAT/ RRCPCLK RAD/ RPOHFP[1]/ RPOHCK[1] TAD/ TAFP/ TACK TRCPFP/ TRCPDAT/ TRCPCLK WEST TRAFFIC TRANSMIT TD+/FIBER HP SDX1155 PM5371 TUDX2 SCLK DINB[8:0] DINT[8:0] DOUTL[8:0] SFP COUTL DOUTR[8:0] PMC-Sierra, Inc. EAST TRAFFIC RECEIVE RD+/FIBER SD LOOP BACK SELECT HEADERS RING EXPANSION INTERFACE ABC D EFGH PM5543 SARD SONET/SDH 155Mbit/s ADM Reference Design ADM BOARD PMC-Sierra, Inc. STANDARD PRODUCT ISSUE 2 PM5543 SARD SONET/SDH 155Mbit/s ADM Reference Design PM5101 Motherboard Interface The micro control Interface includes all the interface logic required to connect to a standard PMC PM1501 EVMB evaluation motherboard. Bus buffers and transceivers are provided at the interface to reduce loading on the PM1501 EVBD's 68HC11 microprocessor and to increase the drive capability of the interface. Decode logic provides memory mapped access to all of the on board PMC-Sierra Stel/ar devices ( STXC, SPTX, TUPP/TUPP-Plus TUDX1 and TUDX2) and all board level registers. Three read/write registers are provided to control the STXC, SPTX, TUPP/TUPP-Plus , TUDX1 and TUDX2 devices. One of these registers is reserved for future use. The second one is dedicated to the STXC and TIMING CONTROL blocks and is used to control the configuration of these blocks. The third one is a general software reset register used for resetting any device on an individual basis. Optical Interface The optical interface consists of the HP SDX1155 intermediate reach (approximately 16 dB per link loss at 1.3 m wavelength) single mode optical transceiver. This device is interchangeable with any multisourced 1X9 pin (lower or higher power) transceiver, or multimode LED transceiver for short haul applications. This reference design is not designed for the long reach separate optical receiver and transmitter modules available today. For long reach designs the layout must be changed to accompany the different footprints of the separate optics pair. However, it is expected that a long reach optical transceiver compatible with the footprint on this board will be available in the near future. In the receive direction, the HP SDX1155 converts the OC-1 or OC-3 optical signal to a two-level (NRZ) bit serial electrical data stream at the STS-1 or STS-3(STM-1) rate. In the transmit direction, the HP SDX1155 takes the bit serial STS-1 or STS-3 signal and modulates the laser output as an OC-1 or OC-3 optical data stream. The optical transceiver uses dual SC/PC type connector. CY7B951 The Cypress SONET/SDH Serial Transceiver (CY7B951) contains integrated clock and data recovery and clock synthesis. The internal receive PLL recovers a 155.52MHz or a 51.84MHz clock from an incoming NRZ or NRZI data. The differential input data is re-timed by the recovered clock and is presented as a differential PECL bit serial data output. The receive PLL requires a 19.44MHz reference clock to provide a 155.52MHz or 51.84MHz clock in the absence of input data. The reference clock is also used to improve the PLL lock time by training to the approximate frequency of the incoming data stream during optical LOS. 5 PMC-Sierra, Inc. STANDARD PRODUCT ISSUE 2 PM5543 SARD SONET/SDH 155Mbit/s ADM Reference Design The transmit section of the Cypress (CY7B951) SONET/SDH Serial Transceiver contains a PLL that takes a reference clock and multiplies it by 8 to produce a 155.52MHz or 51.84MHz PECL differential output clock. This clock is used by the STXC to transmit PECL differential data. The PECL data from the STXC is then buffered by the CY7B951 before interfacing to the optics. Reference Clock The 19.44MHz reference is an ECL oscillator required for clock and data recovery by the CY7B951. The receive PLL of the CY7B951 utilizes this clock to generate a 155.52MHz or 51.84MHz clock in the absence of input data. Also, the CY7B951 synthesizes a 155.52MHz or 51.84MHz clock for the timing of the transmit bit serial stream. This clock is used by the STXC's TXCI input to time the output bit serial data stream on its TXD+/- outputs. The reference clock is also used to improve the PLL lock time inside the CY7B951. System Clock A TTL/CMOS level clock is used as a byte serial system clock to drive the SPTX (drop side), TUPP/TUPP-Plus, TUDX1 and TUDX2 circuitry. This clock also accompanies the data sent out on the Mapper Interface and the Ring Expansion Interface. STXC The PM5343 SONET/SDH Transport Overhead Transceiver (STXC) processes the transport overhead (section and line overhead) of an STS-1 or STS-3 (STM-1) stream. The STXC operates to implement SONET/SDH-compliant line interfaces. The STXC processes either byte serial data at 6.48 Mbyte/s (STS-1) or 19.44 Mbyte/s (STS-3, STM-1), or bit serial data at 51.84 Mbits/s (STS-1) or 155.52 Mbits/s (STS-3, STM-1) on the line side depending on the mode selected. In this design, the STXC implements the bit serial interface only during normal operation. When the optics and clock recovery front end detect a loss of light condition, the STXC is automatically configured to select the byte serial parallel interface. Because of the parallel interface input is tied to ground, the STXC receives all "0". Then the LOS is claimed. The 19.44 MHz RICLK clock input is also switched from the receive sourced clock GRICLK to the transmit sourced clock GTICLK. This allows the STXC to guarantee the detection of an LOS state. Otherwise the parallel interface is not utilized. On the system side, the STXC either expects or outputs an STS-1 or an STS-3 (STM-1) byte serial stream as determined by the selected operating mode during Stel/ar device programming. In the receive direction, the STXC frames to the incoming stream, optionally descrambles the receive stream, calculates and compares the bit interleaved parity 6 PMC-Sierra, Inc. STANDARD PRODUCT ISSUE 2 PM5543 SARD SONET/SDH 155Mbit/s ADM Reference Design error detection codes (B1, B2) and accumulates BIP-8 errors (B1, B2) and retransmits the B2 errors as FEBE indications (Z2). Loss of signal (LOS), out of frame (OOF), loss of frame (LOF), far end receive failure (FERF), line alarm indication signal (AIS), and protection switching byte failure alarms are detected. In addition to extracting the entire transport overhead on a dedicated output port, the STXC also extracts and serializes the order wire channels (E1, E2), the data communication channels (D1-D3, D4-D12), the section user channel (F1) and the APS bytes (K1, K2) on their own dedicated output ports. In the transmit direction, the STXC internally generates all transport overhead bytes with the exception of the H1, H2 and H3 bytes and inserts them into the outgoing SONET stream. Transport overhead bytes can also be inserted using a dedicated transport overhead insertion port or dedicated orderwire or data communication channel ports. In addition, the STXC provides FERF and AIS alarm insertion, loss of signal insertion, framing pattern error insertion, and coding violation insertion (B1 and B2) for diagnostic purposes. A transmit and receive ring control port which allows alarm and maintenance signal control and status to be passed between mate STXCs is also provided. This feature is useful for ring-based add-drop multiplex applications and is taken advantage of in this design through the Ring Expansion Interface. When the Ring Expansion Interface is not used, the same STXC is used for both the receive and transmit sides of a ring connection. SPTX The SPTX device provides receive path termination for a SONET STS-1, STS-3 or STS-3c stream, or an SDH STM-1 stream carrying three AU3s or one AU4. SPTX interprets the received payload pointers (H1, H2) and extracts the synchronous payload envelope (virtual container). The extracted SPE (VC) is placed on a TeleCombus DROP bus. Frequency offsets (e.g., due to pleisiochronous network boundaries, or the loss of a primary reference timing source) and phase differences (due to normal network operation) between the received data stream and the DROP bus are accommodated by pointer adjustments in the DROP bus. In addition to its basic processing of the received SONET/SDH overhead, the SPTX provides convenient access to all path overhead bytes, which are extracted and serialized on lower rate interfaces, allowing additional external processing of overhead, if desired. The SPTX device provides transmit path origination for a SONET STS-1, STS-3 or STS-3c stream or an SDH STM-1 stream carrying three AU3s or one AU4. SPTX generates the transmit payload pointers (H1, H2) and inserts the synchronous payload envelope (virtual container) from a TeleCombus ADD bus into the transmit stream. Frequency offsets (e.g., due to pleisiochronous network boundaries, or the loss of a primary reference timing source) and phase differences (due to normal network operation) between the transmit data stream and the ADD buses are accommodated by pointer adjustments in the transmit stream. In addition to its basic processing of the transmit SONET/SDH overhead, the SPTX provides convenient 7 PMC-Sierra, Inc. STANDARD PRODUCT ISSUE 2 PM5543 SARD SONET/SDH 155Mbit/s ADM Reference Design access to all overhead bytes, which are inserted serially on lower rate interfaces, allowing additional external sourcing of overhead, if desired. The SPTX also supports the insertion of a large variety of errors into the transmit stream, such as bit interleaved parity errors and inverted NDF flags, which are useful for system diagnostics and tester applications. The SPTX device supports in-band error reporting where the path status byte (G1) inserted in the DROP bus reflects the number of BIP-8 errors (B3) detected and the path FERF status. The SPTX can be programmed to pass the path status byte on the ADD bus through unmodified. This feature allows the transmit path processor to be located remotely to the receive processor without having to incur the cost of routing an alarm port. The SPTX device supports tandem connection termination applications where the tandem connection maintenance byte (Z5) carries the incoming B3 BIP-8 error count, a tandem data link, and a path AIS code. The B3 byte is passed through to the DROP bus after being compensated for the differing Z5 byte, otherwise the B3 byte is unaffected. The incoming error count is accumulated and the receive data link is serialized for external processing. A new data link can be inserted from a low speed serial input. An incoming signal failure alarm (ISF code with IEC field set to 'b1111) is used to convey path AIS in place of all-ones in the pointer (H1, H2). The SPTX device maintains a large number of statistics for performance monitoring purposes. BIP-8 errors (B3) and tandem path incoming error counts (Z5 IEC) are accumulated. In addition, the SPTX is selectable to accumulate positive and negative pointer justifications that it receives or justifications that it generates on the DROP bus. It also accumulates positive and negative pointer justifications in the transmit stream. Excessive justifications may be indicative of clock synchronization failures. TUPP & TUPP-Plus Either TUPP or TUPP-Plus can be used in this design. When configured for SONET compatible operation, the TUPP or TUPP-Plus transfers all tributaries in the three STS-1 synchronous payload envelopes of an incoming STS-3 byte serial stream to the three STS-1 synchronous payload envelopes of an outgoing STS-3 byte serial stream. Similarly, when configured for SDH compatible operation, the TUPP transfers all tributaries in the single AU4 or three AU3 administrative units of an incoming STM-1 byte serial stream to a single AU4 or three AU3 administrative units of an outgoing STM-1 byte serial stream. The TUPP or TUPP-Plus compensates for pleisiochronous relationships between incoming and outgoing higher level (STS-1, AU4, AU3) synchronous payload envelope frame rates through processing of the lower level (VT6, VT3, VT2, VT1.5, TU3, TU2, TU12, TU11) tributary pointers. The TUPP or TUPP-Plus is configurable to process any legal mix of tributaries. Each VT group can be configured to carry any one of the four tributary types (VT1.5, VT2, VT3, or VT6) and each TUG2 can be configured to carry any one of three tributary 8 PMC-Sierra, Inc. STANDARD PRODUCT ISSUE 2 PM5543 SARD SONET/SDH 155Mbit/s ADM Reference Design types (TU11, TU12, or TU2). TUG2s can be multiplexed into a VC3 or a TUG3. Alternatively, each TUG3 can be configured to carry a TU3. The TUPP and TUPP-Plus provides useful maintenance functions. They include detection of loss of pointer and pointer re-acquisition for each tributary, and optional generation of interrupts. The TUPP also allows insertion of tributary path AIS or tributary idle (unequipped). The TUPP can also insert inverted new data flag fields that can be used to diagnose downstream pointer processing elements. The TUPPPlus implements a superset of the TUPP functionality. The TUPP-Plus contains tributary performance monitoring and tributary path overhead processing. These functions are not supported by the TUPP. The following functions are exclusive to the TUPP-Plus. * The TUPP-Plus is configurable to process 16-byte or 64-byte format tributary path trace messages (tributary trail trace identifiers). * Extracts and serializes the entire tributary path overhead for each tributary into lower speed serial streams. * Extracts tributary size (SS) bits for each tributary into internal registers. Extracts tributary path trace message (trail trace identifier) for each tributary into internal buffers. * Provides individual tributary path trace message buffer that holds the expected message and detects tributary path trace mismatch (trail trace identifier mismatch) alarms (TIM) and return to matched state for each tributary and optionally generates interrupts. * Detects tributary path trace unstable (trail trace identifier unstable) alarms (TIU) and return to stable state for each tributary and optionally generates interrupts. * Extracts tributary path signal label for each tributary into internal registers and detects change of tributary path signal label events (COPSL) for each tributary and optionally generates interrupts. * Provides individual tributary path signal label register that hold the expected label and detects tributary path signal label mismatch alarms (PSLM) and return to matched state for each tributary and optionally generates interrupts. * Detects tributary path signal label unstable alarms (PSLU) and return to stable state for each tributary and optionally generates interrupts. * Detects tributary unequipped defect (UNEQ) and tributary path defect indication (PDI-V). 9 PMC-Sierra, Inc. STANDARD PRODUCT ISSUE 2 PM5543 SARD SONET/SDH 155Mbit/s ADM Reference Design * Detects assertion and removal of tributary extended remote defect indications (RDI) for each tributary and optionally generates interrupts. * Calculates and compares the tributary path BIP-2 error detection code for each tributary and configurable to accumulate the BIP-2 errors, on block or bit basis, in internal registers. * Calculates and compares the TU3 path BIP-8 error detection code for each TU3 stream and accumulates the BIP-8 errors, on block or bit basis, in internal registers. * Accumulates TU3 tributary far end block errors (FEBE) on a bit or a block basis, in internal registers. * Allows insertion of all-zeros or all-ones tributary idle code with unequipped indication and valid pointer into any tributary under software control. Idle tributaries are identified by an output signal. Identifies outgoing tributaries that are in AIS state by an output signal. * Allows software to force the AIS insertion on a per tributary basis. * Inserts valid H4 byte and all-zeros fixed stuff bytes on the outgoing stream. Remaining path overhead bytes (J1, B3, C2, G1, F2, Z3, Z4, and Z5) can be configured to be set to all-zeros or to reflect the value of the corresponding POH bytes in the incoming stream. * Inserts valid pointers, and all-zeros transport overhead bytes on the outgoing stream with valid "TeleCombus" control signals when configured to operate in locked mode. * Supports in-band error reporting by updating the FEBE, RDI and auxiliary RDI bits in the V5 byte (G1 in TU3) with the status of the incoming stream. * Provides low maximum tributary processing delay of 33 s for VT1.5, 25 s for VT2, 17 s for VT3, and 9 s for VT6 streams. * provides independently configurable incoming and outgoing interfaces that operate in byte interface mode from a single 19.44 MHz clock or in nibble interface mode from a single 38.88 MHz clock. * Provides a standard 5 signal IEEE P1149.1 JTAG test port for boundary scan test purposes. TUDX The PM5371 TUDX SONET/SDH Tributary Unit Cross-Connect is a monolithic integrated circuit that allows non-blocking switching of tributaries within two SONET STS-3 or SDH STM-1 streams. Any tributary entering on either stream can be 10 PMC-Sierra, Inc. STANDARD PRODUCT ISSUE 2 PM5543 SARD SONET/SDH 155Mbit/s ADM Reference Design connected to any same size tributary within either outgoing stream. The TUDX can be programmed to cross-connect a mix of SONET VT1.5, VT2, VT3, VT6, or STS-1 channels or SDH TU11, TU12, TU2, or TU3 channels. Programmable idle code can also be inserted into any of these channels. The TUDX allows cross-connection of up to 168 VT1.5 or TU11 streams, up to 126 VT2 or TU12 streams, or up to 42 VT6 or TU2 streams or any legal mix as permitted by the SONET or SDH mappings. In this reference design one stream is provided from the upstream TUPP/TUPP-Plus device whilst the other is provided from an external mapper daughterboard through the Mapper Interface connector. Two TUDXs are used in this design, TUDX1 and TUDX2. The TUDX2 device provides the main data interconnect between the external mapper function and the SARD board. The other TUDX, TUDX1, provides the accompanying control signals that indicate the data condition transported through TUDX2. These control signals are used by the external mapper to decode the presence of tributary payload bytes and tributary V5 bytes. Timing Control The Timing Control circuit contains a 4096 free running counter, a 64K PROM and some other miscellaneous glue logic. The counter starts counting from zero and is initialized to zero after every occurrence of the C1 pulse or a reset. The counter continues to count until the initialization occurs again at the next C1 pulse. The 12 outputs of the counter are used to address an on board PROM that acts as a lookup table. The lookup values are programmed to account for delays through the TUPP/TUPP-Plus and TUDX's. Because these delays are constant, the time when the C1 byte (say) appears on the output of the TUDX2 is predictable. The value of this delay is equal to 280 (5 clock cycles of TUPP/TUPP-Plus and 275 clock cycles of TUDX in STS-3/STS-3c mode)or 100 (5 clock cycles of TUPP/TUPP-Plus and 95 clock cycles of TUDX in STS-1 mode) bytes after the C1 byte appears on the output of the SPTX. These values are equivalent to a count value of 280 or 100 (again, depending on the mode of operation). Therefore, by programming a logic one at this specified location in the PROM a C1 pulse is generated for the data on the output of the TUDX2. By programming a series of such locations the AC1J1V1 and APL signals can be constructed and the outputs of the PROM can be used to control the ADD bus control signals of the SPTX. The four page control bits (PAGE[0] to PAGE[3) from the board level programmable register(C080H) are used to address higher address's of the PROM and effectively segment the PROM into 16 pages, with each page being 4K deep. Page one is programmed to control the SARD board in STS-3 or STM-1(AU3) mode when the TUPP/TUPP-Plus output is locked with J1 at location 522. Page two is programmed to control the SARD board in STS-3c or STM-1(AU4) mode when the TUPP/TUPPPlus J1 output is locked at location 522. Page three is programmed to control the SARD board in STS-1 mode with J1 output from TUPP/TUPP-Plus locked at location 522. Page four to six are similar to page one to three except this time the TUPP-Plus output is locked with J1 at location 0. Page seven to Page sixteen are reserved for future use. 11 PMC-Sierra, Inc. STANDARD PRODUCT ISSUE 2 PM5543 SARD SONET/SDH 155Mbit/s ADM Reference Design Ring Expansion Interface This interface contains all the necessary signals to interconnect to a second SARD board. A single SARD board is equivalent to a single ring network element. To construct a duel ring network element (NE), a second board is required to act as the counter rotating protection path. When one SARD board is dedicated to one ring whilst the other board is dedicated to the counter rotating ring, there is no need to interconnect the two boards via the Ring expansion Interface. The Ring Expansion Interface is required when one of the rings of a dual ring network utilizes half the circuitry on one board (for traffic being received by the NE) and half the circuitry on an adjoining board (for traffic being transmitted by the NE). These two configurations require that the Stel/ar devices must be programmed in two different ways. In the first configuration, where the clockwise ring is constructed utilizing board 1 and the counter-clockwise ring is constructed utilizing board 2, the Stel/ar devices must be configured such that they can receive traffic from the East and transmit traffic to the west. This will be referred to as the "East/West Cut" configuration. In the second configuration, where the clockwise ring is constructed by utilizing half of each Stel/ar device on board 1 and the other half of each Stel/ar device on board 2, the Stel/ar devices must be configured such that its receive circuitry handles traffic from the east (on one ring) and its transmit circuitry handles traffic to the east (on the second ring). This will be referred to as the "North/South Cut" configuration. The Ring Expansion Interface is only useful when implementing the North/South Cut, otherwise there is no need to mate the two boards together. In this configuration, the receive clockwise ring utilizes half the circuitry whilst the transmit counter-clockwise ring utilizes the remaining half. Consequently, the circuitry on the adjoining SARD board must be linked to form a complete NE. The Ring Expansion Interface contains all the control signals and data signals required to interconnect the traffic from one SARD board to the adjoining SARD board. This includes ring control signals that allow communication between the two remote half's of each Stel/ar device from one board to the other. Ring Expansion interface is activated by appropriately configuring the on board jumpers. Mapper Interface The Mapper Interface allows interfacing to an external asynchronous transport system, such as an E1, T1, E3 or DS3 system. Therefore, this interface includes the complete SONET/SHD frame data and control signals as well as the lower level tributary control signals. The SONET/SDH drop traffic is interfaced via the DOUTL[8:0] outputs of the TUDX device and the AC1J1V1 and APL control signals from the TIMING CONTROL. The DOUTL[8:0] outputs of TUDX2 contain the SONET/SDH data and the DOUTL[1:0] outputs of TUDX1 contain the lower level tributary control signals OTSPE (or OTPL when TUPP_Plus is used), OTV5, OTPOH, AIS, IDLE, LC1J1V1, LPL and COUT. The 19.44MHz system clock is also passed through to the Mapper Interface. 12 PMC-Sierra, Inc. STANDARD PRODUCT ISSUE 2 PM5543 SARD SONET/SDH 155Mbit/s ADM Reference Design The SONET/SDH add traffic is interfaced via the DINB[8:0] inputs of TUDX2 and the OC1J1 output of the TIMING CONTROL block. The OC1J1 indicates the frame alignment and pointer value that must be applied to the byte serial data inputs on the DINB[8:0] stream. As an option to the OC1J1 control signal, the control signals LC1J1V1 and LPL are also directly connected to the mapper interface to allow generation of SONET/SDH frames aligned to the same alignment as the frames generated by the TUPP-Plus. The TUPP-Plus tributary overhead signals POH[3:1], POHFP[3:1], POHEN[3:1], POHCK and RAD are connected to the Mapper Interface to provide external tributary path overhead monitoring. Normally this is monitored in the TUPP-Plus and is not required to be done externally. LED Displays Two LED displays are provided to indicate the status of the STXC, SPTX and TUPP devices. When the LED's are lit they indicate the active condition on the STXC's OOF, LOF, LOS, LAIS and FERF outputs, the active condition on the SPTX's PFERF[3:1], PAIS[3:1] and LOP[3:1] outputs and the active condition on the TUPP's IDLE, AIS and LOM[3:1] outputs. Configuration Headers/Jumpers The SARD board contain four configuration headers/jumpers, J1, J2, J3 and J4. Jumpers J1 and J2 are provided to allow prototype boards to be interconnected between the STXC to SPTX interface. Jumper J1 is a 12 by 1 strip and jumper J2 is a 10 by 1 strip. Normally all pins of jumper J2 are connected to the adjacent pins of jumper J1. The remaining pins of J1 are left unconnected and are for observation only. The jumpers J3 and J4 provide SPTX an option to select ADD bus signal (ACK, APL, AC1J1V1 and AD[n]) from on board TUPP/TUPP-Plus, TUDX2 or from expansion board. When the Ring Expansion Interface is not used, jumpers J3 and J4 allows the SPTX to select traffic from the TUDX outputs or the TUPP outputs. When a second SARD board is connected to the Ring Expansion Interface, these jumpers must all be disconnected. See the SPTX ADD Bus Clock & Signal Selection Interface section for more information. 13 PMC-Sierra, Inc. STANDARD PRODUCT ISSUE 2 PM5543 SARD SONET/SDH 155Mbit/s ADM Reference Design INTERFACE SIGNAL DESCRIPTION Microprocessor Interface (Connector P1) This interface consists of a 96 pin male connector that interfaces to the PM1501 EVBD motherboard. Signals on this interface are CMOS/TTL compatible and are used to read and write to on board registers and the memory mapped Stel/ar on chip registers. This interface also provides power and ground connections to the SARD board. Microprocessor Interface Signal Description. Signal Name ALE E RWB RSTB A[15] A[14] A[13] A[12] A[11] A[10] A[9] A[8] AD[7] AD[6] AD[5] AD[4] AD[3] AD[2] AD[1] AD[0] PA3 PA4 Type I I I I I I I I I I I I I/O I/O I/O I/O I/O I/O I/O I/O I I P1 Pin C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 Function Address latch enable. When high, identifies that address is valid on AD[7:0]. External Data Access Indication. Active high. Active low write, active high read enable. Active low H/W reset. Address bus bit 7. Address bus bit 6. Address bus bit 5. Address bus bit 4. Address bus bit 3. Address bus bit 2. Address bus bit 1. Address bus bit 0. Multiplexed address/data bus bit 7. Multiplexed address/data bus bit 6. Multiplexed address/data bus bit 5. Multiplexed address/data bus bit 4. Multiplexed address/data bus bit 3. Multiplexed address/data bus bit 2. Multiplexed address/data bus bit 1. Multiplexed address/data bus bit 0. 68HC11 Processor Port A bit 3. 68HC11 Processor Port A bit 4. 14 PMC-Sierra, Inc. STANDARD PRODUCT ISSUE 2 PM5543 SARD SONET/SDH 155Mbit/s ADM Reference Design PA5 PA6 PD2 PD3 PD4 PD5 IRQ XIRQ DISB I I O I I I O O O C23 C24 C25 C26 C27 C28 C29 C30 C31 68HC11 Processor Port A bit 5. 68HC11 Processor Port A bit 6. MISO. Master In Slave Out of Port D acting as SPI. Pulled up on motherboard. MOSI. Master Out Slave In of Port D acting as SPI. Pulled up on motherboard. SCK. Serial clock of Port D acting as SPI. Pulled up on motherboard. SS. Slave Select of Port D acting as SPI active low. Pulled up on motherboard. Maskable interrupt. Non Maskable Interrupt. Not connected. EVMB memory disable. Pulling this signal low will disable MPU access to the EVMB's on-board RAM and EPROM. Not connected. SPARE. Ground. Power Supply. SP GND +5V O O O C32 A1A28 A29A32 Decoded Microprocessor Signal to Stel/ar chipset Interface The following table describes the interface between the TUDX, STXC, SPTX and TUPP/TUPP_Plus, the Mapper Interface with the decoded outputs of the on board microprocessor interface logic. These signals are the inputs and outputs of sheet 7 and 8. Signal ALE INTB WRB RDB MC STXC RSTB MC SPTX RSTB MC TUPP RSTB I/O O I O O O O O To/From All Stel/ar Devices and P3 All Stel/ar Devices and P3 All Stel/ar Devices and P3 All Stel/ar Devices and P3 STXC SPTX TUPP/TUPP-Plus Description Address latch enable. When high, identifies that address is valid on A[11:0]. Interrupt require signal. Active low. Active low write strobe signal. Active low Read enable select signal. Active low H/W reset. Active low H/W reset. Active low H/W reset. 15 PMC-Sierra, Inc. STANDARD PRODUCT ISSUE 2 PM5543 SARD SONET/SDH 155Mbit/s ADM Reference Design MC TUDX1 RSTB MC TUDX2 RSTB MC MAP RSTB 1 MC MAP RSTB 2 MC MAP RSTB 3 MC STXC CSB MC SPTX CSB MC TUPP CSB MC TUDX1 CSB MC TUDX2 CSB MC MAP CSB A[11] A[10] A[9] A[8] A[7] A[6] A[5] A[4] A[3] A[2] A[1] A[0] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] MC MAP CONTROL1 O O O O O O O O O O O O O O O O O O O O O O O I/O I/O I/O I/O I/O I/O I/O I/O O TUDX1 TUDX2 P3 P3 P3 STXC SPTX TUPP TUDX1 TUDX2 P3 TUPP-Plus P3 TUPP-Plus P3 TUPP-Plus & P3 SPTX TUPP-Plus P3 SPTX TUPP TUPPPlus P3 STXC SPTX TUPP TUPP-Plus P3 STXC SPTX TUPP TUPP-Plus P3 All Stel/ar Devices P3 All Stel/ar Devices P3 All Stel/ar Devices P3 All Stel/ar Devices P3 All Stel/ar Devices P3 All Stel/ar Devices P3 All Stel/ar Devices P3 All Stel/ar Devices P3 All Stel/ar Devices P3 All Stel/ar Devices P3 All Stel/ar Devices P3 All Stel/ar Devices P3 All Stel/ar Devices P3 P3 16 Active low H/W reset. Active low H/W reset. Active low H/W reset. Active low H/W reset. Active low H/W reset. Active low chip select. Active low chip select. Active low chip select. Active low chip select. Active low chip select. Active low chip select. Address bus bit 11. Address bus bit 10. Address bus bit 9. Address bus bit 8. Address bus bit 7. Address bus bit 6. Address bus bit 5. Address bus bit 4. Address bus bit 3. Address bus bit 2. Address bus bit 1. Address bus bit 0. Data bus bit 7. Data bus bit 6. Data bus bit 5. Data bus bit 4. Data bus bit 3. Data bus bit 2. Data bus bit 1. Data bus bit 0. Control bit reserved for future use PMC-Sierra, Inc. STANDARD PRODUCT ISSUE 2 PM5543 SARD SONET/SDH 155Mbit/s ADM Reference Design MC MAP CONTROL2 MC MAP CONTROL3 MC TDIS MC PAGE[0] MC PAGE[1] MC PAGE[2] O O O O O O P3 P3 STXC TIMING CONTROL TIMING CONTROL TIMING CONTROL TIMING CONTROL Control bit reserved for future use Control bit reserved for future use Active high transmit disable signal. PROM address bit 12. PROM address bit 13. PROM address bit 14. PROM address bit 15. MC PAGE[3]/CONCAT O Prototyping Jumper Interface The SARD board provides access to the receive interface between the STXC and the SPTX. This interface can be used to manipulate the SPTX's RECEIVE bus interface. In normal operation the jumpers J1 and J2 are connected as shown below. J1 J2 P_1 P_2 P_3 P_4 P_5 P_6 P_7 P_8 P_9 P_10 P_11 P_12 P_1 P_2 P_3 P_4 P_5 P_6 P_7 P_8 P_9 P_10 J1 P_1 P_2 P_3 P_4 P_5 P_6 P_7 P_8 J2 J2 Pin Description to J1 Pin Description MICRO_CONTROL PAGE[3]/CONCAT STXC GRICLK P_1 P_2 P_3 P_4 P_5 P_6 SPTX IFP SPTX PIN[0] SPTX PIN[1] SPTX PIN[2] SPTX PIN[3] SPTX PIN[4] 17 STXC ROFP STXC ROUT[0] STXC ROUT[1] STXC ROUT[2] STXC ROUT[3] STXC ROUT[4] PMC-Sierra, Inc. STANDARD PRODUCT ISSUE 2 PM5543 SARD SONET/SDH 155Mbit/s ADM Reference Design P_9 P_10 P_11 P_12 P_7 P_8 P_9 P_10 SPTX PIN[5] SPTX PIN[6] SPTX PIN[7] STXC ROUT[5] STXC ROUT[6] STXC ROUT[7] MICRO_CONTROL STXC RSTB SPTX ADD Bus Clock & Signal Select Interface When the Ring Expansion Interface is not used, jumpers J3 and J4 allows the SPTX to select traffic from the TUDX outputs or the TUPP outputs. When a second SARD board is connected to the Ring Expansion Interface, these jumpers must all be disconnected. The configuration shown below depicts the case where the TUDX is looped back to the SPTX's ADD bus. J3 P_2 P_4 P_6 P_8 P_10 P_1 P_3 P_5 P_7 P_9 Jumpers P_2 P_5 P_8 P_11 P_14 P_17 P_20 P_23 P_26 J4 P_1 P_4 P_7 P_10 P_13 P_16 P_19 P_22 P_25 P_3 P_6 P_9 P_12 P_15 P_18 P_21 P_24 P_27 The configuration shown below depicts the case where the TUPP/TUPP_Plus is looped back to the SPTX's ADD bus. J3 P_2 P_4 P_6 P_8 P_10 P_1 P_3 P_5 P_7 P_9 Jumpers P_2 P_5 P_8 P_11 P_14 P_17 P_20 P_23 P_26 J4 P_1 P_4 P_7 P_10 P_13 P_16 P_19 P_22 P_25 P_3 P_6 P_9 P_12 P_15 P_18 P_21 P_24 P_27 18 PMC-Sierra, Inc. STANDARD PRODUCT ISSUE 2 PM5543 SARD SONET/SDH 155Mbit/s ADM Reference Design J3 PIN 1-2 CLOSE PIN 3-4 CLOSE PIN 5-6 CLOSE PIN 7-8 CLOSE PIN 9-10 CLOSE ALL PINS OPEN J4 PIN 1-3 CLOSE PIN 4-6 CLOSE PIN 7-9 CLOSE PIN 10-12 CLOSE PIN 13-15 CLOSE PIN 16-18 CLOSE PIN 19-21 CLOSE PIN 22-24 CLOSE PIN 25-27 CLOSE PIN 2-3 CLOSE PIN 5-6 CLOSE PIN 8-9 CLOSE PIN 1112 CLOSE PIN 14-15 CLOSE PIN 17-18 CLOSE PIN 20-21 CLOSE PIN 23-24 CLOSE PIN 26-27 CLOSE ALL PINS OPEN Description Selects the on board 19.44 MHz crystal as the DROP bus clock Selects APL from TIMING CONTROL Selects AC1J1V1 from TIMING CONTROL Selects LPL from TUPP-Plus Selects LC1J1V1 from TUPP-Plus Selects the Ring Expansion Interface Description Selects the on board TUDX2 DOUTR(0) for loop back Selects the on board TUDX2 DOUTR(1) for loop back Selects the on board TUDX2 DOUTR(2) for loop back Selects the on board TUDX2 DOUTR(3) for loop back Selects the on board TUDX2 DOUTR(4) for loop back Selects the on board TUDX2 DOUTR(5) for loop back Selects the on board TUDX2 DOUTR(6) for loop back Selects the on board TUDX2 DOUTR(7) for loop back Selects the on board TUDX2 DOUTR(8) for loop back Selects the on board TUPP-Plus OD(0) for loop back Selects the on board TUPP-Plus OD(1) for loop back Selects the on board TUPP-Plus OD(2) for loop back Selects the on board TUPP-Plus OD(3) for loop back Selects the on board TUPP-Plus OD(4) for loop back Selects the on board TUPP-Plus OD(5) for loop back Selects the on board TUPP-Plus OD(6) for loop back Selects the on board TUPP-Plus OD(7) for loop back Selects the on board TUPP-Plus ODP for loop back Select the ADD signal from mated ADM board HP SDX1155 Optics to/from Cypress CY7B951 Interface SDX Signal RXDP RXDN SDX Type O O CY7B- CY7BType Signal I I RINP RINN Description Bit serial line side receive data positive Bit serial line side receive data negative 19 PMC-Sierra, Inc. STANDARD PRODUCT ISSUE 2 PM5543 SARD SONET/SDH 155Mbit/s ADM Reference Design SD TXDP TXDN O I I I O O CD TOUTP TOUTN Carrier detect signal, low fail Bit serial line side transmit data positive Bit serial line side transmit data negative Cypress CY7B951 to/from STXC Interface CY7B Signal RCLKP RCLKN RSERP RSERN MODE LOOP LFI* TCLKP TCLKN TSERP TSERN CY7B Type O O O O I I O O O I I STXC Type I I I I O O I I I O O STXC Signal RXCP RXCN RXDP RXDN SCPO(0) SCPO(1) RESR TXCP TXCN TXDP TXDN Description Receive clock positive Receive clock negative Bit serial Receive data positive Bit serial Receive data negative Mode control, low STS-1, high STS-3/STM-1 Loop control, low loopback, high open Line fault indication, low line fault Transmit clock positive Transmit clock negative Bit serial transmit data positive Bit serial transmit data negative STXC to/from SPTX Interface STXC Signal GRICLK ROFP ROUT[7] ROUT[6] ROUT[5] ROUT[4] ROUT[3] ROUT[2] ROUT[1] ROUT[0] GTICLK TIFP STXC Type O O O O O O O O O O O I SPTX SPTX Type Signal I I I I I I I I I I I O RCK IFP RD[7] RD[6] RD[5] RD[4] RD[3] RD[2] RD[1] RD[0] TCK FPOUT Description Byte serial receive clock Receive frame pulse Byte serial data bit 7 Byte serial data bit 6 Byte serial data bit 5 Byte serial data bit 4 Byte serial data bit 3 Byte serial data bit 2 Byte serial data bit 1 Byte serial data bit 0 Byte serial transmit clock Transmit frame pulse 20 PMC-Sierra, Inc. STANDARD PRODUCT ISSUE 2 PM5543 SARD SONET/SDH 155Mbit/s ADM Reference Design TIN[7] TIN[6] TIN[5] TIN[4] TIN[3] TIN[2] TIN[1] TIN[0] I I I I I I I I O O O O O O O O TD[7] TD[6] TD[5] TD[4] TD[3] TD[2] TD[1] TD[0] Byte serial data bit 7 Byte serial data bit 6 Byte serial data bit 5 Byte serial data bit 4 Byte serial data bit 3 Byte serial data bit 2 Byte serial data bit 1 Byte serial data bit 0 SPTX to/from TUPP/TUPP-Plus Interface SPTX Signal DD[7] DD[6] DD[5] DD[4] DD[3] DD[2] DD[1] DD[0] DC1J1V1 DDP DPL SPTX Type O O O O O O O O O O O TUPP Type I I I I I I I I I I I TUPP Signal DIN/ID[7] DIN/ID[6] DIN/ID[5] DIN/ID[4] DIN/ID[3] DIN/ID[2] DIN/ID[1] DIN/ID[0] IC1J1 IPAR/IDP ISPE/IPL Description Byte serial data bit 7 Byte serial data bit 6 Byte serial data bit 5 Byte serial data bit 4 Byte serial data bit 3 Byte serial data bit Byte serial data bit 1 Byte serial data bit 0 C1, J1 and V1 frame pulse Data parity Payload active signal SPTX to/from TIMING CONTROL(TC) block Interface SPTX Signal DC1J1V1 DPL SPTX Type O O TC TC Type Signal I I DC1J1V1 DPL Description C1, J1 and V1 frame pulse Payload active signal TUPP/TUPP-Plus to/from TUDX1 Interface TUPP Signal OTV5 TUPP Type O TUDX TUDX1 Type Signal I DINT[0] Description Outgoing tributary V5 byte 21 PMC-Sierra, Inc. STANDARD PRODUCT ISSUE 2 PM5543 SARD SONET/SDH 155Mbit/s ADM Reference Design OTSPE/ OTPL OTPOH AIS IDLE LC1J1V1 LPL COUT O I DINT[1] Outgoing tributary payload envelope O O O O O O I I I I I I DINT[2] DINT[3] DINT[4] DINT[5] DINT[6] DINT[7] Outgoing tributary path overhead signal Tributary alarm indication signal Tributary idle indication signal Locked mode composite frame pulse Locked mode payload active signal Controlled output signal TUPP/TUPP-Plus to/from TUDX2 Interface TUPP Signal OPAR/ ODP DOUT[7]/ OD[7] DOUT[6]/ OD[6] DOUT[5]/ OD[5] DOUT[4]/ OD[4] DOUT[3]/ OD[3] DOUT[2]/ OD[2] DOUT[1]/ OD[1] DOUT[0]/ OD[0] TUPP Type O O O O O O O O O TUDX TUDX2 Type Signal I I I I I I I I I DINT[8] DINT[7] DINT[6] DINT[5] DINT[4] DINT[3] DINT[2] DINT[1] DINT[0] Description Outgoing data parity signal Byte serial data bit 7 Byte serial data bit 6 Byte serial data bit 5 Byte serial data bit 4 Byte serial data bit 3 Byte serial data bit 2 Byte serial data bit 1 Byte serial data bit 0 TUPP from TIMING CONTROL(TC) Interface TUPP Signal OTMF OC1J1 TUPP Type I I TC TC Type Signal O O OTMF OC1 Description Outgoing tributary multiframe pulse C1 and J1 frame pulse 22 PMC-Sierra, Inc. STANDARD PRODUCT ISSUE 2 PM5543 SARD SONET/SDH 155Mbit/s ADM Reference Design TUDX1 from TIMING CONTROL(TC) Interface TUDX Signal OC1 TUDX Type I TC TC Type Signal O OC1 Description C1 framepulse TUDX2 from TIMING CONTROL(TC) Interface TUDX Signal OC1 TUDX Type I TC TC Type Signal O OC1 Description C1 frame pulse 19.44MHz System Clock Distribution Interface System Clock (Hz) 19.44MHZ 19.44MHZ 19.44MHZ 19.44MHZ 19.44MHZ 19.44MHZ To MAPPER INTERFACE TIMING CONTROL TUPP TUDX1 TUDX2 RING EXPANSION INTERFACE J3 SPTX Name at Destination CLK MAP CLK TC SCLK TUPP SCLK TUDX1 SCLK TUDX2 ACK EXP Description Clock to Mapper Interface 19.44Mbyte/s Clock to TIMING CONTROL Byte serial down stream data clock Byte serial tributary cross connection clock Byte serial tributary cross connection clock Clock to Ring Expansion Interface 19.44MHZ 19.44MHZ ACK DCK Byte serial up stream data loopback clock Byte serial Down stream data clock TIMING CONTROL(TC) Interface Signal DC1J1V1 DPL CLK OTMF OC1 I/O I I I O O To/From SPTX SPTX TC Description Required for counter synchronization Required for counter synchronization 19.44Mbyte/s clock TUPP/ TUPP- Tributary multiframe synchronization Plus TUPP/ TUPP- C1 frame pulse Plus , TUDX1, TUDX2 23 PMC-Sierra, Inc. STANDARD PRODUCT ISSUE 2 PM5543 SARD SONET/SDH 155Mbit/s ADM Reference Design OC1J1 AC1J1V1 O O Mapper Interface J3, Ring Expansion Interface, Mapper Interface Ring Expansion Interface, Mapper Interface Mapper Interface Unused Mapper Interface C1 and J1 synchronization for input data from Mapper Interface C1, J1 and V1 synchronization for input data from TUDX2 output on matted ADM board or Mapper Interface. APL O Payload active signal for data on TUDX2 outputs. OC1J1 SPA0 SPA1 SPA2 O O Mapper ADD traffic C1 and J1 synchronization Unused Spare control bits for mapping interface Ring Expansion Interface Signal ACK EXP TC APL TC AC1J1V1 EXP ACK EXP APL EXP AC1J1V1 TUDX2 DOUTR[8] TUDX2 DOUTR[7] TUDX2 DOUTR[6] TUDX2 DOUTR[5] TUDX2 DOUTR[4] TUDX2 DOUTR[3] I/O O O O I I I O O O O O O P2 pin A39 A35 A31 A61 A65 A69 A11 A13 A15 A17 A19 A21 Description 19.44MHz clock ADD bus payload signal ADD bus C1, J1, V1 synchronization signal 19.44MHz clock ADD bus payload signal ADD bus C1, J1, V1 synchronization signal ADD bus data parity signal ADD bus data bit 7 ADD bus data bit 6 ADD bus data bit 5 ADD bus data bit 4 ADD bus data bit 3 24 PMC-Sierra, Inc. STANDARD PRODUCT ISSUE 2 PM5543 SARD SONET/SDH 155Mbit/s ADM Reference Design TUDX2 DOUTR[2] TUDX2 DOUTR[1] TUDX2 DOUTR[0] EXP ADP EXP AD[7] EXP AD[6] EXP AD[5] EXP AD[4] EXP AD[3] EXP AD[2] EXP AD[1] EXP AD[0] STXC RRCPCLK STXC RRCPFP STXC RRCPDAT STXC TRCPCLK STXC TRCPFP STXC TRCPDAT SPTX RPOHCK1 SPTX RPOHFP1 SPTX RAD EXP TACK EXP TAFP EXP TAD O O O I I I I I I I I I O O O I I I O O O I I I A23 A25 A27 A89 A87 A85 A83 A81 A79 A77 A75 A73 A6 A10 A14 A96 A92 A88 A18 A22 A26 A84 A80 A76 ADD bus data bit 2 ADD bus data bit 1 ADD bus data bit 0 ADD bus data parity signal ADD bus data bit 7 ADD bus data bit 6 ADD bus data bit 5 ADD bus data bit 4 ADD bus data bit 3 ADD bus data bit 2 ADD bus data bit 1 ADD bus data bit 0 Receive Ring control port clock Receive Ring control port frame pulse Receive Ring control port data Transmit Ring control port clock Transmit Ring control port frame pulse Transmit Ring control port data Receive path overhead clock1 Receive path overhead frame pulse 1 Receive alarm port data signal Transmit alarm port clock Transmit alarm port frame signal Transmit alarm port data signal 25 PMC-Sierra, Inc. STANDARD PRODUCT ISSUE 2 PM5543 SARD SONET/SDH 155Mbit/s ADM Reference Design GND A1 A2 A30 A49 A50 A99 A100 Ground Mapper Interface Signal CLK MAP TUDX1 MAP DOUTL[0] TUDX1 MAP DOUTL[1] TUDX1 MAP DOUTL[2] TUDX1 MAP DOUTL[3] TUDX1 MAP DOUTL[4] TUDX1 MAP DOUTL[5] TUDX1 MAP DOUTL[6] TUDX1 MAP DOUTL[7] TUDX1 MAP COUTL TUDX2 MAP COUTL TUDX2 MAP DOUTL[8] TUDX2 MAP DOUTL[7] TUDX2 MAP DOUTL[6] TUDX2 MAP DOUTL[5] TUDX2 MAP DOUTL[4] I/O O O O O O O O O O O O O O O O O P3 pin A40 A36 A34 A32 A30 A28 A26 A24 A22 A18 A27 A31 A33 A35 A37 A39 Description 19.44MHz clock DROP tributary V5 byte indication DROP tributary synchronous payload envelope signal marks Outgoing tributary path overhead signal Tributary alarm indication signal Tributary idle indication signal Locked mode composite frame pulse Locked mode payload active signal Controlled output signal Left control output signal Left control output signal DROP bus data parity signal DROP bus data bit 7 DROP bus data bit 6 DROP bus data bit 5 DROP bus data bit 4 26 PMC-Sierra, Inc. STANDARD PRODUCT ISSUE 2 PM5543 SARD SONET/SDH 155Mbit/s ADM Reference Design TUDX2 MAP DOUTL[3] TUDX2 MAP DOUTL[2] TUDX2 MAP DOUTL[1] TUDX2 MAP DOUTL[0] MAP TUDX2 DINB[8] MAP TUDX2 DINB[7] MAP TUDX2 DINB[6] MAP TUDX2 DINB[5] MAP TUDX2 DINB[4] MAP TUDX2 DINB[3] MAP TUDX2 DINB[2] MAP TUDX2 DINB[1] MAP TUDX2 DINB[0] TC OC1J1 TC APL TC AC1J1V1 TUPP POHEN [3:1] TUPP POHFP [3:1] TUPP POH [3:1] TUPP RAD TUPP POHCK O O O O I I I I I I I I I O O O O A41 A43 A45 A47 A38 A67 A65 A63 A61 A59 A57 A55 A53 A46 A48 A50 A3 A5 A7 A9 A11 A13 A15 A17 A19 A21 A23 DROP bus data bit 3 DROP bus data bit 2 DROP bus data bit 1 DROP bus data bit 0 ADD bus data parity signal ADD bus data bit 7 ADD bus data bit 6 ADD bus data bit 5 ADD bus data bit 4 ADD bus data bit 3 ADD bus data bit 2 ADD bus data bit 1 ADD bus data bit 0 ADD bus C1, J1 frame signal ADD data payload signal ADD data C1, J1, V1 frame synchronization Tributary path overhead enable signals O Tributary path overhead frame pulse signals O Tributary path overhead signals O O Receive alarm port Tributary path overhead enable signals 27 PMC-Sierra, Inc. STANDARD PRODUCT ISSUE 2 PM5543 SARD SONET/SDH 155Mbit/s ADM Reference Design MC MAP RSTB[3:1] MC MAP CONTROL [3:1] MC MAP CSB ALE WRB RDB D[7:0] O A66 A64 A62 A60 A58 A56 A70 A90 A87 A89 A88 A86 A84 A82 A80 A78 A76 A74 A92 A94 A93 A91 A85 A83 A81 A79 A77 A75 A73 A71 A69 A42 A52 A6 A8 A95 A96 A1 A2 A97 A98 A99 A100 H/W reset bits O Reserved for mapper control signals O O O O I/O Chip select signal Address latch enable write strobe signal read enable signal Data bus A[11:0] O Address bus INTB SPARE1 SPARE2 VCC I O O O Interrupt signal from mapper side Reserved for future use Reserved for future use +5 v power GND Ground 28 PMC-Sierra, Inc. STANDARD PRODUCT ISSUE 2 PM5543 SARD SONET/SDH 155Mbit/s ADM Reference Design STXC and TUPP-Plus Status LED Display LED D2 LED1 LED2 LED3 LED4 LED5 LED6 LED7 LED8 LED9 LED10 From STXC STXC STXC STXC STXC TUPPPlus TUPPPlus TUPPPlus TUPPPlus TUPP Plus Signal OOF LOS LAIS FERF LOF AIS IDLE LOM[1] LOM[2] LOM[3] Description Out of frame indicator Loss of signal indicator Line alarm indication signal indicator Far end receive failure indicator Loss of frame indicator Tributary alarm indication signal indicator Tributary idle indicator Loss of multiframe indicator Loss of multiframe indicator Loss of multiframe indicator SPTX status LED Display LED D3 LED1 LED2 LED3 LED4 LED5 LED6 LED7 LED8 LED9 LED10 From SPTX SPTX SPTX SPTX SPTX SPTX SPTX SPTX SPTX NA Signal LOP[1] LOP[2] LOP[3] PAIS[1] PAIS[2] PAIS[3] PFERF[1] PFERF[2] PFERF[3] NA Description Loss of pointer indicator Loss of pointer indicator Loss of pointer indicator Path alarm indication signal indicator Path alarm indication signal indicator Path alarm indication signal indicator Path far end receive failure indicator Path far end receive failure indicator Path far end receive failure indicator Unused 29 PMC-Sierra, Inc. STANDARD PRODUCT ISSUE 2 PM5543 SARD SONET/SDH 155Mbit/s ADM Reference Design SOFTWARE INTERFACE DESCRIPTION The microprocessor interface provides the 68HC11 on the PM1501 EVBD access to the SARD board memory space via the 96 pin DIN edge connector. The SARD memory space contains three board level configuration registers, the register space of the STXC device, the register space of the SPTX device, the register space of the TUPP/TUPP-Plus device and the register space of the TUDX devices. The complete register map is shown below. Address Range C000H C080H C100H C200H-C2FFH C300H-C4FFH 9000H-9FFFH A000H-AFFFH C600H-C6FFH C700H-C7FFH Register Reserved STXC TDIS control , PAGE control and Mapper control Configuration Device Reset STXC device registers SPTX device registers Mapper Interface TUPP/TUPP-Plus device registers TUDX2 device registers TUDX1 device registers 30 PMC-Sierra, Inc. STANDARD PRODUCT ISSUE 2 PM5543 SARD SONET/SDH 155Mbit/s ADM Reference Design SARD General Registers The SARD reference design contains the following general configuration registers to configure the STXC, SPTX, TUPP/TUPP-Plus and TUDX devices. Register C080H: STXC and CONTROL Configuration Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TDIS: The Transmit Disable (TDIS) controls overwriting of overhead bytes in the transmit stream of the STXC. When TDIS is set high, most of the overhead passes through unchanged (except K1, B1, B2). When TDIS is low, the overhead bytes will be overwritten as determined by the TTOH and TTOHEN inputs. PAGE[0] to PAGE[3]: Bits PAGE[0] through PAGE[3] together is an address which identifies one of the sixteen possible look up tables (4Kbytes deep) within a 64Kbytes on board PROM. PAGE[0] forms the least significant bit of the four most significant bits of the PROM address. PAGE[3] forms the most significant bit of the four most significant bits of the PROM address. One of sixteen tables in the PROM can be selected by these four address bits. Each table contains the timing control signal required by different operation mode. These operating modes are show in the Mode Select Table below. Mode Select Table Page[3] 0 0 0 Page[2] 0 0 0 Page[1] 0 0 1 31 Type R/W R/W R/W R/W R/W R/W R/W R/W Function MCNTRL3 MCNTRL2 MCNTRL1 TDIS PAGE[3] PAGE[2] PAGE[1] PAGE[0] Default 0 0 0 0 0 0 0 0 Page[0] 0 1 0 Operation mode STS-3/STM-1(AU3) J1 at location 522 STS-3c/STM-1(AU4) J1 at location 522 STS-1 J1 at location 522 PMC-Sierra, Inc. STANDARD PRODUCT ISSUE 2 PM5543 SARD SONET/SDH 155Mbit/s ADM Reference Design 0 0 0 Others MCNTRL1 to MCNTRL3: 0 1 1 1 0 0 1 0 1 STS-3/STM-1(AU3) J1 at location 0 STS-3c/STM-1(AU4) J1 at location 0 STS-1 J1 at location 0 Reserved for future use These bits are reserved for Mapping Interface use. Register C100H: Device Reset Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type Function R/W TUDX1_RSTB R/W TUDX2_RSTB R/W TUPP_RSTB R/W SPTX_RSTB R/W STXC_RSTB R/W MRSTB3 R/W MRSTB2 R/W MRSTB1 Default 0 0 0 0 0 0 0 0 MRSTBn: These bits are reserved for use by the Mappier Interface. STXC_RSTB: This active low reset bit controls the RSTB input of the STXC device. When set to logic one, the STXC device is allowed to operate normally. When set to logic zero, the STXC device is held in reset. The STXC devices remain in reset until a logic one is written to this bit. SPTX_RSTB: This active low reset bit controls the RSTB input of the SPTX device. When set to logic one, the SPTX device is allowed to operate normally. When set to logic zero, the SPTX device is held in reset. The SPTX devices remain in reset until a logic one is written to this bit. TUPP_RSTB: This active low device reset bit controls the RSTB input of the TUPP/TUPP_Plus device. When set to logic one, the TUPP/TUPP_Plus device is allowed to operate normally. When set to logic zero, the TUPP/TUPP_Plus 32 PMC-Sierra, Inc. STANDARD PRODUCT ISSUE 2 PM5543 SARD SONET/SDH 155Mbit/s ADM Reference Design device is held in reset. The TUPP/TUPP_Plus device remains in reset until a logic one is written to this bit. TUDX1_RSTB: This active low reset bit controls the RSTB input of the TUDX1 device. When set to logic one, the TUDX1 device is allowed to operate normally. When set to logic zero, the TUDX1 device is held in reset. The TUDX1 devices remain in reset until a logic one is written to this bit. TUDX2_RSTB: This active low reset bit controls the RSTB input of the TUDX2 device. When set to logic one, the TUDX2 device is allowed to operate normally. When set to logic zero, the TUDX2 device is held in reset. The TUDX2 devices remain in reset until a logic one is written to this bit. STXC Registers The STXC address space extends from C200H to C2FFH. For further details, please refer to the SONET/SDH Transport Overhead Terminating Transceiver Datasheet. Address Register C200 Master Configuration C201 Master Control/Enable C202 Master Interrupt Status C203 Master Reset and Identity C204 TLOP Control C205 TLOP Diagnostic C206 Transmit K1 C207 Transmit K2 C208 RLOP Control/Status C209 RLOP Interrupt C20A B2 Error Count #1 C20B B2 Error Count #2 C20C B2 Error Count #3 C20D FEBE Error Count #1 C20E FEBE Error Count #2 C20F FEBE Error Count #3 C210 RSOP Control C211 RSOP Interrupt Status C212 B1 Error Count #1 C213 B1 Error Count #2 C214 Output Port C215 Input Port Interrupt Enable C216 Unused C217 Ring Control Port C218 TSOP Control 33 PMC-Sierra, Inc. STANDARD PRODUCT ISSUE 2 PM5543 SARD SONET/SDH 155Mbit/s ADM Reference Design C219 C21A C21B C21C C21D C21E C21F C220 C221 C222 C223 C224 C225-C2FF SCPO[0] SCPO[1] SCPO[2] TSOP Diagnostic Transmit Z1 Receive Z1 Reserved Receive K1 Receive K2 Input Port Status/Value Section Trace Control Section Trace Status Section Trace Indirect Address Section Trace Indirect Data Section Trace AIS Insertion Reserved for Test CY7B951 mode control signal CY7B951 loopback control signal Indicator disable signal SPTX Registers The SPTX address space extends from C300H to C4FFH. For further details, please refer to the SONET/SDH Path Terminating Transceiver Payload Processor Datasheet. Address C300 C301 C302 C303 C304 C305 C306 C307 C308 C309-0F C310 C311 C312 C313 C314 C315 C316 C317 C318 C319 Register Master Configuration Master Alarm Configuration Master Parity Configuration Master Reset and Identity Master Interrupt Status #1 Master Interrupt Status #2 Master Transmit Control Master Loopback, ADD Bus Control Input Signal Activity Monitor, Accumulation Trigger Reserved RPOP #1, Status and Control RPOP #1, Alarm Interrupt Status RPOP #1, Pointer Interrupt Status RPOP #1, Alarm Interrupt Enable RPOP #1, Pointer Interrupt Enable RPOP #1, Pointer LSB RPOP #1, Pointer MSB RPOP #1, Path Signal Label RPOP #1, Path BIP-8 Count LSB RPOP #1, Path BIP-8 Count MSB 34 PMC-Sierra, Inc. STANDARD PRODUCT ISSUE 2 PM5543 SARD SONET/SDH 155Mbit/s ADM Reference Design C31A C31B C31C C31D C31E C31F C320 C321 C322-23 C324 C325 C326 C327 C328 C329 C32A C32B- 2F C330 C331 C332 C333 C334 C335 C336 C337 C338 C339 C33A C33B C33C C33D C33E C33F C340 C341 C342 C343-47 C348 C349 RPOP #1, Path FEBE Count LSB RPOP #1, Path FEBE Count MSB RPOP #1, Tributary Multiframe Status and Control RPOP #1, Tandem Connection and Ring Control RPOP #1, Tandem Connection IEC Count LSB RPOP #1, Tandem Connection IEC Count MSB Reserved PMON #1, Interrupt Enable and Status Reserved PMON #1, Receive Positive Pointer Justification Count PMON #1, Receive Negative Pointer Justification Count PMON #1, Transmit Positive Pointer Justification Count PMON #1, Transmit Negative Pointer Justification Count RTAL #1, Control RTAL #1, Interrupt Status and Control RTAL #1, Alarm and Diagnostic Control Reserved TPOP #1, Control TPOP #1, Payload Pointer Control TPOP #1, Source Control TPOP #1, Current Pointer LSB TPOP #1, Current Pointer MSB TPOP #1, Payload Pointer LSB TPOP #1, Payload Pointer MSB TPOP #1, Path Trace TPOP #1, Path Signal Label TPOP #1, Path Status TPOP #1, Path User Channel TPOP #1, Path Growth 1 TPOP #1, Path Growth 2 TPOP #1, Path Growth 3 TPOP #1, Concatenation LSB TPOP #1, Concatenation MSB TTAL #1, Control TTAL #1, Interrupt Status and Control TTAL #1, Alarm and Diagnostic Control Reserved SPTB #1, Control SPTB #1, Status 35 PMC-Sierra, Inc. STANDARD PRODUCT ISSUE 2 PM5543 SARD SONET/SDH 155Mbit/s ADM Reference Design C34A C34B C34C C34D C34E-4F C350-5F C360-67 C368-6B C36C-6F C370-7F C380-83 C384-87 C388-8F C390-9F C3A0-A7 C3A8-AB C3AC-AF C3B0-BF C3C0-C3 C3C4-C7 C3C8-CF C3D0-FF C400 C401-FF SPTB #1, Indirect Address SPTB #1, Indirect Data SPTB #1, Expected Path Signal Label SPTB #1, Path Signal Label Status Reserved RPOP #2 Registers PMON #2 Registers RTAL #2 Registers Reserved TPOP #2 Registers TTAL #2 Registers Reserved SPTB #2 Registers RPOP #3 Registers PMON #3 Registers RTAL #3 Registers Reserved TPOP #3 Registers TTAL #3 Registers Reserved SPTB #3 Registers Reserved Master Test Reserved for Test TUPP & TUPP-Plus Registers The TUPP address spaces extends from A000H to A0FFH and the TUPP-Plus address spaces extends from A000H to AFFFH. For further details, please refer to the SONET/SDH Tributary Unit Payload Processor Datasheet (PM5361 or PM5362). Address A000 A001 A002 A003 A004 A005 A006 A007 A008 A009 Register Master Incoming Configuration Master Outgoing Configuration Input Signal Activity Monitor Master Reset and Identity Tributary Payload Processor #1 Configuration Tributary Payload Processor #2 Configuration Tributary Payload Processor #3 Configuration Tributary Payload Processor and H4 OOF Interrupt Enable Tributary Payload Processor Interrupt Status and H4 OOF Status Parity Error and H4 OOF Interrupt 36 PMC-Sierra, Inc. STANDARD PRODUCT ISSUE 2 PM5543 SARD SONET/SDH 155Mbit/s ADM Reference Design A00A-1F A020 A021 A022 A023 A024 A025 A026 A027 A028 A029 A02A A02B A02C A02D A02E A02F A030 A031 A032 A033 A034 A035 A036 A037 A038 A039 A03A A03B A03C A03D A03E A03F A040-5F A060-7F A080 A081-FF Reserved TPP #1, TU3, or TU #1 in TUG2 #1, Configuration and Status TPP #1, TU #1 in TUG2 #2, Configuration and Status TPP #1, TU #1 in TUG2 #3, Configuration and Status TPP #1, TU #1 in TUG2 #4, Configuration and Status TPP #1, TU #1 in TUG2 #5, Configuration and Status TPP #1, TU #1 in TUG2 #6, Configuration and Status TPP #1, TU #1 in TUG2 #7, Configuration and Status TPP #1, TU3 or TU #1 in TUG2 #1 to TUG2 #7, LOP Interrupt TPP #1, TU #2 in TUG2 #1, Configuration and Status TPP #1, TU #2 in TUG2 #2, Configuration and Status TPP #1, TU #2 in TUG2 #3, Configuration and Status TPP #1, TU #2 in TUG2 #4, Configuration and Status TPP #1, TU #2 in TUG2 #5, Configuration and Status TPP #1, TU #2 in TUG2 #6, Configuration and Status TPP #1, TU #2 in TUG2 #7, Configuration and Status TPP #1, TU #2 in TUG2 #1 to TUG2 #7, LOP Interrupt TPP #1, TU #3 in TUG2 #1, Configuration and Status TPP #1, TU #3 in TUG2 #2, Configuration and Status TPP #1, TU #3 in TUG2 #3, Configuration and Status TPP #1, TU #3 in TUG2 #4, Configuration and Status TPP #1, TU #3 in TUG2 #5, Configuration and Status TPP #1, TU #3 in TUG2 #6, Configuration and Status TPP #1, TU #3 in TUG2 #7, Configuration and Status TPP #1, TU #3 in TUG2 #1 to TUG2 #7, LOP Interrupt TPP #1, TU #4 in TUG2 #1, Configuration and Status TPP #1, TU #4 in TUG2 #2, Configuration and Status TPP #1, TU #4 in TUG2 #3, Configuration and Status TPP #1, TU #4 in TUG2 #4, Configuration and Status TPP #1, TU #4 in TUG2 #5, Configuration and Status TPP #1, TU #4 in TUG2 #6, Configuration and Status TPP #1, TU #4 in TUG2 #7, Configuration and Status TPP #1, TU #4 in TUG2 #1 to TUG2 #7, LOP Interrupt Tributary Payload Processor #2 Registers Tributary Payload Processor #3 Registers Master Test Reserved for Test 37 PMC-Sierra, Inc. STANDARD PRODUCT ISSUE 2 PM5543 SARD SONET/SDH 155Mbit/s ADM Reference Design TUDX1 Registers The TUDX1 address spaces extends from C700H to C7FFH. For further details, please refer to the SONET/SDH Tributary Unit Cross-connect Datasheet. Address C700 C701 C702 C703 C704 C705 C706 C707 C708 C709 C70A C70B C70C C70D C70E C70F C710 C711-1F Register Master Configuration Connection Memory Control Clock Monitor Master Reset/Revision ID Parity Configuration Parity Error Interrupt Enable Parity Error Interrupt Status Systolic Delay Control Left Switch Element Connection Address High Left Switch Element Connection Address Low Left Switch Element Connection Data High Left Switch Element Connection Data Low Right Switch Element Connection Address High Right Switch Element Connection Address Low Right Switch Element Connection Data High Right Switch Element Connection Data Low Master Test Reserved for Test TUDX2 Registers The TUDX2 address spaces extends from C600H to C6FFH. For further details, please refer to the SONET/SDH Tributary Unit Cross-connect Datasheet. Address C600 C601 C602 C603 C604 C605 C606 C607 C608 C609 C60A C60B Register Master Configuration Connection Memory Control Clock Monitor Master Reset/Revision ID Parity Configuration Parity Error Interrupt Enable Parity Error Interrupt Status Systolic Delay Control Left Switch Element Connection Address High Left Switch Element Connection Address Low Left Switch Element Connection Data High Left Switch Element Connection Data Low 38 PMC-Sierra, Inc. STANDARD PRODUCT ISSUE 2 PM5543 SARD SONET/SDH 155Mbit/s ADM Reference Design C60C C60D C60E C60F C610 C611-1F Right Switch Element Connection Address High Right Switch Element Connection Address Low Right Switch Element Connection Data High Right Switch Element Connection Data Low Master Test Reserved for Test 39 PMC-Sierra, Inc. STANDARD PRODUCT ISSUE 2 PM5543 SARD SONET/SDH 155Mbit/s ADM Reference Design ON BOARD PROM The PROM device can be programmed to generate various control signals. The output on U47 pin 3 (AC1J1V1) and the buffer(U38) pin Q4(APL) controls the SPTX's ADD bus and the outgoing traffic on the Mapper and Ring Expansion Interfaces. The output on the buffer pin Q0 controls the outgoing tributary multiframe on the TUPP/TUPP_Plus by clocking an external 2 bit counter. The output on buffer pin Q2(OC1) controls the frame sychronization on the TUDX1, TUDX2 devices and also controls the outgoing frame alignment of the TUPP/TUPP_Plus when it is operating in locked mode. The output on buffer pin Q5(OC1J1) controls the ADD traffic frame synchronization at the Mapper Interface. The buffer output pins Q6 and Q7 are routed to the Ring Expansion Interface and the Mapper Interface respectively and can be used as desired. The following table shows the contents of the PROM(U15) required for operation at STS-3, STS-3c and STS-1 when the J1 output from the TUPP/TUPP-Plus is locked at a pointer of 522 or 0. PAGE 0 STS-3/STM-1(AU3) with J1 Locked at 522 bit7 bit6 bit5 OC1J 1 ADDRESS HEX 0 1 2 3 4 5 6 7 8 9 A B C-110 111 112 113 114 115 116 117 118 119 bit4 APL bit3 AV1 bit2 OC1 bit1 SPA0 bit0 OTM F SPA2 SPA1 PROM DATA HEX Description Signal Name 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 40 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 D1 1 1 1 1 1 1 1 1 1 D1 D1 D1 C1 C5 C1 C1 C1 C1 C1 C1 C1 C1 C1 C1 C1 C1 C1 E1 C1 C1 APL (9th row) APL & OC1 APL APL APL APL APL APL APL APL (1st row) APL APL APL APL APL APL & C1 APL APL PMC-Sierra, Inc. STANDARD PRODUCT ISSUE 2 PM5543 SARD SONET/SDH 155Mbit/s ADM Reference Design 11A 11B 11C 11D 11E 11F 120-21E 21F 220 221 222 223 224 225 226 227 228-32C 32D 32E 32F 330 331 332 333 334 335 336-43A 43B 43C 43D 43E 43F 440 441 442 443 444-548 549 54A 54B 54C 54D 54E 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 41 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 F1 F1 F1 D9 D9 D9 D1 C1 C1 C1 C1 C1 C1 C1 C1 C1 D1 C1 C1 C1 C1 C1 C1 C1 C1 C1 D1 C1 C1 C1 C1 C1 C1 C1 C1 C1 D1 C1 C1 C1 C1 C1 C1 J1 J1 J1 V1 V1 V1 APL(2nd row) APL APL APL APL APL APL APL APL APL (3rd row) APL APL APL APL APL APL APL APL APL (4th row) APL APL APL APL APL APL APL APL APL (5th row) APL APL APL APL APL PMC-Sierra, Inc. STANDARD PRODUCT ISSUE 2 PM5543 SARD SONET/SDH 155Mbit/s ADM Reference Design 54F 550 551 552-656 657 658 659 65A 65B 65C 65D 65E 65F 660-764 765 766 767 768 769 76A 76B 76C 76D 76E-872 873 874 875 876 877 878 879 87A 87B 87C-97E 97F-0FFF PAGE 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 C1 C1 C1 D1 C1 C1 C1 C1 C1 C1 C1 C1 C1 D1 C1 C1 C1 C1 C1 C1 C1 C1 C1 D1 C1 C1 C1 C1 C1 C1 C1 C1 C1 D0 FF APL APL APL APL (6th row) APL APL APL APL APL APL APL APL APL (7th row) APL APL APL APL APL APL APL APL APL (8th row) APL APL APL APL APL APL APL APL OTMF trigger Unused STS-3c/STM-1(AU4) with J1 Located at 522 bit7 bit6 bit5 OC1J 1 ADDRESS HEX 1000 bit4 APL bit3 AV1 bit2 OC1 bit1 SPA0 bit0 OTM F SPA2 SPA1 PROM DATA HEX Description 1 1 0 1 0 42 0 0 1 D1 PMC-Sierra, Inc. STANDARD PRODUCT ISSUE 2 PM5543 SARD SONET/SDH 155Mbit/s ADM Reference Design 1001 1002 1003 1004 1005 1006 1007 1008 1009 100A 100B 100C-1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 111A 111B 111C 111D 111E 111F 1120-121E 121F 1220 1221 1222 1223 1224 1225 1226 1227 1228-132C 132D 132E 132F 1330 1331 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 43 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D1 D1 C1 C5 C1 C1 C1 C1 C1 C1 C1 D1 C1 C1 C1 C1 C1 C1 E1 C1 C1 F1 D1 D1 D9 D1 D1 D1 C1 C1 C1 C1 C1 C1 C1 C1 C1 D1 C1 C1 C1 C1 C1 APL (9th row) APL & OC1 APL APL APL APL APL APL APL APL (1st row) APL APL APL APL APL APL & C1 APL APL J1 V1 APL (2nd row) APL APL APL APL APL APL APL APL APL (3rd row) APL APL APL APL PMC-Sierra, Inc. STANDARD PRODUCT ISSUE 2 PM5543 SARD SONET/SDH 155Mbit/s ADM Reference Design 1332 1333 1334 1335 1336-143A 143B 143C 143D 143E 143F 1440 1441 1442 1443 1444-1548 1549 154A 154B 154C 154D 154E 154F 1550 1551 1552-1656 1657 1658 1659 165A 165B 165C 165D 165E 165F 1660-1764 1765 1766 1767 1768 1769 176A 176B 176C 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 44 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 C1 C1 C1 C1 D1 C1 C1 C1 C1 C1 C1 C1 C1 C1 D1 C1 C1 C1 C1 C1 C1 C1 C1 C1 D1 C1 C1 C1 C1 C1 C1 C1 C1 C1 1 C1 C1 C1 C1 C1 C1 C1 C1 APL APL APL APL APL (4th row) APL APL APL APL APL APL APL APL APL (5th row) APL APL APL APL APL APL APL APL APL (6th row) APL APL APL APL APL APL APL APL D1 APL (7th row) APL APL APL APL APL APL APL PMC-Sierra, Inc. STANDARD PRODUCT ISSUE 2 PM5543 SARD SONET/SDH 155Mbit/s ADM Reference Design 176D 176E-1872 1873 1874 1875 1876 1877 1878 1879 187A 187B 187C-197E 197F-1FFF PAGE 2 ADDRESS HEX 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 200A-2060 2061 2062 2063 2064 2065 2066-20BA 20BB 20BC 20BD 20BE-2114 2115 2116 2117 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 1 1 1 1 1 1 1 0 1 C1 1 C1 C1 C1 C1 C1 C1 C1 C1 C1 D0 FF APL D1 APL (8th row) APL APL APL APL APL APL APL APL OTMF trigger Unused STS-1 with J1 Located at 522 bit7 bit6 bit5 OC1J 1 bit4 APL bit3 AV1 bit2 OC1 bit1 SPA0 bit0 OTM F SPA2 SPA1 PROM DATA HEX Description 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 1 0 0 0 1 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 45 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D1 D1 D1 D1 D5 D1 D1 C1 C1 C1 D1 C1 C1 E1 F1 D9 D1 C1 C1 C1 D1 C1 C1 C1 OC1 APL (9th row) APL APL APL (1st row) APL APL & C1 J1 V1 APL (2nd row) APL APL APL (3rd row) APL APL PMC-Sierra, Inc. STANDARD PRODUCT ISSUE 2 PM5543 SARD SONET/SDH 155Mbit/s ADM Reference Design 2118-216E 216F 2170 2171 2172 -21C8 21C9 21CA 21CB 21CC-2222 2223 2224 2225 2226-227C 227D 227E 227F 2280-22D6 22D7 22D8 22D9 22DA-232A 232B-2FFF PAGE 3 ADDRESS HEX 3000 3001 3002 3003 3004 3005 3006 3007 3008 3009 300A 300B 300C-3110 3111 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 0 1 D1 C1 C1 C1 D1 C1 C1 C1 1 C1 C1 C1 D1 C1 C1 C1 D1 C1 C1 C1 D0 FF APL (4th row) APL APL APL (5th row) APL APL D1 APL (6th row) APL APL APL (7th row) APL APL APL (8th row) APL APL OTMF trigger Unused STS-3/STM-1(AU3) with J1 Located at 0 bit7 bit6 bit5 OC1J 1 bit4 APL bit3 AV1 bit2 OC1 bit1 SPA0 bit0 OTM F SPA2 SPA1 PROM DATA HEX Description 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 46 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D1 D1 D1 C1 C5 C1 C1 C1 C1 C1 C1 C1 D1 C1 APL (9th row) APL & OC1 APL APL APL APL APL APL APL APL (1st row) PMC-Sierra, Inc. STANDARD PRODUCT ISSUE 2 PM5543 SARD SONET/SDH 155Mbit/s ADM Reference Design 3112 3113 3114 3115 3116 3117 3118 3119 311A-321E 321F 3220 3221 3222 3223 3224 3225 3226 3227 3228-332C 332D 332E 332F 3330 3331 3332 3333 3334 3335 3336-343A 343B 343C 343D 343E 343F 3440 3441 3442 3443 3444 3445 3446 3447 3448 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 47 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 C1 C1 C1 C1 C1 E1 C1 C1 D1 C1 C1 C1 C1 C1 C1 C1 C1 C1 D1 C1 C1 C1 C1 C1 C1 C1 C1 C1 D1 C1 C1 C1 C1 C1 C1 C1 C1 C1 F1 F1 F1 D9 D9 APL APL APL APL APL APL & C1 APL APL APL (2nd row) APL APL APL APL APL APL APL APL APL (3rd row) APL APL APL APL APL APL APL APL APL (4th row) APL APL APL APL APL APL APL APL J1 J1 J1 V1 V1 PMC-Sierra, Inc. STANDARD PRODUCT ISSUE 2 PM5543 SARD SONET/SDH 155Mbit/s ADM Reference Design 3449 344A-3548 3549 354A 354B 354C 354D 354E 354F 3550 3551 3552-3656 3657 3658 3659 365A 365B 365C 365D 365E 365F 3660-3764 3765 3766 3767 3768 3769 376A 376B 376C 376D 376E-3872 3873 3874 3875 3876 3877 3878 3879 387A 387B 387C-397E 397F -3FFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 48 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0 1 D9 D1 C1 C1 C1 C1 C1 C1 C1 C1 C1 D1 C1 C1 C1 C1 C1 C1 C1 C1 C1 1 C1 C1 C1 C1 C1 C1 C1 C1 C1 1 C1 C1 C1 C1 C1 C1 C1 C1 C1 D0 FF V1 APL (5th row) APL APL APL APL APL APL APL APL APL (6th row) APL APL APL APL APL APL APL APL D1 APL (7th row) APL APL APL APL APL APL APL APL D1 APL (8th row) APL APL APL APL APL APL APL APL OTMF trigger Unused PMC-Sierra, Inc. STANDARD PRODUCT ISSUE 2 PM5543 SARD SONET/SDH 155Mbit/s ADM Reference Design PAGE 4 ADDRESS HEX STS-3c/STM-1(AU4) with J1 Located at 0 bit7 bit6 bit5 OC1J 1 bit4 APL bit3 AV1 bit2 OC1 bit1 SPA0 bit0 OTM F SPA2 SPA1 PROM DATA HEX Description 4000 4001 4002 4003 4004 4005 4006 4007 4008 4009 400A 400B 400C-4110 4111 4112 4113 4114 4115 4116 4117 4118 4119 411A -421E 421F 4220 4221 4222 4223 4224 4225 4226 4227 4228-432C 432D 432E 432F 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 49 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D1 D1 D1 C1 C5 C1 C1 C1 C1 C1 C1 C1 D1 C1 C1 C1 C1 C1 C1 E1 C1 C1 D1 C1 C1 C1 C1 C1 C1 C1 C1 C1 D1 C1 C1 C1 APL (9th row) APL & OC1 APL APL APL APL APL APL APL APL (1st row) APL APL APL APL APL APL & C1 APL APL APL (2nd row) APL APL APL APL APL APL APL APL APL (3rd row) APL APL PMC-Sierra, Inc. STANDARD PRODUCT ISSUE 2 PM5543 SARD SONET/SDH 155Mbit/s ADM Reference Design 4330 4331 4332 4333 4334 4335 4336-443A 443B 443C 443D 443E 443F 4440 4441 4442 4443 4444 4445 4446 4447 4448 4449 444A-4548 4549 454A 454B 454C 454D 454E 454F 4550 4551 4552-4656 4657 4658 4659 465A 465B 465C 465D 465E 465F 4660-4764 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 50 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 C1 C1 C1 C1 C1 C1 D1 C1 C1 C1 C1 C1 C1 C1 C1 C1 F1 D1 D1 D9 D1 D1 1 C1 C1 C1 C1 C1 C1 C1 C1 C1 D1 C1 C1 C1 C1 C1 C1 C1 C1 C1 D1 APL APL APL APL APL APL APL (4th row) APL APL APL APL APL APL APL APL J1 V1 D1 APL (5th row) APL APL APL APL APL APL APL APL APL (6th row) APL APL APL APL APL APL APL APL PMC-Sierra, Inc. STANDARD PRODUCT ISSUE 2 PM5543 SARD SONET/SDH 155Mbit/s ADM Reference Design 4765 4766 4767 4768 4769 476A 476B 476C 476D 476E-4872 4873 4874 4875 4876 4877 4878 4879 487A 487B 487C-497E 497F-4FFF PAGE 5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0 1 C1 C1 C1 C1 C1 C1 C1 C1 C1 1 C1 C1 C1 C1 C1 C1 C1 C1 C1 D0 FF APL (7th row) APL APL APL APL APL APL APL APL D1 APL (8th row) APL APL APL APL APL APL APL APL OTMF trigger Unused STS-5 with J1 Located at 0 bit7 bit6 bit5 OC1J 1 ADDRESS HEX 5000 5001 5002 5003 5004 5005 5006 5007 5008 5009 500A-5060 5061 5062 5063 5066-50BA bit4 APL bit3 AV1 bit2 OC1 bit1 SPA0 bit0 OTM F SPA2 SPA1 PROM DATA HEX Description 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 51 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 D1 D1 D1 D1 D5 D1 D1 C1 C1 C1 1 C1 C1 E1 D1 OC1 APL (9th row) APL APL D1 APL (1st row) APL APL & C1 PMC-Sierra, Inc. STANDARD PRODUCT ISSUE 2 PM5543 SARD SONET/SDH 155Mbit/s ADM Reference Design 50BB 50BC 50BD 50BE-5114 5115 5116 5117 5118-516E 516F 5170 5171 5172 5173 5174 -51C8 51C9 51CA 51CB 51CC-5222 5223 5224 5225 5226-527C 527D 527E 527F 5280 -52D6 52D7 52D8 52D9 52DA-532A 532B-5FFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 1 1 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 0 1 C1 C1 C1 D1 C1 C1 C1 D1 C1 C1 C1 F1 D9 D1 C1 C1 C1 1 C1 C1 C1 D1 C1 C1 C1 D1 C1 C1 C1 D0 FF APL (2nd row) APL APL APL (3rd row) APL APL APL (4th row) APL APL J1 V1 APL (5th row) APL APL D1 APL (6th row) APL APL APL (7th row) APL APL APL (8th row) APL APL OTMF trigger Unused 52 PMC-Sierra, Inc. STANDARD PRODUCT ISSUE 2 PM5543 SARD SONET/SDH 155Mbit/s ADM Reference Design D.C. CHARACTERISTICS Symbol VDD IDD TA Parameter Min Max 5.5 2.5 0 50 Units V A C VDD =5.5 Test Conditions +5V DC Power 4.5 Supply Voltage +5V DC Power Supply Current Ambient Temperature 53 PMC-Sierra, Inc. STANDARD PRODUCT ISSUE 2 PM5543 SARD SONET/SDH 155Mbit/s ADM Reference Design REFERENCES PMC-930303, SONET-STXC-DS, "SONET/SDH Transport Overhead Transceiver Device Datasheet", Dec 1993, Issue 2 PMC-920518, SONET-SPTX-DS, "SONET/SDH Path Terminating Transceiver Device Datasheet", Feb 1994, Issue 6 PMC-920526, SONET-TUPP-DS, "SONET/SDH Tributary Unit Payload Processor Device Datasheet", Nov 1992, Issue 2 PMC-940528, SONET-TUPP_Plus-DS, "SONET/SDH Tributary Unit Payload Processor Device Datasheet", Jan 1995, Issue 5 PMC-920525, SONET-TUDX-DS, "SONET/SDH Tributary Unit Cross-Connect Device Datasheet", Apr 1993, Issue 2 PMC-920235, EVMB-DS, "PMC Device Evaluation Motherboard Datasheet", February 1992, Issue 1 "FORTH: A Text and Reference", Mahlon G. Kelly, Nicolas Spies, Prentice-Hall 1986 "Understanding FORTH", J. Reymann, Alfred Publishing Co., 1983 "MAX-FORTH Reference Manual (Preliminary Edition.)". New Micros Inc., 1601 Chalk Hill Rd Dallas, Texas. Tel 214 339 2204 54 PMC-Sierra, Inc. STANDARD PRODUCT ISSUE 2 PM5543 SARD SONET/SDH 155Mbit/s ADM Reference Design APPENDIX 1: SPECIAL LAYOUT CONSIDERATIONS High Speed Signal Termination Trace Impedance Control To reduce signal degradation due to reflection and radiation, the impedance of all high frequency signals should be treated as transmission lines and terminated with a matching impedance at the destination. In this design, all high speed signal traces use 50 Ohm transmission lines. SDX 1155 TXD+/RXD+/- CY7B951 TOUT+/TSER+/TCLK+/RCLK+/RINP+/RSER+/- STXC TXD+/TXCI+/RXC+/RXD+/- 50 Ohm Transmission Line All high frequency traces are modeled as microstrip transmission lines. The calculation of the trace width is calculated using the following formula. Zo = 87 5.98 x h x ln 0.8 x w + t r + 1.41 and based on the following layer setup: w t 1 Oz Copper dielectric r Ground Plane h1 t h2 h3 dielectric r dielectric r 1 Oz Copper 1 Oz Copper 1 Oz Copper Power Plane t where 55 PMC-Sierra, Inc. STANDARD PRODUCT ISSUE 2 PM5543 SARD SONET/SDH 155Mbit/s ADM Reference Design r = relative dielectric constant , nominally 5.0 for G -10 fibre - glass epoxy t = thickness of the copper , fixed according to the weight of copper selected . For 1 oz copper, the thickness is 1.4 mil. This thickness can be ignored if w is great enough. h1, h2, h3 = thickness of dielectric . w = width of copper The parameters h1, h2, and h3 can be specified. For example, if a 20 mil (including the copper thickness on both sides of the board) two layer core is selected, dielectric material that have the same relative dielectric constant can be added to both sides of the core to construct a 4 layer board. Since all the controlled impedance traces are on the component side, only h1 is relevant in calculating the trace width. The calculation for the reference design is shown in the table below: Note: The relative dielectric constant is specified to be between 4.8 and 5.4. Parameter Data 4.8 62 1.4 50 108.9 5.4 62 1.4 50 101.6 4.8 62 1.4 100 24.7 5.4 62 1.4 100 21.3 r h (mil) t (mil) Zo (Ohm) W (mil) The value of the parameter h1 is chosen to be 62 mil. Since h1 is directly proportional to the width of the traces, a small h1 will result in the 100 Ohm traces being too thin to be accurately fabricated. Wider traces can be more precisely manufactured, but they take up too much board space. Therefore, the thickness of the board should be chosen so that the traces take up as little board space as possible yet still leaving enough margin to allow accurate fabrication. In the layout enclosed, the width of the 100 Ohm traces is 24 mil and that of the 50 Ohm traces is 104 mil. 56 PMC-Sierra, Inc. STANDARD PRODUCT ISSUE 2 PM5543 SARD SONET/SDH 155Mbit/s ADM Reference Design Routing Routing is based on the design considerations as well as manufacturability. Several suggestions are listed below: 1. Turns and corners should be rounded to curves to avoid discontinuity in the signal path. 2. Allow at least 10 mil clearance among vias, traces, and pads to prevent shorts and reduce crosstalk. If possible, allow 20 mil or more clearance around vias as manufacturers may have minimum clearance requirements. For the traces that run between pads of the 100 pin edge connector, clearances of 6 mil and a trace width of 8 mil can be used. However, the number and lengths of such traces should be kept to a minimum. 3. The differential signal pairs should be of equal length so that both signals arrive at the inputs at the same time. They should also run parallel and close to one another for as long as possible so that noise will couple onto both lines and become common mode noise which is ignored by the differential inputs. 4. All power and ground traces should be made as wide as possible, up to 24 mil to provide low impedance paths for the supply current as well as to allow quick noise dissipation. Termination "Termination" applies to terminating a signal propagating down a transmission line to the characteristic impedance of line. If the line is not terminated to it's characteristic impedance, there will be reflection back down the line. The amount of reflection at the load (receiver) is given by the load reflection coefficient: rL = (RT-Zo)/(R T+Zo) where R T is the load impedance and Zo is the characteristic impedance of the line. The amount of reflection at the source (transmitter) is given by the source reflection coefficient: rS = (RS -Zo)/(R S+Zo) where R S is the source impedance and Zo is the characteristic impedance of the line. The reflected signal propagates back and forth until the "ringing" dies out. There are 4 basic types of terminations used for PECL (or ECL). They are open line termination, series termination, parallel termination, and Thevenin parallel termination. Since PECL (or ECL) signals only drive high, external biasing is need to pull the PECL signal low. This biasing has to be incorporated into the termination scheme. 57 PMC-Sierra, Inc. STANDARD PRODUCT ISSUE 2 PM5543 SARD SONET/SDH 155Mbit/s ADM Reference Design In the design, the Thevenin termination method has been used. The terminated lines are terminated to the characteristic impedance and sets the terminating (VT) voltage. The Thevenin equivalent parallel termination is shown below: Vcc R1 Transmitter Receiver R2 Zo The resistors R1 and R2 in parallel must equal Zo and the voltage at the input must pull the output of the transmitting gate to Vcc - 2 Volts. Working out the equations for PECL +5 Volt supply for Vcc gives: R2 = 2.5 * Zo R1 = R2*2/3 Note that the above examples show only one of the differential inputs. With the Thevenin termination care must be taken so that the Vcc and grounds of the differential signals are taken in close proximity of each other or the noise on Vcc and ground will not be in common with each other. Also it is not necessary to use PECL (or ECL) transmitter and receivers to drive characteristic impedance lines. The STXC Transmit and receive signals are actually AC-coupled to CY7B951 in order to obtain proper signal level to and from CY7B951 inputs and output. The method for ACcoupling is shown in the drawing below: Vcc R1 Transmitter Receiver R2 Zo 58 PMC-Sierra, Inc. STANDARD PRODUCT ISSUE 2 PM5543 SARD SONET/SDH 155Mbit/s ADM Reference Design Power and Ground Plane Noise Decoupling Only one supply voltage, nominally +5 Volts, is used by all devices on the board and referenced to by all PECL signals. One solid ground plane is used. Ferrite beads are deployed to prevent digital noise from entering analog circuits. Bypass capacitors can supply transient current and help filter out power and ground noise. They are placed as close to the pins as possible. A minimum of one 0.1 uF bypass capacitor per device is used. Wherever possible, one 0.1 uF bypass capacitor is placed at each power pin of each IC. For high speed IC's, such as the SDX1155, CY7B951 and STXC as well as oscillators, an additional 0.01 uF bypass capacitor is added to each power pin. The 10 uF electrolytic bypass capacitors are also deployed for some positions. Two large electrolytic bypass capacitors (100 uF) are placed near the 5 volt power supply input. A special power plane is provided on the component side for the Cypress CY7B951 device. The power plane under the IC provides a low impedance path connecting pin 6, 17, and 19. Pin 6 of the CY7B951 provides current for all output pins and is internally connected to pin 17 and 19. Its voltage fluctuates as the outputs switch. The voltage difference between pin 6 and pins 17 and 19 will be amplified, causing the voltage fluctuation on pin 6 to increase. When the voltage at pin 6 fluctuates, the outputs it drives will start to draw more current which causes the voltage on pin 6 to fluctuate further. Testing has shown this fluctuation can reach 2 V p-p. The low impedance power plane guarantees that pins 6, 17, and 19 are at the same voltage level so that if pin 6 fluctuates due to outputs switching, pin 17 and 19 will follow, preventing any voltage difference between them. It is also necessary to isolate the analog from the digital. The digital CMOS circuits have high immunity to external noise (approximately 0.3 * Vcc) whereas a small amount of external noise coupled into the analog circuits can be devastating. The analog circuits operate on low voltage swings (600 mVolts for the STXC PECL inputs) as compared to the large (5 Volt) of the CMOS inputs. The CMOS circuits can also generate a lot of switching noise, especially when a large number of circuits are running synchronously all timed to the same system clock. If the analog power and grounds are not isolated from each other it is unlikely that the SARD board will be able to meet the 0.01 U.I. rms. jitter specified by Bellcore. Therefore, it is necessary to isolate the digital from the analog, otherwise the analog performance can be degraded to a point of non-conformance. It is also necessary to isolate the transmit analog from the receive analog. Any noise on the receive analog power and ground or on the receive inputs will degrade jitter tolerance and add jitter to the recovered clock. It is also important to keep the analog optical receiver and CY7B951 receive path in common with the receive portion of the 59 PMC-Sierra, Inc. STANDARD PRODUCT ISSUE 2 PM5543 SARD SONET/SDH 155Mbit/s ADM Reference Design STXC, especially the grounds. The STXC PECL inputs are internally self-biased between Vcc and ground and are AC-coupled. Since the inputs are not true differential inputs, if the STXC's ground and power are in common with the optical and CY7B951 receivers the common mode noise on the input signal is also common to the biasing reference. It is especially important to keep the ground plane between the optical receiver in common with the RAVS inputs of the STXC. On the transmit side of the STXC, a 155.52 MHz clock is synthesized from a 19.44 MHz reference clock. Any added noise on the power or ground inputs impacts the resulting 155.52 MHz clock. The added noise will increase the intrinsic jitter of the transmitter. The power and ground of the CY7B951 and the optical transmitters can be in common with the analog transmit power and ground of the STXC. Since only one ground plane and one power plane is normally available, the transmit, receive, and digital power and grounds can be isolated by channels cut into the respective planes. The power and grounds should be brought from a quiet part of the board, usually where the power and grounds enter the board. Ferrite beads can also be used on the receive and transmit analog powers to prevent digital noise from entering analog circuits of the STXC, the PECL oscillator, CY7B951 and the optical transceiver. It is important to keep the receive analog power, analog ground of the STXC, the receive portion of the CY7B951 and optical transceiver power and ground common to each other. Ferrite beads are mainly used on power rails to pass DC current but to attenuate the higher frequency noise that is created by other sources. The impedance of Ferrite beads increases with frequency. At DC the ferrite bead is like a short but at higher frequencies the impedance of a ferrite bead can increase to over 100 ohms (depending on the bead and frequency). Ferrite beads attenuate high frequency noise from the power supply from getting into a circuit, but they also stop high frequency noise from leaving the circuit. It is important, therefore, to use proper bypass decoupling when using ferrite beads. Ferrite beads should be avoided on CMOS I/O power pins as the high current switching of the CMOS circuits causes a I/t noise to be introduced into the power rail. Ferrite beads should also be avoided on the ground bus as this inhibits the return currents. To reduce digital circuit switching noise, it is important to decouple every digital power pin of all devices so that the switching currents can be satisfied and thereby reduce the amount of noise introduced into the power plane. 60 PMC-Sierra, Inc. STANDARD PRODUCT ISSUE 2 PM5543 SARD SONET/SDH 155Mbit/s ADM Reference Design APPENDIX 2: BILL OF MATERIAL Item Part Name - Value Number . 1 27512_DIP-BASE 2 49FCT805_SOIC-BASE 3 74F163A_SOIC-BASE 4 5 6 7 8 74F374_SOIC-BASE 74HC138_SOIC-BASE 74HCT245_SOIC-BASE 74XXX04_SOIC-HCMOS 74XXX08_SOIC-HCMOS Part Number Jedec Type Ref Des Qty 27512 49FCT805 74F163A 74F374 74HC138 74HCT245 74HC04D 74HC08D DIP28_6 SOIC20W SOIC16 SOIC20W SOIC16 SOIC20W SOIC14 SOIC14 9 10 11 12 13 74XXX257_SOIC-HCMOS 74XXX273_SOIC-HCMOS 74XXX32_SOIC-HCMOS 74XXX373_SOIC-HCMOS 74XXX541_SOIC-HCMOS 74HC257D 74HC273DW 74HC32D 74HC373DW 74HC541DW SOIC16 SOIC20W SOIC14 SOIC20W SOIC20W 14 CAP-100000PF DIGI-KEY - SMDCAP1206 U15 U18 U8, U14, U17, U25 U38 U20, U21 U19 U5, U36, U49 U3, U29, U32, U43, U51 U16 U24, U42, U44 U22, U26, U47, U50 U27, U28 U2, U4, U6, U7, U9, U11U13, U23, U30, U31, U33, U37, U40,U41, U48 C1-C3, C5, C7, C8, 1 1 4 1 2 1 3 5 1 3 4 2 16 148 61 PMC-Sierra, Inc. STANDARD PRODUCT ISSUE 2 PM5543 SARD SONET/SDH 155Mbit/s ADM Reference Design PCC104BCT-ND 15 CAP-10000PF DIGI-KEY PCC103BNCT-ND SMDCAP805 16 17 CAPACITOR POL-100UF, 16V, ELECTRO CAPACITOR POL-10UF, 16V, TANT TEH DIGI-KEY -P1211-ND DIGI-KEY -PCT3106CT-ND CAP320 SMDTANCAP_C C10, C12, C13, C16C21, C23C31, C35C44, C48C60, C64C96, C99, C108, C110, C113-C120, C124-C129, C131-C133, C136, C137, C139, C142, C143, C145, C146, C148, C150, C151, C153-C157, C159, C160, C163-C165, C167, C168, C171-C174, C176-C179, C181-C183, C185-C191 C4, C6, C9, C1, C14, C15, C22, C34, C47, C63, C97, C109, C121, C144, C147, C149, C152, C158, C161, C162, C166, C169, C170, C175, C180, C184 C135, C138 C32, C33, C45, C61, C62, C98, C111, C112, C122, C123, C130, C134, C140, C141 P2, P3 P1 Y2 26 2 15 18 19 20 CONN100AMP_103911-8 DIN96_MALE-BASE ECLFP5Q_19_44-BASE AMP - 103911-8 DIGI-KEY A1254-ND ECLFP5Q 62 AMP_103911-8 AMP_650473-5 CRYS14 2 1 1 PMC-Sierra, Inc. STANDARD PRODUCT ISSUE 2 PM5543 SARD SONET/SDH 155Mbit/s ADM Reference Design 21 22 23 24 25 26 27 28 29 HEADER10-BASE HEADER12-BASE HEADER5X2-BASE HEADER9X3-BASE INDUCTOR-FB,50, FAIR RITE LED-RED,1-5 MA,1.8V, PCB RIGHT A LED10-RED,25MA,2.1V OSC_TTL_DIP19.44MHZ ,20 PPM,CHA RESISTOR-0,5% DIGI-KEY S101136-ND DIGI-KEY S101136-ND DIGI-KEY S201236-ND DIGI-KEY S101136-ND FAIR RITE -2743019447 DIGI-KEY -LU20091-ND DIGI-KEY -LT1066-ND K1110CA DIGI-KEY -P SIP10 SIP12 HEADER_5X2 HEADER_9X3 INDUCTOR_FB LED DIP20_LED CRYS14 SMDRES805 J2 J1 J3 J4 L1-L9 D1 D2,D3 Y1 R15, R16, R18-R24, R29, R36, R38, R41, R42, R47, R50, R52, R57, R63, R64, R87 R10, R17, R2, R30, R31, R33, R46, R62, R65-R78, R81-R86, R88 R25,R37,R43 R80 R1, R3, R6, R7, R13, R14, R34, R40, R44, R48, R49, R55 R26,R28 R56 R58,R59 1 1 1 1 9 1 2 1 21 30 RESISTOR-1.0K,5% DIGI-KEY -P SMDRES805 29 31 32 33 RESISTOR-10K,5% RESISTOR-120,5% RESISTOR-124,1% DIGI-KEY -P SMDRES805 SMDRES805 SMDRES805 3 1 12 34 35 36 RESISTOR-27,5% RESISTOR-270,5% RESISTOR-316,1% DIGI-KEY -P SMDRES805 SMDRES805 SMDRES805 2 1 2 63 PMC-Sierra, Inc. STANDARD PRODUCT ISSUE 2 PM5543 SARD SONET/SDH 155Mbit/s ADM Reference Design 37 38 39 40 41 RESISTOR-330,5% RESISTOR-499,1% RESISTOR-59,1% RESISTOR-634,1% RESISTOR-84.5,1% DIGI-KEY -P SMDRES805 SMDRES805 SMDRES805 SMDRES805 SMDRES805 R9 R79 R60,R61 R53 R2, R4, R5, R8, R11, R12, R32, R35, R39, R45, R51, R54 RN5,RN15,RN 16 RN1-RN4, RN6, RN9, RN10, RN12RN14, RN17 RN8,RN11 1 1 2 1 12 42 RES_ARRAY_15_SMD10K RES_ARRAY_15_SMD1K 43 DIGI-KEY -766-161R SOIC16 3 SOIC16 11 44 RES_ARRAY_15_SMD270 RES_ARRAY_8_SMD-27 45 46 47 48 49 50 51 52 SDX1155-BASE SPTX-BASE STXC-BASE SY69951-BASE TST_PT-BASE TUDX-BASE TUPP_PLUS-BASE DIGI-KEY -766-161R SOIC16 2 SOIC16 RN7 1 LCD-PMDSOCKET PQFP160 PQFP160 SOIC28W TST_PT_1 PQFP160 PQFP160 U1 U39 U45 U46 TP1-TP14 U34,U35 U10 1 1 1 1 14 2 1 64 PMC-Sierra, Inc. STANDARD PRODUCT ISSUE 2 PM5543 SARD SONET/SDH 155Mbit/s ADM Reference Design APPENDIX 3: SCHEMATICS 65 PMC-Sierra, Inc. STANDARD PRODUCT ISSUE 2 PM5543 SARD SONET/SDH 155Mbit/s ADM Reference Design APPENDIX 4: OTHER LAYOUT DRAWINGS 66 PMC-Sierra, Inc. STANDARD PRODUCT ISSUE 2 PM5543 SARD SONET/SDH 155Mbit/s ADM Reference Design NOTES 67 PMC-Sierra, Inc. STANDARD PRODUCT ISSUE 2 PM5543 SARD SONET/SDH 155Mbit/s ADM Reference Design Seller will have no obligation or liability in respect of defects or damage caused by unauthorized use, mis-use, accident, external cause, installation error, or normal wear and tear. There are no warranties, representations or guarantees of any kind, either express or implied by law or custom, regarding the product or its performance, including those regarding quality, merchantability, fitness for purpose, condition, design, title, infringement of thirdparty rights, or conformance with sample. Seller shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon, the information contained in this document. In no event will Seller be liable to Buyer or to any other party for loss of profits, loss of savings, or punitive, exemplary, incidental, consequential or special damages, even if Seller has knowledge of the possibility of such potential loss or damage and even if caused by Seller's negligence. (c) 1996 PMC-Sierra, Inc. PMC-951036(P2) Issue date: July, 1996. 68 |
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