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| 1CY M14 41 CYM1441 256K x 8 Static RAM Module Features * High-density 2-megabit SRAM module * High-speed CMOS SRAMs -- Access time of 20 ns * Low active power -- 5.3W (max.) * SMD technology * Separate data I/O * 60-pin ZIP package * TTL-compatible inputs and outputs * Low profile -- Max. height of 0.5 in. * Small PCB footprint -- 1.14 sq. in. Functional Description The CYM1441 is a very high performance 2-megabit static RAM module organized as 256K words by 8 bits. The module is constructed using eight 256K x 1 static RAMs in SOJ packages mounted onto an epoxy laminate substrate with pins. Two chip selects (CSL and CSU) are used to independently enable the upper and lower 4 bits of the data word. Writing to the memory module is accomplished when the chip select (CS) and write enable (WE) inputs are both LOW. Data on the eight input pins (DI0 through DI7) is written into the memory location specified on the address pins (A0 through A17). Reading the device is accomplished by taking chip select (CS) LOW while write enable (WE) remains inactive or HIGH. Under these conditions, the contents of the memory location specified on the address pins will appear on the appropriate data output pins (DO0 through DO7). The data output pins remain in a high- impedance state unless the module is selected and write enable (WE) is HIGH.Two pins (PD0 and PD1) are used to identify module memory density in applications where alternate versions of the JEDEC-standard modules can be interchanged. Logic Block Diagram A0 - A17 WE CSU Pin Configuration ZIP TopView (OPEN)PD 0 NC VCC DI0 DO0 A0 A2 A4 256K x 1 A6 SRAM GND DI1 DO1 WE DO4 - DO7 A9 CSL NC NC VCC DI2 DO2 A10 A12 A14 A16 NC DI3 DO3 NC NC GND 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 256K x 1 SRAM 256K x 1 SRAM 256K x 1 SRAM DI4 - DI7 CSL GND PD1 (GND) NC DI4 DO4 NC A1 A3 A5 A7 DI5 DO5 VCC A8 NC CSU NC NC DI6 DO6 GND A11 A13 A15 A17 DI7 DO7 VCC NC NC 1441-2 256K x 1 SRAM 256K x 1 SRAM 256K x 1 SRAM 256K x 1 SRAM DI0 - DI3 1441-1 DO0 - DO3 Cypress Semiconductor Corporation * 3901 North First Street * San Jose * CA 95134 * 408-943-2600 November 1990 - Revised March 1995 CYM1441 Selection Guide 1441-20 Maximum Access Time (ns) Maximum Operating Current (mA) Maximum Standby Current (mA) Shaded area contains preliminary information. 20 960 320 1441-25 25 960 320 1441-35 35 960 320 1441-45 45 960 320 Maximum Ratings (Above which the useful life may be impaired.) Storage Temperature ................................. -55C to +125C Ambient Temperature with Power Applied............................................... -10C to +85C Supply Voltage to Ground Potential ............... -0.5V to +7.0V DC Voltage Applied to Outputs in High Z State................................................-0.5V to +7.0V DC Input Voltage ............................................-0.5V to +7.0V Operating Range Range Commercial Ambient Temperature 0C to +70C VCC 5V 10% Electrical Characteristics Over the Operating Range Parameter VOH VOL VIH VIL IIX IOZ ICC ISB1 ISB2 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[1] GND < VI < VCC GND < VO < VCC, Output Disabled VCC = Max., IOUT = 0 mA, CS < VIL Max. VCC, CS > VIH, Min. Duty Cycle = 100% Max. VCC, CS > VCC - 0.2V, VIN > VCC - 0.2V or VIN < 0.2V Input Load Current Output Leakage Current VCC Operating Supply Current Automatic CS Power-Down Current Automatic CS Power-Down Current Test Conditions VCC = Min., IOH = -4.0 mA VCC = Min., IOL = 12.0 mA 2.2 -0.5 -80 -50 Min. 2.4 0.4 VCC 0.8 +80 +50 960 320 160 Max. Unit V V V V A A mA mA mA Capacitance[2] Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 5.0V Max. 60 15 Unit pF pF AC Test Loads and Waveforms R1329 5V OUTPUT 30 pF INCLUDING JIG AND SCOPE R2 202 5V OUTPUT 5 pF INCLUDING JIG AND SCOPE R2 202 R1329 3.0V 90% GND < 5 ns 1441-3 ALL INPUT PULSES 90% 10% < 5 ns 1441-4 10% (a) Equivalent to: OUTPUT THEVENIN EQUIVALENT 125 1.9V (b) 2 CYM1441 AC Test Loads and Waveforms Notes: 1. VIN (min.) = -3.0V for pulse widths less than 20 ns. 2. Tested on a sample basis. Switching Characteristics Over the Operating Range[3] 1441-20 Parameter READ CYCLE tRC tAA tOHA tACS tLZCS tHZCS tPU tPD WRITE tWC tSCS tAW tHA tSA tPWE tSD tHD tLZWE tHZWE Read Cycle Time Address to Data Valid Data Hold from Address Change CS LOW to Data Valid CS LOW to Low Z CS HIGH to High Z[4] CS LOW to Power-Up CS HIGH to Power-Down CYCLE[5] Write Cycle Time CS LOW to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE HIGH to Low Z WE LOW to High Z[4] 20 15 15 2 0 15 13 0 3 0 13 25 20 20 2 0 20 15 0 3 0 15 35 30 30 2 0 25 20 0 3 0 20 45 35 35 2 2 30 20 0 3 0 25 ns ns ns ns ns ns ns ns ns ns 0 20 3 12 0 25 3 20 3 15 0 35 20 20 3 25 3 25 0 45 25 25 3 35 3 30 35 35 3 45 45 45 ns ns ns ns ns ns ns ns Description Min. Max. 1441-25 Min. Max. 1441-35 Min. Max. 1441-45 Min. Max. Unit Shaded area contains preliminary information. Switching Waveforms [6,7] Read Cycle No. 1 tRC ADDRESS tAA tOHA DATAOUT PREVIOUS DATA VALID DATA VALID 1441-5 Notes: 3. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 4. tHZCS and tHZWE are specified with C L = 5 pF as in part (b) of AC Test Loads and Waveforms. Transition is measured 500 mV from steady state voltage. 5. The internal write time of the memory is defined by the overlap of CS LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. 6. WE is HIGH for read cycle. 7. Device is continuously selected, CS = VIL. 3 CYM1441 Switching Waveforms (continued) Read Cycle No. 2 CS [6,8] tRC tACS tLZCS HIGH IMPEDANCE DATAOUT tPU VCC SUPPLY CURRENT 50% DATA VALID tHZCS HIGH IMPEDANCE tPD ICC 50% ISB 1441-6 Write Cycle No. 1 (WE Controlled) [5] tWC ADDRESS tSCS CS tSA WE tSD DATAIN DATA VALID tHZWE DATAOUT DATA UNDEFINED 1441-7 tAW tPWE tHA tHD tLZWE HIGH IMPEDANCE Write Cycle No. 2 (CS Controlled) ADDRESS [5,9] tWC tSA CS tAW tSCS tHA tPWE WE tSD DATAIN DATA VALID tHZWE DATAOUT HIGH IMPEDANCE DATA UNDEFINED 1441-8 tHD Notes: 8. Address valid prior to or coincident with CS transition LOW. 9. If CS goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. 4 CYM1441 Truth Table CS H L L WE X H L Input/Output High Z Data Out Data In Read Write Mode Deselect/Power-Down Ordering Information Speed 20 25 35 45 Ordering Code CYM1441PZ-20C CYM1441PZ-25C CYM1441PZ-35C CYM1441PZ-45C Package Name PZ04 PZ04 PZ04 PZ04 Package Type 60-Pin ZIP Module 60-Pin ZIP Module 60-Pin ZIP Module 60-Pin ZIP Module Operating Range Commercial Commercial Commercial Commercial Shaded area contains preliminary information. Document #: 38-M-00020-B Package Diagrams 60-Pin ZIP Module PZ04 BottomView 0.050 3.440 3.460 0.330 MAX 0.050 0.120 0.150 0.500 MAX 0.008 0.014 0.135 0.165 0.015 0.025 0.250 TYP 0.100 TYP 0.050 TYP 0.100 TYP Pin 1 DIMENSIONS IN INCHES MIN. MAX. (c) Cypress Semiconductor Corporation, 1995. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. |
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