View GS9005A_330537.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

GENLINXTM GS9005A
Serial Digital Receiver
DATA SHEET
FEATURES * * * automatic cable equalization (typically 300m of high quality cable at 270Mb/s) fully compatible with SMPTE 259M and operational to 400 Mb/s adjustment free receiver when used with the GS9000B or GS9000S decoder and GS9010A Automatic Tuning Sub-system signal strength indicator selectable cable or direct digital inputs 28 pin PLCC packaging DEVICE DESCRIPTION The GS9005A is a monolithic IC designed to receive SMPTE 259M serial digital video signals. This device performs the functions of automatic cable equalization and data and clock recovery. It interfaces directly with the GENLINXTM GS9000B or GS9000S decoder, and GS9010A Automatic Tuning Subsystem. The VCO centre frequencies are controlled by external resistors which can be selected by applying a two bit binary code to the Standards Select input pins. An additional feature is the Signal Strength Indicator output which provides a 0.5V to 0V analog output relative to VCC indicating the amount of equalization being applied to the signal. The GS9005A is packaged in a 28 pin PLCC operating from a single +5 or -5 volt supply. SPECIAL NOTE: RVCO1 and RVCO2 are functional over a reduced temperature range of TA=0 C to 50 C. RVCO0 and RVCO3 are functional over the full temperature range of TA=0 C to 70 C. This limitation does not affect operation with the GS9010A ATS.
GS9005A
28 SIGNAL STRENGTH INDICATOR FILTER CONTROL PEAK DETECTOR VOLTAGE VARIABLE FILTER CABLE 8,9 IN EQUALIZER DIGITAL 5,6 IN 24 DATA LATCH 25 22 23 DC RESTORER ANALOG DIGITAL SELECT LOGIC COMPARATOR AGC 2 CAPACITOR
* * *
APPLICATIONS * 4SC, 4:2:2 and 360 Mb/s serial digital interfaces ORDERING INFORMATION
PART NUMBER GS9005ACPJ GS9005ACTJ PACKAGE 28 Pin PLCC 28 Pin PLCC Tape TEMPERATURE 0O C to 70O C 0O C to 70O C
16
OUTPUT 'EYE' MONITOR
1
A/D
SERIAL DATA SERIAL DATA SERIAL CLOCK SERIAL CLOCK
PHASE
COMPARATOR
CARRIER DETECT
19 CARRIER DETECT CHARGE PUMP
10 /2
/2 ENABLE
20 LOOP FILTER 12 PLL 13 14 15 17 VCO STANDARD SELECT 21
SS0 SS1
Revision Date: August 1997
FUNCTIONAL BLOCK DIAGRAM
Document No. 520 - 28 - 11
GENNUM CORPORATION P.O. Box 489, Stn A, Burlington, Ontario, Canada L7R 3Y3 tel. (905) 632-2996 fax: (905) 632-5946
Gennum Japan Corporation: A-302 Miyamae Village, 2-10-42 Miyamae, Suginami-ku, Tokyo 168, Japan tel. (03) 3334-7700 fax (03) 3247-8839
ABSOLUTE MAXIMUM RATINGS
PARAMETER Supply Voltage Input Voltage Range (any input) DC Input Current (any one input) Power Dissipation Operating Temperature Range Storage Temperature Range Lead Temperature (soldering, 10 seconds) VALUE / UNITS 5.5 V VCC +0.5 to VEE-0.5 V 5 mA 750 mW 0C T 70C A -65C T S150C 260C CAUTION
ELECTROSTATIC SENSITIVE DEVICES
DO NOT OPEN PACKAGES OR HANDLE EXCEPT AT A STATIC-FREE WORKSTATION
GS9005A RECEIVER DC ELECTRICAL CHARACTERISTICS
VS = 5V, TA = 0C to 70C, R L = 100 to (VCC - 2V) unless otherwise shown.
PARAMETER Supply Voltage Power Consumption Supply Current (Total) Serial Data & Clock Output Logic Inputs (1, 10, 20, 21) Carrier Detect Output Voltage Signal Strength Indicator Output Direct Digital Input Levels (5, 6) - High - Low - High - Low
SYMBOL VS PD IS V OH V OL V IH MIN V IL MAX V CDL V CDH V SS V DDI
CONDITIONS Operating Range
MIN 4.75 -
TYP 5.0 500 122 0.2 5.0 -
MAX 5.25 700 160 -0.88 -1.6 +0.8 0.4 0 2000
UNITS V mW mA V V V V V V V mVp-p
NOTES
see Figure13 with respect to V CC with respect to VCC with respect to V EE with respect to V EE
with respect to VEE Open Collector - Active High
T A = 25C T A = 25C
-1.025 -1.9 +2.0 -
R L = 10 k to VCC
4.0
See Note 2
-0.6 200
with respect to V CC Differential Drive
GS9005A RECEIVER AC ELECTRICAL CHARACTERISTICS
V S = 5V, TA = 0C to 70C, R L = 100 to (VCC - 2V) unless otherwise shown.
PARAMETER Serial Data Bit Rate Serial Clock Frequency Output Signal Swing Serial Data to Serial Clock Synchronization Lock Times Equalizer Gain Jitter
SYMBOL BR SDO SLK VO td
CONDITION T A = 25C T A = 25C T A = 25C See Waveforms
MIN 100 100 700 -
TYP 800 -500
MAX 400 400 900 -
UNITS Mb/s MHz mV p-p ps
NOTES
see Figure11 see Figure12 Data lags Clock
t LOCK AV EQ tJ RIN C IN V OEM
See Note 1 T A = 25C T A = 25C 0 metres, 270 Mb/s T A = 25C T A = 25C R L = 50 to VCC
30 -
36 100
10 -
s dB ps p-p pF mVp-p at 135 MHz see Figure15
Input Resistance (SDI/SDI) Input Capacitance (SDI/SDI) Output Eye Monitor
3k -
5k 1.8 40
-
see Figure14 see Figure14
NOTES: 1. Switching between two sources of the same data rate. 2. With weaker signals V SS approaches VCC.
520 - 28 - 11
2
GS9005A Re - clocking Receiver - Detailed Device Description The GS9005A Reclocking Receiver is a bipolar integrated circuit containing a built-in cable equalizer and circuitry necessary to re-clock and regenerate the NRZI serial data stream. Packaged in a 28 pin PLCC, the receiver operates from a single five volt supply at data rates in excess of 400 Mb/s. Typical power consumption is 500 mW. Typical output jitter is 100 ps at 270 Mb/s. Serial Digital signals are applied to either a built-in analog cable equalizer via the SDI and SDI inputs (pins 8,9) or via the direct digital inputs DDI and DDI (pins 5,6). Cable Equalizer The Serial Digital signal is connected to the input either differentially or single ended with the unused input being decoupled. The equalized signal is generated by passing the cable signal through a voltage variable filter having a characteristic which closely matches the inverse cable loss characteristic. Additionally, the variation of the filter characteristic with control voltage is designed to imitate the variation of the inverse cable loss characteristic as the cable length is varied. The amplitude of the equalized signal is monitored by a peak detector circuit which produces an output current with a polarity corresponding to the difference between the desired peak signal level and the actual peak signal level. This output is integrated by an external AGC filter capacitor (AGC CAP pin 2), providing a steady control voltage for the voltage variable filter. A separate signal strength indicator output, (SSI pin 28), proportional to the amount of AGC is also provided. As the filter characteristic is varied automatically by the application of negative feedback, the amplitude of the equalized signal is kept at a constant level which is representative of the original amplitude at the transmitter. The equalized signal is then DC restored, effectively restoring the logic threshold of the equalized signal to its correct level irrespective of shifts due to AC coupling. As the final stage of signal conditioning, a comparator converts the analog output of the DC restorer to a regenerated digital output signal. An OUTPUT 'EYE' MONITOR (pin 16), allows verification of signal integrity after equalization but before reslicing. Analog/Digital Select A 2:1 multiplexer selects either the equalized (analog) signal or a differential ECL data (digital) signal as input to the reclocker PLL. 3 A logical HIGH applied to the Analog/Digital Select input (1) routes the equalized signal while a logic LOW routes the direct digital signal to the reclocker. Phase Locked Loop The phase comparator itself compares the position of transitions in the incoming signal with the phase of the local oscillator (VCO). The error-correcting output signals are fed to the charge pump in the form of short pulses. The charge pump converts these pulses into a "charge packet" which is accurately proportional to the system phase error. The charge packet is then integrated by the second-order loop filter to produce a control voltage for the VCO. During periods when there are no transitions in the signal, the loop filter voltage is required to hold precisely at its last value so that the VCO does not drift significantly between corrections. Commutating diodes in the charge pump keep the output leakage current extremely low, minimizing VCO frequency drift. The VCO is implemented using a current-controlled multivibrator, designed to deliver good stability, low phase noise and wide operating frequency capability. The frequency range is design-limited to 10% about the oscillator centre frequency. VCO Centre Frequency Selection The centre frequency of theVCO is set by one of four external current reference resistors (RVCO0-RVCO3) connected to pins 13,14,15 or 17. These are selected by two logic inputs SS0 and SS1 (pins 20, 21) through a 2:4 decoder according to the following truth table. SS1 0 0 1 1 SS0 0 1 0 1 Resistor Selected RVCO0 (13) RVCO1 (14) RVCO2 (15) RVCO3 (17)
As an alternative, the GS9010A Automatic Tuning Sub-system and the GS9000B or GS9000S Decoder may be used in conjunction with the GS9005A to obtain adjustment free and automatic standard select operation (see Figure 20). With the VCO operating at twice the clock frequency, a clock phase which is centred on the eye of the locked signal is used to latch the incoming data, thus maximising immunity to jitter-induced errors. The alternate phase is used to latch the output re-clocked data SDO and SDO (pins 25, 24). The true and inverse clock signals themselves are available from the SCO and SCO pins 23 and 22.
520 - 28 - 11
AGC VCC1 VEE1 CAP
tD tD
A/D
SSI
VEE2 27
VCC4 26 25 24 23 SD0 SD0 SC0 SC0 SS1 SS0 CD
4
SERIAL DATA OUT (SD0)
3
2
28
DDI DDI VCC2
5 6 7 8 9 10 11 12 13 14 15 16 17 18
SERIAL CLOCK OUT (SCK)
50%
50%
SDI SDI
GS9005A TOP VIEW
22 21 20 19
/2 EN
Fig.1 Waveforms
VEE3
LOOP RVCO0 RVCO1 RVCO2 OEM RVCO3 VCC3 FILT
Fig. 2 GS9005A Pin Connections GS9005 & GS9005A PIN DESCRIPTIONS PIN NO. 1 SYMBOL A/D TYPE Input DESCRIPTION Analog/Digital Select. TTL compatible input used to select the input signal source. A logic HIGH routes the Equalizer inputs (pins 8 and 9) to the PLL and a logic LOW routes the Direct Digital inputs (pins 5 and 6) to the PLL. 2 3 4 5,6 AGC CAP VEE1 VCC1 DDI/DDI Input Input AGC Capacitor. Connection for the AGC capacitor. Power Supply. Most negative power supply connection. (Equalizer) Power Supply. Most positive power supply connection. (Equalizer) Direct Data Inputs (true and inverse). Pseudo-ECL, differential serial data inputs. These are selected when the A/D input (pin 1) is at logic LOW and are self biased to 1.2 volts below VCC. They may be directly driven from true ECL drivers when VEE = -5V and VCC= 0 V. 7 8,9 VCC2 SDI/SDI Input Power Supply. Most positive power supply connection. ( Phase detector, A/D select, carrier detect). Serial Data Inputs (true and inverse). Differential analog serial data inputs. Inputs must be AC coupled and may be driven single ended. These inputs are selected when the A/D input (pin 1) is logic HIGH. 10 11 12 13 /2 EN VEE3 LOOP FILT RVCO0 Input Input /2 Enable-TTL compatible input used to enable the divide by 2 function. Power Supply. Most negative power supply connection. (VCO, Mux, Standard Select) Loop Filter. Node for connecting the loop filter components. VCO Resistor 0. Analog current input used to set the centre frequency of the VCO when the two Standard Select bits (pins 20 and 21) are set to logic 0,0. A resistor is connected from this pin to VEE. 14 RVCO1 Input VCO Resistor 1. Analog current input used to set the centre frequency of the VCO when Standard Select bit 0 (pin 20) is set HIGH and bit 1 (pin 21) is set LOW. A resistor is connected from this pin to VEE. 15 RVCO2 Input VCO Resistor 2. Analog current input used to set the centre frequency of the VCO when Standard Select bit 0 (pin 20) is set LOW and bit 1 (pin 21) is set HIGH. A resistor is connected from this pin to VEE. 16 17 OEM RVCO3 Output Input Output Eye Monitor Analog voltage representing the serial bit stream after equalization but before reslicing. VCO Resistor 3. Analog current input used to set the centre frequency of the VCO when the two Standard Select bits (pins 20 and 21) are set HIGH. A resistor is connected from this pin to VEE.
520 - 28 - 11
4
GS9005 & GS9005A PIN DESCRIPTIONS cont.
PIN NO 18 19
SYMBOL VCC3 CD
TYPE
DESCRIPTION Power Supply. Most positive power supply connection. (VCO, MUX, standards select).
Output
Carrier Detect. Open collector output which goes HIGH when a signal is present at either the Serial Data inputs or the Direct Digital inputs. This output is used in conjunction with the GS9000B or GS9000S in the Automatic Standards Select Mode to disable the 2 bit standard select counter. This pin should see a low impedance (e.g. 1nF to AC Gnd)
20,21
SS0, SS1 Inputs
Standard Select Inputs. TTL inputs to the 2:4 multiplexer used to select one of four VCO centre frequency setting resistors (RVCO0 - RVCO3). When both SS0 and SS1 are LOW, RVCO0 is selected. When SS0 is HIGH and SS1 is LOW, RVCO1 is selected. When SS0 is LOW and SS1 is HIGH, RVCO2 is selected and when both SS0 and SS1 are HIGH, RVCO3 is selected. These pins should see a low impedance (e.g. 1nF to AC Gnd)
22,23
SCO/SCO Outputs
Serial Clock Outputs (inverse and true). Pseudo-ECL differential outputs of the extracted serial clock. These outputs require 390 pull-down resistors to VEE.
24,25
SDO/SDO Outputs
Serial Data Outputs (inverse and true). Pseudo-ECL differential outputs of the regenerated serial data. These outputs require 390 pull-down resistors to VEE.
26 27 28
VCC4 VEE2 SSI
Power Supply. Most positive power supply connection. (ECL outputs) Power Supply. Most negative power supply connection. (Phase detector, A/D select, Carrier detect) Signal Strength Indicator. Analog output which indicates the amount of AGC action. This output indirectly indicates the amount of equalization and thus cable length.
INPUT / OUTPUT CIRCUITS
VCC + VCC VCC 16A 2k 2k 1.2V
VCC 1k 1k
A/D Pin 1
DDI Pin 5 DDI Pin 6 + 1.6V -
50A
380A
Fig. 3 Pins 1, 5 and 6
5
520 - 28 - 11
INPUT / OUTPUT CIRCUITS cont.
IVCO
(1.9 - 2.4V)
LOOP FILTER (1.8 - 2.7V)
Pin 13 RVCO 0 Pin 14 RVCO 1 Pin 15 RVCO 2
400 400 400 400
Pin 17 RVCO 3
Fig. 4 Pins 13, 14, 15 and 17
VCC VCC4 200
200
10k
10k SDO or SCO Pin 25, 24 SDO or SCO Pin 23, 22 VCC
VCC 3k
800
Fig. 5 Pins 25, 24, 23 and 22
520 - 28 - 11
6
INPUT / OUTPUT CIRCUITS cont.
VCC 500 SSI Pin 28 5k AGC CAP Pin 2 VCC + 2V 1k + 0.4V 5k 5k 620 SDI Pin 8 SDI Pin 9 LOOP FILTER Pin 12 VCC VCC VCC
1.5k
2k
920A
920A
Fig. 7 Pin 12
Fig. 6 Pins 28, 2, 8 and 9
VCC VCC 10k
OEM Pin 16
CD Pin 19
200 5mA 5mA
Fig. 8 Pin 16
VCC 40A VCC 40A VCC 18A
Fig. 9 Pin 19
VCC
VCC
SS1 Pin 21
/2 EN Pin 10 SSO Pin 20
55A
480A
+ -
1.6V
Fig. 10 Pins 20, 21 and 10
7
520 - 28 - 11
TYPICAL PERFORMANCE CURVES
(VS = 5V, TA = 25C)
500 450
900
850
FREQUENCY (MHz)
SERIAL OUTPUTS (mV)
400 350 300 250 /2 OFF 200 /2 ON 150
VS = 5.25V 800 VS = 5.00V
750
700
VS = 4.75V
650 100 50 600 1 2 3 4 5 6 7 8 9 10 0 10 20 30 40 50 60 70
FREQUENCY SETTING RESISTANCE (k)
TEMPERATURE (C)
Fig. 11 Clock Frequency
Fig. 12 Serial Outputs
140 j1 135 130 V S = 5.25V j0.5 j2
CURRENT (mA)
125 120
V S = 5.00V j0.2
115 110 105 100 0 10 20 30
VS = 4.75V
j5
0
0.2
3000
0.5
1
2
5 270
40
50
60
70 -j0.2
TEMPERATURE (C)
Fig. 13 Supply Current
-j0.5 800 700 600 -j1
Frequencies in MHz, impedances normalized to 50 .
Fig. 14 Equalizer Input Impedance
270 Mb/s
JITTER p-p (ps)
500 400 300 200 100 0 0 25 50 75 100 125 150 175 200 225 250 275 300
143 Mb/s
INPUT CABLE LENGTH - 8281 (m)
Fig. 15 Output Jitter vs Input Cable Length at 143 & 270 Mb/s
520 - 28 - 11
8
1620
810
-j2
-j5
+5V +5V 10 + 0.1
ANALOG DIGITAL SSI
0.1
+5V
0.1
390 4 3 2 1 28 27 26
VEE1
VCC1
VEE2
AGC
0.1 INPUT 75 47p
ECL DATA INPUTS 5 DDI 6 DDI 7 VCC2 8 SDI 9 SDI 10 /2
VCC4
A/D
SSI
390 25 24 23 22 21 20 19 +5V 100 100 100 100 390 390 CARRIER DETECT OUTPUT 10k DATA DATA CLOCK CLOCK
SDO SDO SCO
GS9005A
SCO SS1 SS0
EYEOUT
RVCO0
RVCO1
RVCO2
RVCO3
LOOP
11 VEE3
75
12 13 14 15 16 17 18
VCC3
47p
CD
+5V
22n
113 5.6p 910 +5V 10n /2 /1 See Figure 18
0.1
STAR ROUTED
LOOP VOLTAGE TEST POINT
All resistors in ohms, all capacitors in microfarads, all inductors in henries unless otherwise stated.
Fig.16 GS9005A Typical Test Circuit Using +5V Supply
TEST SETUP Figure 16 shows a typical circuit for the GS9005A using a +5 volt supply. The four 0.1F decoupling capacitors must be placed as close as possible to the corresponding VCC pins. The loop voltage can be conveniently measured across the 10nF capacitor in the loop filter. Tuning procedures are described in the Temperature Compensation Section (page 11). The fixed value frequency setting resistors should be placed close to the corresponding pins on the GS9005A. The layout of the loop filter and RVCO components requires careful attention. This has been detailed in an application note entitled "Optimizing Circuit and Layout Design of the GS9005A/15A", Document No. 521 - 32 - 00. When the Direct Digital Inputs are not used, one of these inputs should be connected to VCC to avoid picking up noise and unwanted signals. The Carrier Detect is an open-collector active high output requiring a pull-up resistor of approximately 10 k. The SS0, SS1, CD pins should see a low AC impedance. This is particularly important when driving the SS0, SS1 pins with external logic. The use of 1 nF decoupling capacitors at these pins ensures this. Figure 17 shows the GS9005A connections when using a -5 volt supply.
9
520 - 28 - 11
ANALOG 10 + 0.1 SSI -5V DIGITAL
0.1 -5V
-5V 0.1
390 4 ECL DATA INPUTS 5 6 0.1 7 INPUT 75 -5V 47p 47p 75 3 2 1 28 27 26
-5V DATA DATA CLOCK CLOCK
AGC
VCC1
VEE1
A/D
SSI
VEE2
VCC4
390 25 24 23 22 21 20 19 10k CARRIER DETECT OUTPUT 100 100 100 100 390 390
DDI DDI VCC2
SDO SDO SCO
GS9005A
8 SDI 9 SDI 10 /2
SCO SS1
EYEOUT
SS0
RVCO0
RVCO1
RVCO2
RVCO3
LOOP
VCC3
-5V
11 VEE3
CD
12 13 14 15 16 17 18
113 22n 5.6p 910 -5V
0.1
10n /2 /1 See Figure 18
-5V
STAR -5V ROUTED
LOOP VOLTAGE
All resistors in ohms, all capacitors in microfarads, all inductors in henries unless otherwise stated.
Fig. 17 GS9005A Typical Test Circuit Using -5V Supply
VCO Frequency Setting Resistors There are two modes of VCO operation available in the GS9005A. When the /2 ENABLE (pin 10) is LOW, any of the four VCO frequency setting resistors, RVCO0 through RVCO3 (pins 13, 14, 15 and 17) may be used for any data rate from 100 Mb/s to over 400 Mb/s. For example, for 143 Mb/s data rate, the value of the total RVCO resistance is approximately 6k8 and for 270 Mb/s operation, the value is approximately 3k5. The 5k potentiometers will then tune the desired data rate near their mid-points. Jitter performance at the lower data rates (143, 177 Mb/s) is improved by operating the VCO at twice the normal frequency. This is accomplished by enabling the /2 function which activates an additional divide by two block in the PLL section of the GS9005A. When the /2 ENABLE is HIGH two of the RVCO pins are assigned to data rates below 200 Mb/s and two are assigned to data rates over 200 Mb/s. The selection is dependent upon the level of the STANDARD SELECT BIT, SS1 (pin 21). When SS1 is LOW, RVCO0 and RVCO1 (pins 13 and 14) are used for the higher data rates. When SS1 is HIGH, the VCO frequency is now twice the bit rate and its frequency is set by RVCO2 and RVCO3 (pins 15 and 17). For 143 Mb/s and 270 Mb/s operation, (the VCO is at 286 MHz and 270 MHz respectively) the total resistance required is approximately the same for both data rates. This also applies for 177 Mb/s and 360 Mb/s operation (the VCO is tuned to 354 MHz and 360 MHz respectively). This means that one potentiometer may be used for each frequency pair with only a small variation of the fixed resistor value. This halves the number of adjustments required.
520 - 28 - 11
10
Temperature Compensation Figure 18 shows the connections for the frequency setting resistors for the various data rates. The compensation shown for 360 Mb/s and 177 Mb/s with Divide by 2 ON, is useful to a maximum ambient temperature of 50C. If the Divide by 2 function is not enabled by the /2 ENABLE input, no compensation is needed for the 143 Mb/s and 177 Mb/s data rates. The resistor connections are shown in Figure 19. In both cases, the 0.1 F capacitor that bypasses the potentiometer should be star routed to VEE 3.
1k
10k 0.1F
VEE Divide by 2 is OFF 143Mb/s and 177 Mb/s using any RVCO0 pins
Fig. 19
5.6k 1N914 5k 1.3k 4.3k 1N914 5k 1.3k
Non - Temperature Compensated Resistor Values for 143 Mb/s and 177 Mb/s
0.1F
0.1F
Loop Bandwidth
VEE Divide by 2 is OFF 270 Mb/s using RVCO0 or RVCO1 VEE Divide by 2 is ON 143 Mb/s using RVCO2 or RVCO3
The loop bandwidth is dependant upon the internal PLL gain constants along with the loop filter components connected to pin 12. In addition, the impedance seen by the RVCO pin also influences the loop characteristics such that as the impedance drops, the loop gain increases. Applications Circuit
1k
1k
1k
0.1F 1N914
1k 0.1F 1N914 VEE Divide by 2 is ON 177 Mb/s using RVCO2 or R VCO3
Figure 20 shows an application of the GS9005A in an adjustment free, multi-standard serial to parallel convertor. This circuit uses the GS9010A Automatic Tuning Subsystem IC and a GS9000B or GS9000S Decoder IC. The GS9005A may be replaced with a GS9015A Reclocker IC if cable equalization is not required. The GS9010A ATS eliminates the need to manually set or externally temperature compensate the Receiver or Reclocker VCO. The GS9010A can also determine whether the incoming data stream is 4sc NTSC,4sc PAL or component 4:2:2. The GS9010A includes a ramp generator/oscillator which repeatedly sweeps the Receiver VCO frequency over a set range until the system is correctly locked. An automatic fine tuning (AFT) loop maintains the VCO control voltage at it's centre point through continuous, long term adjustments of the VCO centre frequency. When an interruption to the incoming data stream is detected by the Receiver, the Carrier Detect goes LOW and opens the AFT loop in order to maintain the correct VCO frequency for a period of at least 2 seconds. This allows the Receiver to rapidly relock when the signal is re-established. During normal operation, the GS9000B or GS9000S Decoder provides continuous HSYNC pulses which disable the ramp/oscillator of the GS9010A. This maintains the correct Receiver VCO frequency.
VEE Divide by 2 is OFF 360 Mb/s using RVCO0 or R VCO1
Fig. 18 Frequency Setting Resistor Values & Temperature Compensation
Temperature Compensation Procedure In order to correctly set the VCO frequency so that the PLL will always re-acquire lock over the full temperature range, the following procedure should be used. The circuit should be powered on for at least one minute prior to starting this procedure. Monitor the loop filter voltage at the junction of the loop filter resistor and 10 nF loop filter capacitor (LOOP FILTER TEST POINT). Using the appropriate network shown above, the VCO frequency is set by first tuning the potentiometer so that the PLL loses lock at the low end (lowest loop filter voltage). The loop filter voltage is then slowly increased by adjusting the the potentiometer to determine the error free low limit of the capture range. Error free operation is determined by using a suitable CRC or EDH measurement method to obtain a stable signal with no errors. Record the loop filter voltage at this point as VCL . Now adjust the potentiometer so that the loop filter voltage is 250 mV above VCL .
11
520 - 28 - 11
Application Note - PCB Layout Special attention must be paid to component layout when designing high performance serial digital receivers. For background information on high speed circuit and layout design concepts, refer to Document No. 521-32-00, "Optimizing Circuit and Layout Design of the GS90005A/15A". A recommended PCB layout can be found in the Gennum Application Note "EB9010B Deserializer Evaluation Board." The use of a star grounding technique is required for the loop filter components of the GS9005A/15A. Controlled impedance PCB traces should be used for the differential clock and data interconnection between the GS9005A and the GS9000B or GS9000S. These differential traces must not pass over any ground plane discontinuities. A slot antenna is formed when a microstrip trace runs across a break in the ground plane. The series resistors at the parallel data output of the GS9000B or GS9000S are used to slow down the fast rise/fall time of the GS9000B or GS9000S outputs. These resistors should be placed as close as possible to the GS9000B or GS9000S output pins to minimize radiation from these pins.
SSI VCC +5V + DVCC +5V + VCC 0.1 GND DGND ECL DATA INPUT VCC 0.1 INPUT 75 47p 5 6 7 DDI DDI 390
VSS
SWF 0.1 VCC 100 3.3k 100
10 + 0.1
10
10
VCC 0.1 DGND 4
SWF
DGND
100 INPUT SELECTION DGND SYNC WARNING FLAG HSYNC OUTPUT PARALLEL DATA BIT 9 PARALLEL DATA BIT 8 25 24 23 22 21 20 100 100 100 100 100 100 100 DVCC PARALLEL DATA BIT 7 PARALLEL DATA BIT 6 PARALLEL DATA BIT 5 PARALLEL DATA BIT 4 PARALLEL DATA BIT 3 PARALLEL DATA BIT 2 PARALLEL DATA BIT 1 PARALLEL DATA BIT 0 PARALLEL CLOCK OUT SYNC CORRECTION ENABLE 0.1 DGND
3
VSS
2
HSYNC
1
PD9
28 27 26
PD8 PDO VSS
4
VEE1 VCC1
3
AGC
2
A/D
1
SSI
28 27 26
VEE2 VCC4
390 25 24 23 22 100 100 100 100 390 390 5 6 7 8 9 10 11 SDI SDI SCI SCI SS1 SS0
SDO SDO SCO
PD7 PD6 (4) PD5 PD4 PD3 PD2
PCLK
VCC2 8 SDI 9 SDI
LOOP
GS9005A
SCO
EYEOUT
RVCO0
RVCO1
RVCO2
RVCO3
VDD
VDD
75 5.6p
(1)
VCC3
12 13 14 15 16 17 18
VCC
DVCC
12 13 14 15 16
SCE
47p
17
22n
113
(2)
910
0.1F
0.1 DGND
100
100
10n
1.2k
VCC 1.2k
DVCC
0.1
(3)
50k VCC
68k
22n
STAR ROUTED + +
120
DGND
GS9010A
6.8 6.8 1 2 3 4
3.3n 5
(2)
P/N OUT INCOMP LF /2 VCC SWF
STDT VCC CD HSYNC GND OSC DLY FVCAP
16 15 14 13 12 11 10 9
0.1
VCC
6 VCC 7 8
VDD
SST
SWC
10 /2 11 VEE3
V SS1 21 CC SS0 20 CD 19
GS9000B or GS9000S
PD1 19
18
100k
82n 0.68
(2)
STANDARD TRUTH TABLE /2 0 0 P/N 0 1 0 1 STANDARD 4:2:2 - 270 4:2:2 - 360 4sc - NTSC 4sc - PAL
All resistors in ohms, all capacitor in microfarads, all inductors in henries unless otherwise stated.
0.1
SWF
VCC
180n
1 1
(1) Typical value for input return loss matching (2) To reduce board space, the two anti-series 6.8F capacitors (connected across pins 2 and 3 of the GS9010A) may be replaced with a 0.33 F capacitor and (b) the GS9005A /15A Loop Filter Capacitor is 10nF. (3) Remove this potentiometer if P/N function is not required, and ground pin 16 of the GS9010A. (4) The GS9000B will operate to a maximum frequency of 370 Mbps. The GS9000S will operate to a maximum frequency of 300 Mbps. 1.0 F non-polarized capacitor provided that: DOCUMENT IDENTIFICATION
PRODUCT PROPOSAL This data has been compiled for market investigation purposes only, and does not constitute an offer for sale. ADVANCE INFORMATION NOTE This product is in development phase and specifications are subject to change without notice. Gennum reserves the right to remove the product at any time. Listing the product does not constitute an offer for sale. PRELIMINARY The product is in a preproduction phase and specifications are subject to change without notice. DATA SHEET The product is in production. Gennum reserves the right to make changes at any time to improve reliability, function or design, in order to provide the best product possible.
(a) the 0.68 F capacitor connected to the OSC pin (11) of the GS9010A is replaced with a
Fig. 20 Typical Application Circuit
REVISION NOTES Changes to Figures 16, 17 and 20.
Gennum Corporation assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement. (c) Copyright March 1991 Gennum Corporation. All rights reserved. Printed in Canada.
520 - 28 - 11
12

▲Up To Search▲

Price & Availability of GS9005A

	To Download GS9005A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .