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PRELIMINARY TECHNICAL DATA
a
FEATURES Fast Throughput Rate: 1.5 MSPS Specified for VDD of 2.7 V to 5.25 V Low Power: 8 mW max at 1.5 MSPS with 3V Supplies 16 mW max at 1.5 MSPS with 5V Supplies 8 Analog Input Channels with a Sequencer Software Configurable Analog Inputs: 8-Channel Single Ended Inputs 4-Channel Fully Differential Inputs 4-Channel Pseudo Differential Inputs 7-Channel Pseudo Differential Inputs Accurate On-chip 2.5 V Reference Wide Input Bandwidth: 70dB SNR at 50kHz Input Frequency No Pipeline Delays High Speed Parallel Interface - Word/Byte Modes Full Shutdown Mode: 1A max 32-Pin LFCSP Package
8-Channel, 1.5 MSPS, 12- & 10-Bit Parallel ADCs with a Sequencer AD7938/AD7939
FUNCTIONAL BLOCK DIAGRAM
VDD VREFIN/ VREFOUT VIN0 I/P MUX VIN7 AGND
AD7938/AD7939
2.5 V VREF T/H 12-/10-BIT SAR ADC AND CONTROL CLKIN CONVST BUSY
SEQUENCER
PARALLEL INTERFACE/CONTROL REGISTER
VDRIVE
DB0
DB9/ CS DB11
RD WR W/B
DGND
GENERAL DESCRIPTION
The AD7938/AD7939 are 12- & 10-bit, high speed, low power, successive approximation (SAR) ADCs. The parts operate from a single 2.7 V to 5.25 V power supply and feature throughput rates up to 1.5 MSPS. The parts contain a low noise, wide bandwidth, differential track/hold amplifier that can handle input frequencies up to 20MHz. The AD7938/AD7939 feature 8 analog input channels with a channel sequencer to allow a pre-programmed selection of channels to be converted sequentially. These parts can operate with either Single-ended, Fully Differential or Pseudo Differential analog inputs. The analog input configuration is chosen by setting the relevant bits in the on-chip Control Register. The conversion process and data acquisition are controlled using standard control inputs allowing easy interfacing to Microprocessors and Dsps. The input signal is sampled on the falling edge of CONVST and the conversion is also initiated at this point. The AD7938/AD7939 has an accurate on-chip 2.5 V reference that can be used as the reference source for the analog to digital conversion. Alternatively, this pin can be overdriven to provide an external reference in the range 100mV to 3.5 V.
These parts use advanced design techniques to achieve very low power dissipation at high throughput rates. They also feature flexible power management options. An on-chip Control register allows the user to set up different operating conditions including analog input range and configuration, output coding, power management and channel sequencing.
PRODUCT HIGHLIGHTS
1. High Throughput with Low Power Consumption The AD7938/AD7939 offer 1.5 MSPS throughput with 8mW power consumption at VDD = 3V. 2. Eight Analog Inputs with a Channel Sequencer. A sequence of input channels can be selected, through which the AD7938/AD7939 will continuously cycle and convert on. 3. Accurate on-chip 2.5 V reference. 4. Software Configurable Analog Inputs Single-Ended, Pseudo Differential or Fully Differential analog inputs that are software selectable. 5. Single-supply Operation with VDRIVE Function. The AD7938/AD7939 operates from a single 2.7 V to 5.25 V supply. The VDRIVE function allows the parallel interface to connect directly to either 3V or 5 V proces sor systems independent of VDD. 6. No Pipeline Delay The parts feature a standard successive-approximation ADC with accurate control of the sampling instant via a CONVST input and once off conversion control.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106,U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2003
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PRELIMINARY TECHNICAL DATA
AD7938-SPECIFICATIONS1
Parameter DYNAMIC PERFORMANCE Signal to Noise + Distortion 2 (SINAD) Signal to Noise Ratio (SNR)2 Total Harmonic Distortion (THD) 2 Peak Harmonic or Spurious Noise (SFDR) 2 Intermodulation Distortion (IMD) 2 Second Order Terms Third Order Terms Aperture Delay Aperture Jitter Channel-to-Channel Isolation 2 Full Power Bandwidth DC ACCURACY Resolution Integral Nonlinearity 2 Differential Nonlinearity 2 Total Unadjusted Error 0V to VREF IN Input Range3 Offset Error Offset Error Match Gain Error Gain Error Match 0V to 2 x VREF IN Input Range4 Positive Gain Error Positive Gain Error Match Zero Code Error Zero Code Error Match Negative Gain Error Negative Gain Error Match ANALOG INPUT Input Voltage Ranges 70 70 -75 -75
( VDD = VDRIVE=2.7 V to 5.25V, VREFIN/VREFOUT = 2.5V unless otherwise noted, FCLKIN = 20MHz, FSAMPLE = 1.5 MSPS; TA = TMIN to TMAX, unless otherwise noted.)
Units dB min dB min dB max dB max Test Conditions/Comments F IN =50kHz Sine Wave
BVersion1
-80dB typ -82dB typ fa = 40.1kHz, fb = 51.5kHz
-85 -85 10 50 -82 20 2.5 12 1 0.95 TBD 3 0.5 2 0.6
dB typ dB typ ns typ ps typ dB typ MHz typ MHz typ Bits LSB max LSB max LSB max LSB LSB LSB LSB max max max max
@ 3 dB @ 0.1 dB
Guaranteed No Missed Codes to 12 Bits. Straight Binary Output Coding
-VREF IN to +VREF IN Biased about VREF with Twos Complement Output Coding 2 0.6 3 1 1 0.5 0 to VREF 0 to 2xVREF 1 20 2.5 5 1 2.49/2.51 15 10 0.7xVDRIVE 0.3xVDRIVE 1 10 LSB LSB LSB LSB LSB LSB V V A max pF typ V A max Vmin/max ppm/C typ V min V max A max pF max 1% Specified Performance max max max max max max RANGE bit in the Control register set to 1. RANGE bit in the Control register set to 0. VDD/VDRIVE = 4.75 V to 5.25 V for 0-2VREF range
DC Leakage Current Input Capacitance REFERENCE INPUT/OUTPUT V REFIN Input Voltage DC Leakage Current VREFOUT Output Voltage V REFOUT Tempco V REF Output Impedance LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN6 LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL Floating-State Leakage Current Floating-State Output Capacitance 6 Output Coding
Typically 10 nA, VIN = 0 V or VDRIVE
VDRIVE -0.2 V min 0.4 V max 10 A max 10 pF max Straight (Natural) Binary 2s Complement -2-
ISOURCE = 200 A; VDD = 2.7 V to 5.25 V I SINK =200A CODING bit in the control register set to 1. CODING bit in the control register set to 0. REV. PrD
AD7938-SPECIFICATIONS1
Parameter CONVERSION RATE Conversion Time Track/Hold Acquisition Time Throughput Rate POWER REQUIREMENTS V DD V DRIVE I DD Normal Mode(Static) Normal Mode (Operational) Auto StandBy Mode Auto Shutdown Mode Full Shut-Down Mode Power Dissipation Normal Mode (Operational) Auto Standby-Mode (Static) Auto Shutdown-Mode (Static) Full Shutdown-Mode 12
PRELIMINARY TECHNICAL DATA
B Version1 Units CLKIN cycles (max) ns max ns max MSPS max V min/max V min/max mA typ mA max mA max mA typ A max mA typ A max A max mW max mW max W max W max W max W max W max W max Digital VDD = VDD = VDD = I/Ps = 0V or VDRIVE. 2.7V to 5.25V. 4.75V to 5.25V. 2.7V to 3.6V. Test Conditions/Comments
300 325 1.5 2.7/5.25 2.7/5.25 0.5 3.2 2.6 1.55 90 1 1 1 16 8 450 270 5 3 5 3
Sine Wave Input Full-Scale Step Input Conversion Time + Acquisition Time
(Static) (Static) SCLK On or Off. VDD VDD VDD VDD VDD VDD VDD VDD = = = = = = = = 5V. 3V. 5V. 3V. 5V. 3V. 5V. 3V.
NOTES 1 Temperature ranges as follows: B Versions: -40C to +85C. 2 See Terminology Section. 3 Bit 9 in the Control register set to 1 4 Bit 9 in the Control register set to 0 5 This device is operational with an external reference in the range 0.1 V to 3.5 V. 6 Sample tested @ +25C to ensure compliance. Specifications subject to change without notice.
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PRELIMINARY TECHNICAL DATA
AD7939-SPECIFICATIONS1
Parameter DYNAMIC PERFORMANCE Signal to Noise + Distortion 2 (SINAD) Signal to Noise Ratio (SNR)2 Total Harmonic Distortion (THD) 2 Peak Harmonic or Spurious Noise2 (SFDR) Intermodulation Distortion (IMD)2 Second Order Terms Third Order Terms Aperture Delay Aperture Jitter Channel-to-Channel Isolation 2 Full Power Bandwidth DC ACCURACY Resolution Integral Nonlinearity 2 Differential Nonlinearity Total Unadjusted Error 0V to VREF IN Input Range3 Offset Error Offset Error Match Gain Error Gain Error Match 0V to 2 x VREF IN Input Range4 Positive Gain Error Positive Gain Error Match Zero Code Error Zero Code Error Match Negative Gain Error Negative Gain Error Match ANALOG INPUT Input Voltage Ranges B Version1 60 60 -73 -73
( VDD = VDRIVE=2.7 V to 5.25V, VREFIN/VREFOUT = 2.5V unless otherwise noted, FCLKIN = 20MHz, FSAMPLE = 1.5MSPS; TA = TMIN to TMAX, unless otherwise noted.)
Units dB min dB min dB max dB max fa = 40.1kHz, fb = 51.5kHz Test Conditions/Comments F IN =50kHz Sine Wave
-75 -75 10 50 -82 20 2.5 10 0.5 0.5 TBD 3 0.5 2 0.6
dB typ dB typ ns typ ps typ dB typ MHz typ MHz typ Bits LSB max LSB max LSB max LSB LSB LSB LSB max max max max
@ 3 dB @ 0.1 dB
Guaranteed No Missed Codes to 10 Bits. Straight Binary Output Coding
-VREF IN to +VREF IN Biased about VREF with Twos Complement Output CodingOffset 2 0.6 3 1 1 0.5 0 to VREF 0 to 2xVREF 1 20 2.5 5 1 36 2.49/2.51 15 10 0.7xVDRIVE 0.3xVDRIVE 1 10 LSB LSB LSB LSB LSB LSB V V A max pF typ V A max k Vmin/max ppm/C typ V min V max A max pF max 1% Specified Performance max max max max max max RANGE bit in the Control register set to 1. RANGE bit in the Control register set to 0. VDD/VDRIVE = 4.75 V to 5.25 V for 0-2VREF range
DC Leakage Current Input Capacitance REFERENCE INPUT/OUTPUT V REFIN Input Voltage DC Leakage Current V REFIN Input Impedance VREFOUT Output Voltage V REFOUT Tempco VREF Output Impedance LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN6 LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL Floating-State Leakage Current Floating-State Output Capacitance 6 Output Coding
Typically 10 nA, VIN = 0 V or VDRIVE
VDRIVE -0.2 V min 0.4 V max 10 A max 10 pF max Straight (Natural) Binary 2s Complement -4-
ISOURCE = 200 A; VDD = 2.7 V to 5.25 V I SINK =200A CODING bit in the control register set to 1. CODING bit in the control register set to 0. REV. PrD
PRELIMINARY TECHNICAL DATA
AD7939-SPECIFICATIONS1
Parameter CONVERSION RATE Conversion Time Track/Hold Acquisition Time Throughput Rate POWER REQUIREMENTS VDD V DRIVE I DD Normal Mode(Static) Normal Mode (Operational) Auto StandBy Mode Auto Shutdown Mode Full Shut-Down Mode Power Dissipation Normal Mode (Operational) Auto Standby-Mode (Static) Auto Shutdown-Mode (Static) Full Shutdown-Mode B Version1 10 300 325 1.5 2.7/5.25 2.7/5.25 0.5 3.2 2.6 1.55 90 1 1 1 16 8 450 270 5 3 5 3 Units CLKIN cycles (max) ns max ns max MSPS max V min/max V min/max mA typ mA max mA max mA typ A max mA typ A max A max mW max mW max W max W max W max W max W max W max Digital VDD = VDD = VDD = I/Ps = 0V or VDRIVE. 2.7V to 5.25V. 4.75V to 5.25V. 2.7V to 3.6V. Test Conditions/Comments
Sine Wave Input Full-Scale Step Input Conversion Time + Acquisition Time
(Static) (Static) SCLK On or Off. VDD VDD VDD VDD VDD VDD VDD VDD = = = = = = = = 5V. 3V. 5V. 3V. 5V. 3V. 5V. 3V.
NOTES 1 Temperature ranges as follows: B Versions: -40C to +85C. 2 See Terminology Section 3 Bit 9 in the Control register set to 1 4 Bit 9 in the Control register set to 0 5 This device is operational with an external reference in the range 0.1 V to 3.5 V. 6 Sample tested @ +25C to ensure compliance. Specifications subject to change without notice.
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PRELIMINARY TECHNICAL DATA
AD7938/AD7939
TIMING SPECIFICATIONS1,2,3
Parameter f CLKIN t quiet t convert t1 t2 t3 t4 t5 t6 t7 t8 t9 t 10 t 11 5 t 12 6 t 13 t 14 t 15 t 16 t 17
4
( VDD = VDRIVE=2.7 V to 5.25V, VREFIN/VREFOUT = 2.5V unless otherwise noted, FCLKIN = 20MHz, FSAMPLE = 1.5MSPS; TA = TMIN to TMAX, unless otherwise noted.)
Units kHz min MHz max ns min ns max ns min ns min ns max ns min ns min ns min ns min ns min ns max ns min ns max ns min ns max ns min ns min ns min/max ns min ns max Description
Limit at TMIN, TMAX AD7938 AD7939 10 20 100 TBD 100 0 0 55 10 5 1/2 t CLKIN 0 0 55 50 5 40 15 5 60 0 5 10 20 100 TBD 100 0 0 55 10 5 1/2 t CLKIN 0 0 55 50 5 40 15 5 60 0 5
Minimum time between conversions Conversion Time CONVST pulsewidth CS to WR setup time CS to WR hold time WR Pulse Width Data Setup time before WR Data Hold after WR New data valid before falling edge of BUSY CS to RD setup time CS to RD hold time RD Pulse Width Data access time after RD Bus relinquish time after RD Bus relinquish time after RD HBEN to RD setup time HBEN to RD hold time Minimum time between Reads HBEN to WR setup time HBEN to RD setup time
NOTES 1 Sample tested at +25C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD ) and timed from a voltage level of 1.6 Volts. 2 See Figure 1, Figure 20 and Figure 21. 3 All timing specifications given above are with a 25pF load capacitance. 4 Mark/Space ratio for the SCLK input is 40/60 to 60/40. 5 The time required for the output to cross 0.4 V or 0.7 x VDRIVE V. 6 t 12 is derived form the measured time taken by the data outputs to change 0.5 V. The measured number is then extrapolated back to remove the effects of charging or discharging the 25 pF capacitor. This means that the time, t 12 quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the bus loading. Specifications subject to change without notice.
t1 CONVST BUSY CS t2 WR RD t5 DB0-DB11 DATA t4 t8 t6 t11 t10 t12 DATA t9 t3 t7
OLD DATA
NEW DATA
Figure 1. AD7938/AD7939 Parallel Interface
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PRELIMINARY TECHNICAL DATA AD7938/AD7939
ABSOLUTE MAXIMUM RATINGS1
(TA = +25C unless otherwise noted)
V DD to AGND/DGND . . . . . . . . . . . . . . . . . -0.3 V to 7 V V DRIVE to AGND/DGND . . . . . . . . . . . . . . . -0.3 V to 7 V Analog Input Voltage to AGND . -0.3 V to VDD + 0.3 V Digital Input Voltage to DGND . . . . . . . . . . -0.3 V to 7 V VDRIVE to VDD . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to VDD + 0.3 V Digital Output Voltage to AGND -0.3 V to VDD + 0.3 V REFIN to AGND . . . . . . . . . ........-0.3 V to VDD + 0.3 V Input Current to Any Pin Except Supplies2 . . . . 10 mA Operating Temperature Range Commercial (B Version) . . . . . . . . . . . -40C to +85C Storage Temperature Range . . . . . . . -65C to +150C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . +150C JA Thermal Impedance . . . . . . . . . . . 108.2C/W (LFCSP) JC Thermal Impedance . . . . . . . . . . . 32.71C/W (LFCSP) Lead Temperature, Soldering Vapor Phase (60 secs) . . . . . . . . . . . . . . . . . . . +215C Infared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . +220C E S D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 kV
NOTES 1 Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Transient currents of up to 100 mA will not cause SCR latch up.
ORDERING GUIDE
Model AD7938 AD7939 EVAL-ADxxxxCB 2 EVAL-CONTROL BRD2 3
Range -40C to +85C -40C to +85C Evaluation Board Controller Board
Linearity Error (LSB)1 1 1
Package Option CP-32 CP-32
Package Descriptions LFCSP LFCSP
NOTES 1 Linearity error here refers to integral linearity error. 2 This can be used as a stand-alone evaluation board or in conjunction with the Evaluation Board Controller for evaluation/demonstration purposes. 3 Evaluation Board Controller. This board is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators. The following needs to be ordered to obtain a complete evaluation kit: the ADC Evaluation Board (EVALADxxxxCB), the EVAL-CONTROL BRD2 and a 12 V ac transformer. See the ADxxxx evaluation board technical note for more details.
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7938/AD7939 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
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AD7938/AD7939
PRELIMINARY TECHNICAL DATA
PIN CONFIGURATION LFCSP
VDD
W/B
30 VIN7
26 VIN3
D0
1
PIN 1 IDENTIFIER
32
28 VIN5
25 VIN2
29 VIN6
31
27 VIN4
24 VIN1 23 VIN0 VREFIN/OUT AGND +5
D1 2 D2 3
D3 4 D4 5 D5 6 D6 7
AD7938/AD7939 TOP VIEW (Not to Scale)
22 21 20
19 4, 18 17 94 CONVST
D7 8
D8/HBEN 11
D10 13
PIN FUNCTION DESCRIPTION
Pin no. 1-8
Pin Mnemonic Function DB0 to DB7 Data Bits 0 to 7. Three state parallel digital I/O pins that provide the conversion result and also allow the Control and Shadow registers to be programmed. These pins are controlled by CS, RD and WR. The logic high voltage level for these pins is determined by the VDRIVE input. V DRIVE Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the parallel interface of the AD7938/AD7939 will operate. DGND Digital Ground. This is the ground reference point for all digital circuitry on the AD7938/ AD7939. The DGND and AGND voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis. DB8/HBEN Data Bit 8/High Byte Enable. When W/B is high, this pin acts as Data Bit 8, a three state I/O pin that is controlled by CS, RD and WR. When W/B is low, this pin acts as the high byte enable pin. When HBEN is low, the low byte of data being written to or read from the AD7938/AD7939 is on DB0 to DB7. When reading from the AD7939 the two LSBs in the low byte are zeros, followed by 6 bits of conversion data. When HBEN is high, the top 4 bits of the data being written to or read from the AD7938/AD7939 are on DB0 to DB3. When reading from the device, DB4 to DB5/6 of the high byte will contain the ID of the channel for which the conversion result corresponds. DB9 to DB11 Data Bits 9 to 11. Three state parallel digital I/O pins that provide the conversion result and also allow the status and sequencer registers to be programmed. These pins are controlled by CS, RD and WR. The logic high voltage level for these pins is determined by the VDRIVE input. DB10 and DB11 are only used as inputs for the AD7939 10-bit ADC. BUSY Busy Output. Logic output indicating the status of the conversion. The BUSY output goes high following the falling edge of CONVST and stays high for the duration of the conversion. Once the conversion is complete and the result is available in the output register, the BUSY output will go low. The track/hold returns to track mode just prior to the falling edge of BUSY and the acquisition time for the part begins when BUSY goes low.
9 10
11
12-14
15
VDRIVE
BUSY 15
9
CLKIN 16
DGND 10
D9 12
D11 14
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PRELIMINARY TECHNICAL DATA AD7938/AD7939
PIN FUNCTION DESCRIPTION
Pin no. 16
Pin Mnemonic Function CLKIN Master Clock Input. The clock source for the conversion process is applied to this pin. Conversion time for the AD7938 takes 12 clock cycles while conversion time for the AD7939 takes 10 clock cycles. The frequency of the master clock input therefore determines the conversion time and achievable throughput rate. Conversion Start Input. Following powerdown, when operating in Auto-shutdown or Auto STBY modes, a rising edge on CONVST is used to power up the device. A falling edge on CONVST is used to initiate a conversion. The track/hold goes from track to hold mode on the falling edge of CONVST and the conversion process is initiated at this point. Write Input. Active low logic input used in conjunction with CS to write data to the internal registers. Read Input. Active low logic input used in conjunction with CS to access the conversion result. The conversion result is placed on the data bus following the falling edge of both CS and RD. Chip Select. Active low logic input used in conjunction with RD and WR to Read conversion data or to Write data to the internal registers. When reading, data is placed on to the data bus following the falling edge of both CS and RD. Analog Ground. This is the ground reference point for all analog circuitry on the AD7938/AD7939. All analog input signals and any external reference signal should be referred to this AGND voltage. The AGND and DGND voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis. Reference Input/Output. This pin is connected to the internal reference and is the reference source for the ADC. The nominal internal reference voltage is 2.5 V and this appears at this pin. This pin can be overdriven by an external reference. The input voltage range for the external reference is 0.1 V to 3.5 V. Analog Input 0 to Analog Input 7. Eight analog input channels that are multiplexed into the on-chip track/hold. The analog inputs can be programmed to be eight single ended inputs, four fully differential pairs, four pseudo differential pairs or seven pseudo differential inputs by setting the MODE bits in the Control register appropriately (see Table III). The analog input channel to be converted can either be selected by writing to the Address bits (ADD2 to ADD0) in the control register prior to the conversion, or the on-chip sequencer can be used. The SEQ and SHADOW bits in conjunction with the address bits in the Control register allow the Shadow Register to be programmed. The input range for all input channels can either be 0V to VREF or 0V to 2 x VREF and the coding can be binary or two's complement, depending on the states of the RANGE and CODING bits in the Control register. Any unsed input channels should be connected to AGND to avoid noise pickup. Power Supply Input. The VDD range for the AD7938/AD7939 is from +2.7V to +5.25V. The supply should be decoupled to AGND with a 0.1F capacitor and a 10F tantalum capacitor. Word/Byte Input. When this input is logic high, data is transferred to and from the AD7938/AD7939 in 12/10-bit words on pins DB0 to DB11/9. When this pin is logic low, byte transfer mode is enabled. Data and the channel ID is transferred on pins DB0 to DB7 and pin DB8/HBEN assumes its HBEN functionality.
17
CONVST
18 19
WR RD
20
CS
21
AGND
22
VREFIN/VREFOUT
23-30
VIN0 - VIN7
31
V DD W/B
32
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AD7938/AD7939
TERMINOLOGY Integral Nonlinearity
PRELIMINARY TECHNICAL DATA
tion, but not the converter's linearity. Power supply rejection is the maximum change in full-scale transition point due to a change in power-supply voltage from the nominal value. See Typical PerformancePlots.
Track/Hold Acquisition Time
This is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale, a point 1 LSB below the first code transition, and full scale, a point 1 LSB above the last code transition.
Differential Nonlinearity
This is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC.
Offset Error
The track/hold amplifier returns into track mode and the end of conversion. Track/Hold acquisition time is the time required for the output of the track/hold amplifier to reach its final value, within 1/2 LSB, after the end of conversion.
Signal to (Noise + Distortion) Ratio
This is the deviation of the first code transition (00 . . . 000) to (00 . . . 001) from the ideal, i.e AGND + 1 LSB
Offset Error Match
This is the difference in offset error between any two channels. Gain Error This is the deviation of the last code transition (111 . . . 110) to (111 . . . 111) from the ideal (i.e., VREFIN - 1 LSB) after the offset error has been adjusted out. Gain Error Match This is the difference in Gain error between any two channels. Zero Code Error This applies when using the 2's complement output coding option, in particular to the 2 x VREFIN input range with -VREFIN to +VREFIN biased about the VREFIN point. It is the deviation of the mid scale transition (all 0s to all 1s) from the ideal VIN voltage, i.e. VREFIN - 1 LSB. Zero Code Error Match This is the difference in Zero Code Error between any two channels. Positive Gain Error This applies when using the 2's complement output coding option, in particular to the 2 x VREFIN input range with -VREFIN to +VREFIN biased about the VREFIN point. It is the deviation of the last code transition (011. . .110) to (011 . . . 111) from the ideal (i.e., +VREFIN - 1 LSB) after the Zero Code Error has been adjusted out. Positive Gain Error Match This is the difference in Positive Gain Error between any two channels. Negative Gain Error This applies when using the 2's complement output coding option, in particular to the 2 x VREFIN input range with -VREFIN to +VREFIN biased about the VREFIN point. It is the deviation of the first code transition (100 . . . 000) to (100 . . . 001) from the ideal (i.e., -REF IN + 1 LSB) after the Zero Code Error has been adjusted out. Negative Gain Error Match This is the difference in Negative Gain Error between any two channels.
Channel-to-Channel Isolation
This is the measured ratio of signal to (noise + distortion) at the output of the A/D converter. The signal is the rms amplitude of the fundamental. Noise is the sum of all nonfundamental signals up to half the sampling frequency (fS/2), excluding dc. The ratio is dependent on the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. The theoretical signal to (noise + distortion) ratio for an ideal N-bit converter with a sine wave input is given by: Signal to (Noise + Distortion) = (6.02 N + 1.76) dB Thus for a 12-bit converter, this is 74 dB and for a 10-bit converter, this is 61.96dB.
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the rms sum of harmonics to the fundamental. For the AD7938/ AD7939, it is defined as:
THD (dB ) = 20 log V2 +V3 +V
2 2 2 4
+V5 +V
2
2 6
V1
where V1 is the rms amplitude of the fundamental and V2, V3, V4, V5 and V6 are the rms amplitudes of the second through the sixth harmonics.
Peak Harmonic or Spurious Noise
Peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the ADC output spectrum (up to fS/2 and excluding dc) to the rms value of the fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for ADCs where the harmonics are buried in the noise floor, it will be a noise peak
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities will create distortion products at sum and difference frequencies of mfa nfb where m, n = 0, 1, 2, 3, etc. Intermodulation distortion terms are those for which neither m nor n are equal to zero. For example, the second order terms include (fa + fb) and (fa - fb), while the third order terms include (2fa + fb), (2fa - fb), (fa + 2fb) and (fa - 2fb).
The AD7938/AD7939 is tested using the CCIF standard where two input frequencies near the top end of the input bandwidth are used. In this case, the second order terms are usually distanced in frequency from the original sine waves while the third order terms are usually at a frequency close to the input frequencies. As a result, the second and third order terms are specified separately. The calculation of the The figure is given worse case across all 8 channels for the intermodulation distortion is as per the THD specification AD7938/AD7939. where it is the ratio of the rms sum of the individual distorPSR (Power Supply Rejection) tion products to the rms amplitude of the sum of the Varations in power supply will affect the full scale transifundamentals expressed in dBs. REV. PrD -10- Channel-to-Channel Isolation is a measure of the level of crosstalk between channels. It is measured by applying a fullscale 390 kHz sine wave signal to all 7 nonselected input channels and determining how much that signal is attenuated in the selected channel with a 50 kHz signal.
PRELIMINARY TECHNICAL DATA AD7938/AD7939
TYPICAL
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PERFORMANCE CHARACTERISTICS
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AD7938 Performance Curves
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TPC1 PSRR versus Supply ripple Frequencywith supply decoupling
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TPC9. Change in INL vs VREF for VDD = 5V
TPC5. AD7938 SINAD vs Analog Input Frequency for various Supply Voltages
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TPC2 PSRR versus Supply ripple Frequencywithout supply decoupling
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TPC10. Change in DNL vs VREF for VDD = 5V
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TPC6. FFT @ VDD = 5V
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TPC3 Internal VREF Error vs Temperature
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TPC11. Change in ENOB vs VREF for VDD = 5V
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TPC7. Typical DNL @ VDD = 5V
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TPC4 VREFout vs Rsource
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TPC12. Offset vs VREF
TPC8. Typical INL @ VDD = 5V
REV. PrD
-11-
AD7938/AD7939
0 0
PRELIMINARY TECHNICAL DATA
AD7939 Performance Curves
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TPC13. Histogram of codes @ VDD = 5v
ON-CHIP REGISTERS
TPC13. FFT @ VDD = 5V
TPC 14. Typical DNL @ VDD = 5V
TPC 15. Typcial INL @ VDD = 5V
The AD7938/AD7939 has two on-chip registers that are necessary for the operation of the device. These are the Control register, used to set up different conditions and the Shadow register, used to program the analog input channels to be converted on.
CONTROL REGISTER
The Control Register on the AD7938/AD7939 is a 12-bit, write-only register. Data is written to this register using the CS and WR pins. The Control Register is shown below and the functions of the bits are described in Table I.
MSB D11 PM1 D10 PM0 D9 CODING D8 REF D7 ADD2 D6 ADD1 D5 ADD0 D4 MODE1 D3 MODE0 D2 SHDW D1 SEQ LSB D0 RANGE
Table I. Control Register Bit Function Description
Bit 11, 10
Mnemonic PM1 PM0 CODING REF
Comment Power Management Bits. These two bits are used to select the power mode of operation. The user can choose between either normal mode or various power down modes of operation as shown in Table II. This bit selects the output coding of the conversion result. If this bit is set to 0, the output coding will be 2s complement. If this bit is set to 1, the output coding will be straight binary. This bit selects whether the internal or an external reference is used to perform the conversion. If this bit is logic 0, the internal reference is selected and if it is 1, an external reference should be applied (see the Reference Section). These three address bits are used to either select which analog input channel is to be converted on in the next conversion if the sequencer is not being used, or to select the final channel in a consecutive sequence when the sequencer is being used as described in Table IV. The selected input channel is decoded as shown in Table III. The two Mode pins select the type of analog input on the eight VIN pins. The AD7938/AD7939 can have either 8 Single Ended inputs, 4 Fully Differential inputs, 4 Pseudo Differential inputs or 7 Pseudo Differential inputs. See Table III. The SHADOW bit in the control register is used in conjunction with the SEQ bit to control the sequencer function and access the SHADOW register. See Table IV. The SEQ bit in the control register is used in conjunction with the SHDW bit to control the sequencer function and access the SHADOW register. See Table IV. This bit selects the analog input range of the AD7938/AD7939. If it is set to 0 then the analog input range will extend from 0V to VREFIN. If it is set to 1 then the analog input range will extend from 0V to 2xVREFIN. When this range is selected, AVDD must be 4.75 V to 5.25 V.
9 8
7, 6, 5
ADD2, ADD1, ADD0 MODE1, MODE0 SHDW SEQ
4,3
2 1
0
RANGE
-12-
REV. PrD
PRELIMINARY TECHNICAL DATA AD7938/AD7939
Table II. Power Mode Selection using the Power Management Bits in the Control Register
PM1 PM2 1 1 0 0 1 0 1 0
Mode
Description
Normal Mode When operating in normal mode, all circuitry is fully powerered up at all times. Full Shutdown When the AD7938/AD7939 enters this mode, all circuitry is powered down. The information in the Control Register is retained. Auto Shutdown When operating in Auto Shutdown mode, the AD7938/AD7939 will enter Full Shutdown mode at the end of each conversion. In this mode, all circuitry is powered down. Auto Standby When the AD7938/AD7939 enter this mode, all circuitry is powered down excluding the internal reference. This mode is similar to Auto Shutdown and allows the part to power up in 1sec.
Table III. Analog Input Type Selection
MODE0=0, MODE1=0 MODE0=0, MODE1=1 MODE0=1, MODE1=0 MODE0=1, MODE1=1 8 Single-Ended I/P 4 Fully Differential 4 Pseudo Differential 7 Pseudo Differential Channels I/P Channels I/P Channels I/P Channels ADD2 ADD1 ADD0 VIN+ VINVIN+ VINVIN+ VINVIN+ VIN0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 VIN0 VIN1 VIN2 VIN3 VIN4 VIN5 VIN6 VIN7 AGND AGND AGND AGND AGND AGND AGND AGND VIN0 VIN1 VIN2 VIN3 VIN4 VIN5 VIN6 VIN7 VIN1 VIN0 VIN3 VIN2 VIN5 VIN4 VIN7 VIN6 VIN0 VIN1 VIN2 VIN3 VIN4 VIN5 VIN6 VIN7 VIN1 VIN0 VIN3 VIN2 VIN5 VIN4 VIN7 VIN6 VIN0 VIN1 VIN2 VIN3 VIN4 VIN5 VIN6 VIN7 VIN7 VIN7 VIN7 VIN7 VIN7 VIN7 VIN7 VIN7
Channel Address
SEQUENCER OPERATION The configuration of the SEQ and SHADOW bits in the control register allows the user to select a particular mode of operation of the sequencer function. Table IV outlines the four modes of operation of the Sequencer.
Table IV. Sequence Selection
SEQ SHDW Sequence Type 0 0 This configuration is selected when the sequence function is not used. The analog input channel selected on each individual conversion is determined by the contents of the channel address bits ADD2-ADD0 in each prior write operation. This mode of operation reflects the normal operation of a multi-channel ADC, without the Sequencer function being used, where each write to the AD7938/39 selects the next channel for conversion. This configuration selects the Shadow register for programming. The following write operation will load the data on DB0-DB11/9 to the Shadow Register. This will program the sequence of channels to be converted on continuously after each CONVST falling edge (see the Shadow register description and Table V). If the SEQ and SHADOW bits are set in this way then the sequence function will not be interrupted upon completion of the WRITE operation. This allows other bits in the Control Register to be altered between conversions while in a sequence without terminating the cycle. This configuration is used in conjunction with the Channel Address bits (ADD2 -ADD0) to program continuous conversions on a consecutive sequence of channels from Channel 0 through to a selected final channel as determined by the Channel Address bits in the Control Register.
SHADOW REGISTER
0
1
1
0
1
1
The Shadow Register on the AD7938/AD7939 is an 8-bit, write-only register. Data is loaded from DB0 to DB11 on the rising edge of WR. The 8 LSBs will be loaded into the Shadow register. The information is written into the Shadow Register provided the SEQ and SHADOW bits in the control register were set to 0 & 1 respectively in the previous write to the Control Register. Each bit represents an analog input from channel 0 through to channel 7. A sequence of channels may be selected through which the AD7938/AD7939 will cycle with each consecutive conversion after the write to the Shadow register. To select a sequence of channels, the associated channel bit must be set for each analog input. The AD7938/AD7939 will continuously cycle through the selected channels in ascending order, beginning with the lowest channel, until a write operation occurs with the SEQ and SHADOW bits configured in any way except 1,0 (see Table IV). The bit functions are outlined in Table V.
Table V. Shadow Register Bit Functions
VIN0
REV. PrD
VIN1
VIN2
VIN3
-13-
VIN4 VIN5
VIN6 VIN7
AD7938/AD7939
CIRCUIT INFORMATION
PRELIMINARY TECHNICAL DATA
disconnected once the conversion begins. The Control Logic and the charge redistribution DACs are used to add and subtract fixed amounts of charge from the sampling capacitor arrays to bring the comparator back into a balanced condition. When the comparator is rebalanced, the conversion is complete. The Control Logic generates the ADC's output code. The output impedances of the sources driving the VIN+ and the VIN- pins must be matched otherwise the two inputs will have different settling times, resulting in errors.
The AD7938/AD7939 are fast, 8 channel, 12-&10-bit, single supply, Analog to Digital converters. The parts can be operated from a either a 2.7 V to 3.6 V or a 4.75 V to 5.25 V power supply and feature throughput rates up to 1.5MSPS. The AD7938/AD7939 provide the user with an on-chip track/hold, an internal accurate reference, an analog to digital converter, and a parallel interface housed in a 32- lead LFCSP. The AD7938/AD7939 have eight analog input channels which can be configured to be 8 single ended inputs, 4 fully differential pairs, 4 pseudo differential pairs or 7 pseudo differential inputs. There is an on-chip user-programmable channel sequencer which allows the user to select a sequence of channels through which the ADC can cycle. The analog input range for the AD7938/AD7939 is 0 to VREF or 0 to 2 x VREF depending on the status of the RANGE bit in the Control register. For the 0 to 2 x VREF range the part must be operated from a 4.75 V to 5.25 V supply. The AD7938/AD7939 provides flexible power management options to allow the user to achieve the best power performance for a given throughput rate. These options are selected by programming the power management bits, PM1 and PM0, in the Control Register. CONVERTER OPERATION The AD7938/AD7939 is a successive approximation ADC based around two capacitive DACs. Figures 2 and 3 show simplified schematics of the ADC in Acquisition and Conversion phase respectively. The ADC comprises of Control Logic, a SAR and two capacitive DACs. Figure 2 shows the operation of the ADC in Differential/Pseudo Differential Mode. Single Ended mode operation is similar but VIN- is internally tied to AGND. In acquisition phase, SW3 is closed and SW1 and SW2 are in position A, the comparator is held in a balanced condition and the sampling capacitor arrays acquire the differential signal on the input.
CAPACITIVE DAC COMPARATOR
CAPACITIVE DAC COMPARATOR CONTROL LOGIC
B VIN+ V INA SW1 A SW2 B VREF
Cs SW3 Cs
CAPACITIVE DAC
Figure 3. ADC Conversion Phase
ADC TRANSFER FUNCTION
The output coding for the AD7938/AD7939 is either straight binary or two's complement, depending on the status of the CODING bit in the control register. The designed code transitions occur at successive LSB values (i.e. 1LSB, 2LSBs, etc.) and the LSB size is VREF/4096 for the AD7938 and VREF/1024 for the AD7939. The ideal transfer characteristics of the AD7938/AD7939 for both straight binary and twos complement output coding are shown in Figures 4 and 5 respectively.
111...111 111...110
ADC CODE
111...000 011...111
1LSB = VREF/4096 (AD7938) 1LSB = VREF/1024 (AD7939)
000...010 000...001 000...000 0V
1LSB +VREF-1LSB
B VIN+ V INA SW1 A SW2 B VREF
Cs SW3 Cs
CONTROL LOGIC
ANALOG INPUT
NOTE: VREF is either VREF or 2 X VREF
CAPACITIVE DAC
Figure 4. AD7938/AD7939 Ideal Transfer Characteristic with Straight Binary Output Coding
Figure 2. ADC Acquisition Phase
When the ADC starts a conversion (figure 3), SW3 will open and SW1 and SW2 will move to position B, causing the comparator to become unbalanced. Both inputs are
-14-
REV. PrD
PRELIMINARY TECHNICAL DATA AD7938/AD7939
ANALOG INPUT STRUCTURE
1LSB = 2xVREF/4096 (AD7938) 1LSB = 2xVREF/1024 (AD7939)
011...111 011...110
000...001 000...000 111...111
Figure 7 shows the equivalent circuit of the analog input structure of the AD7938/AD7939 in Differential/Pseudo Differential Mode. In Single Ended mode, VIN- is internally tied to AGND. The four diodes provide ESD protection for the analog inputs. Care must be taken to ensure that the analog input signals never exceed the supply rails by more than 300mV. This will cause these diodes to become forward biased and start conducting into the substrate. These diodes can conduct up to 10mA without causing irreversible damage to the part. The capacitors C1, in figure 7 are typically 4pF and can primarily be attributed to pin capacitance. The resistors are lumped components made up of the on-resistance of the switches. The value of these resistors is typically about 100 . The capacitors, C2, are the ADC's sampling capacitors and have a capacitance of 16pF typically. For ac applications, removing high frequency components from the analog input signal is recommended by the use of an RC low-pass filter on the relevant analog input pins. In applications where harmonic distortion and signal to noise ratio are critical, the analog input should be driven from a low impedance source. Large source impedances will significantly affect the ac performance of the ADC. This may necessitate the use of an input buffer amplifier. The choice of the opamp will be a function of the particular application.
VDD D VIN+ C1 D R1 C2
ADC CODE
100...010 100...001 100...000 -VREF + 1LSB 0LSB +VREF - 1LSB
ANALOG INPUT (VIN+- VIN-)
Figure 5. AD7938/AD7939 Ideal Transfer Characteristic with Twos Complement Output Coding
TYPICAL CONNECTION DIAGRAM
Figure 6 shows a typical connection diagram for the AD7938/AD7939. The AGND and DGND pins are connected together at the device for good noise supression. The VREFIN/VREFOUT pin is decoupled to AGND with a 0.1F capacitor to avoid noise pickup if the internal reference is used. Alternatively, VREFIN/VREFOUT can be connected to a external decoupled reference source. In both cases the analog input range can either be 0V to VREF (Range bit = 1) or 0V to 2 x VREF (Range bit = 0). The analog input configuration can be either 8 Single Ended inputs, 4 Differential Pairs, 4 Pseudo Differential Pairs or 7 Pseudo Differential Inputs (see Table III). The VDD pin is connected to either a 3V or 5V supply. The voltage applied to the VDRIVE input controls the voltage of the digital interface and here, it is connected to the same 3V supply of the microprocessor to allow a 3V logic interface (See the digital inputs section).
+3V/+5V SUPPLY
VDD D VINC1 D R1 C2
0.1F
10F
VDD VIN0 0 to VREF/ 0 to 2 x VREF VIN7 AGND DGND
AD7938/AD7939
W/B CLKIN CS RD WR BUSY CONVST DB0 C/P
Figure 7. Equivalent Analog Input Circuit. Conversion Phase - Switches Open Track Phase - Switches Closed
DB11/9 VREFIN/VREFOUT VDRIVE 0.1F 2.5V VREF 0.1F External Vref 0.47F Internal Vref 10F +3V SUPPLY
When no amplifier is used to drive the analog input, the source impedance should be limited to low values. The maximum source impedance will depend on the amount of Total Harmonic Distortion (THD) that can be tolerated. The THD will increase as the source impedance increases and performance will degrade. Figure 8 shows a graph of the THD versus analog input signal frequency for different source impedances for both VDD = 5 V and 3 V.
Figure 6. Typical Connection Diagram
REV. PrD
-15-
AD7938/AD7939
0
PRELIMINARY TECHNICAL DATA
connection diagram when operating the ADC in single ended mode.
+2.5 V R +1.25V 0V R V IN 3R R 0V
0
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TITLE
-1.25 V
VIN0
AD7938/ AD7939* VREFOUT
VIN7
0.1F
0
0
0
0
0 TITLE
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0
*Addition Pins Omitted for Clarity
Figure 8.THD vs Analog Input Frequency for Various Source Impedances Figure 9 shows a graph of THD versus analog input frequency for various supplies, while sampling at 1.5MHz with an SCLK of 20 MHz. In this case the source impedance is 10 .
0
Figure 10. Single Ended Mode Connection Diagram Differential Mode The AD7938/AD7939 can have 4 Differential Input Pairs by setting the MODE0 and MODE1 bits in the control register to 0 and 1 respectively.
Differential signals have some benefits over single ended signals including noise immunity based on the device's common mode rejection and improvements in distortion performance. Figure 11 defines the fully differential analog input of the AD7938/AD7939.
0
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COMMON MODE VOLTAGE
TITLE
VREF P-to-P
VIN+ AD7938/ AD7939*
VREF P-to-P
VIN-
0
*Additional Pins Omitted for Clarity
0 0 0 0 TITLE 0 0 0
Figure 11. Differential Input Definition
Figure 9.THD vs Analog Input Frequency for various Supply Voltages
THE ANALOG INPUTS
The AD7938/AD7939 has software selectable analog input configurations. The user can choose either 8 Single Ended Inputs, 4 Fully Differential Pairs, 4 Pseudo Differential Pairs or 7 Pseudo Differential Inputs. The analog input configuration is chosen by setting the MODE0/ MODE1 bits in the internal control register (See Table III). Single Ended Mode The AD7938/AD7939 can have 8 single ended analog input channels by setting the MODE0 and MODE1 bits in the control register both to 0. In applications where the signal source has a high impedance, it is recommended to buffer the analog input before applying it to the ADC. The internal reference is used to externally bias up a bipolar analog input signal. Figure 10 shows a typical
The amplitude of the differential signal is the difference between the signals applied to the VIN+ and VIN- pins in each differential pair (i.e. VIN+ - VIN-). VIN+ and VINshould be simultaneously driven by two signals each of amplitude VREF that are 180 out of phase. The amplitude of the differential signal is therefore -VREF to +VREF peakto-peak (i.e. 2 x VREF). This is regardless of the common mode (CM). The common mode is the average of the two signals, i.e. (VIN+ + VIN-)/2 and is therefore the voltage that the two inputs are centered on. This results in the span of each input being CM VREF/2. This voltage has to be set up externally and its range varies with VREF. As the value of VREF increases, the common mode range decreases. When driving the inputs with an amplfier, the actual common mode range will be determined by the amplifier's output voltage swing. Figures 12 and 13 show how the common mode range typically varies with VREF for both a 5 V and a 3 V power REV. PrD
-16-
PRELIMINARY TECHNICAL DATA AD7938/AD7939
supply. The common mode must be in this range to guarantee the functionality of the AD7938/AD7939. When a conversion takes place, the common mode is rejected resulting in a virtually noise free signal of amplitude -VREF to +VREF corresponding to he digital codes of 0 to 4095.
0
Differential Amplifier
0
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An ideal method of applying differential drive to the AD7938/ AD7939 is to use a differential amplifier such as the AD8138. This part can be used as a single ended to differential amplifier or as a differential to differential amplifier. In both cases the analog input needs to be bipolar. It also provides common mode level shifting and buffering of the bipolar input signal. Figure 14 shows how the AD8138 can be used as a single ended to differential amplifier. The positive and negative outputs of the AD8138 are connected to the respective inputs on the ADC via a pair of series resistors to minimize the effects of switched capacitance on the front end of the ADC. The RC low pass filter on each analog input is recommended in ac applications to remove high frequency components of the analog input. The architecture of the AD8138 results in outputs that are very highly balanced over a wide frequency range without requiring tightly matched external components. If the analog input source being used has zero impedance then all four resistors (Rg1, Rg2, Rf1, Rf2) should be the same. If the source has a 50 impedance and a 50 termination for example, the value of Rg2 should be increased by 25 to balance this parallel impedance on the input and thus ensure that both the positive and negative analog inputs have the same gain (see figure 14). The outputs of the amplifier are perfectly matched, balanced differential outputs of identical amplitude and are exactly 180o out of phase. The AD8138 is specified with 3 V, 5 V and 5 V power supplies but the best results are obtained when it is supplied by 5 V. A lower cost device that could also be used in this configuration with slight differences in characteristics to the AD8138 but with similar performance and operation is the AD8132.
TITLE
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0
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Figure 12. Input Common Mode Range versus VREF (VDD = 5V and VREF (max) = 3.5V)
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0
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TBD
0 0 0 0 0 TITLE 0 0 0
Figure 13. Input Common Mode Range versus VREF (VDD= 3V and VREF (max) = 2.2V)
Driving Differential Inputs
Differential operation requires that VIN+ and VIN- be simultaneously driven with two equal signals that are 180o out of phase. The common mode must be set up externally and has a range which is determined by VREF, the power supply and the particular amplifier used to drive the analog inputs. Differential modes of operation with either an ac or dc input, provide the best THD performance over a wide frequency range. Since not all applications have a signal preconditioned for differential operation, there is often a need to perform single ended to differential conversion.
Figure 14. Using the AD8138 as a Single Ended to Differential Amplifier
Pseudo Differential Mode The AD7938/AD7939 can have 4 Pseudo Differential pairs or 7 Pseudo Differential inputs by setting the MODE0 and MODE1 bits in the control register to 1, 0 and 1, 1 respectively. In the case of the 4 Pseudo differential pairs, VIN+ is connected to the signal source which must have an amplitude of VREF to make use of the full dynamic range of the part. A DC input in the range -100mV to +100mV is applied to the VIN- pin . The voltage applied to this input provides an offset from ground or -17-
REV. PrD
AD7938/AD7939
PRELIMINARY TECHNICAL DATA
Using the Sequencer Programmable Sequence (SEQ = 0, SHDW = 1 ) The AD7938/AD7939 may be configured to automatically cycle through a number of selected channels using the onchip programmable sequencer by setting SEQ = 0 and SHDW = 1 in the Control register. The Analog input channels to be converted on are selected by programming the relevent bits in the Shadow Register, see Table V. Once the shadow register has been programmed with the required sequence, the next conversion executed will be on the lowest channel programmed in the SHADOW register. The next conversion will be on the next highest channel in the sequence and so on. When the last channel in the sequence has been converted, the ADC will return to the first channel selected in the Shadow register It is not necessary to write to the control register once a sequencer operation has been initiated. The WRITE input must be kept high to ensure that the Control Register is not accidently overwritten, or a sequence operation interrupted. If the control register is written to at any time during the sequence then it must be ensured that the SEQ and SHDW bits are set to 1,0 to avoid interrupting the automatic conversion sequence. This pattern will continue until such time as the AD7938/AD7939 is written to and the SEQ and SHADOW bits are configured with any bit combination except 1,0. On completion of the sequence, the AD7938/AD7939 sequencer will return to the first selected channel in the Shadow register and commence the sequence again. Figure 17 shows a flow chart of the Programmable Sequence operation
a pseudo ground for the VIN+ input. In the case of the 7 Pseudo Differential inputs, the 7 inputs are referred to the voltage applied to VIN7. The benefit of pseudo differential inputs is that they separate the analog input signal ground from the ADCs ground allowing DC common mode voltages to be cancelled. Figure 15 shows a connection diagram for Pseudo Differential Mode.
VREF P-to-P
VIN+
AD7938/AD7939*
DC INPUT VOLTAGE RANGE 100mV
VINVREF
0.1F
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 15. Pseudo Differential Mode Connection Diagram
ANALOG INPUT SELECTION As illustrated in Table III, the user can set up their analog input configuration by setting the values in the MODE0 and MODE1 bits in the Control Register. Assuming the configuration has been chosen, there are different ways of selecting the analog input to be converted on depending on the state of the SEQ and SHDW bits in the Control register. Normal Multichannel Operation (SEQ=SHDW= 0) Any one of eight analog input channels or 4 pairs of channels may be selected for conversion in any order by setting the SEQ & SHDW bits in the Control register both to 0. The channel to be converted on is selected by writing to the address bits ADD2 - ADD0 in the control register to program the multiplexer prior to the conversion. This mode of operation is of a normal multichannel ADC where each data write selects the next channel for conversion. Figure 16 shows a flow chart of this mode of operation. The channel configurations are shown in table III.
TBD
Figure 17. Programmable Sequence Flow Chart
Consecutive Sequence (SEQ =1, SHDW = 1) A sequence of consecutive channels can be converted on beginning with channel 0 and ending with a final channel selected by writing to the ADD2-ADD0 bits in the Control register. This is done by setting the SEQ and SHDW bits in the control register both to 1. In this mode, the sequencer can be used without having to write to the Shadow register. Once the control register has been written to to set this mode up, the next conversion will be on Channel 0, then Channel 1 and so on until the channel selected via the address bits is reached. The cycle will begin again provided the WR input is tied high or if low, the SEQ and SHDW bits set to 1, 0; then the ADC will continue its pre-programmed automatic sequence uninterrupted. Figure 18 shows the flow chart of the Consecutive Sequence mode. -18- REV. PrD
TBD
Figure 16. Normal Multichannel Operation Flow Chart
PRELIMINARY TECHNICAL DATA AD7938/AD7939
Therefore, when operating at VDD = 5 V, the value of VREF can range from 100mV to a maximum value of 3.5V. When VDD = 4.75 V, VREF max = 3.17 V.
TBD
Example 2: VINmax = VDD + 0.3 VINmax = VREF + VREF/2 If VDD = 3.6V
Figure 18. Consecutive Sequence Mode Flow Chart
REFERENCE SECTION
then VINmax = 3.9 V Therefore 3xVREF/2 = 3.6 V VREF max = 2.6 V Therefore, when operating at VDD = 3 V, the value of VREF can range from 100mV to a maximum value of 2.4V. When VDD = 2.7 V, VREF max = 2 V. These examples show that the maximum reference applied to the AD7938/AD7939 is directly dependant on the value applied to VDD. The performance of the part at different reference values is shown in TBD to TBD. The value of the reference sets the analog input span and the common mode voltage range. Errors in the reference source will result in gain errors in the AD7938/AD7939 transfer function and will add to specified full scale errors on the part. When using an external reference, a capacitor of 0.1F should be used to decouple the VREF pin to AGND. Table VI lists examples of suitable voltage references that could be used that are available from Analog Devices and Figure 20 shows a typical connection diagram for an external reference.
Table VI Examples of Suitable Voltage References
The AD7938/AD7939 can operate with either the on chip reference or an external reference. The internal reference is selected by setting the REF bit in the interal Control register to 0. A block diagram of the internal reference circuitry is shown in Figure 19. The internal reference circuitry includes an on-chip 2.5 V band gap reference, and a reference buffer. When using the internal reference the VREFIN/VREFOUT pin should be decoupled to AGND with a 0.47F capacitor. This internal reference not only provides the reference for the analog to digital conversion but can also be used externally in the system. It is recommended that the reference output is buffered using an external precision opamp before applying it anywhere in the system.
BUFFER VREFIN/ VREFOUT REFERENCE
ADC
AD7938/ AD7939
Figure 19. Internal Reference Circuit Block Diagram Alternatively, an external reference source in the range of 100mV to 3.5V can be applied to the VREFIN/VREFOUT pin of the AD7938/AD7939. An external reference is selected by setting the REF bit in the interal Control register to 1.When using an external reference, the VREFIN/VREFOUT pin should be decoupled to AGND with a 0.1F capacitor. With a 5 V power supply, the specified reference is 2.5 V and maximum reference is 3.5V. With a 3 V power supply, the specified reference is 2.5V and the maximum reference is 2.6 V. In both cases, the reference is functional from 100mV. It is important to ensure that, when chosing the reference value, the maximum analog input range (VINmax) is never greater than VDD + 0.3V to comply with the maximum ratings of the device. The following two examples calculate the maximum VREF input that can be used when operating the AD7938/AD7939 at VDD of 5 V and 3 V respectively.
Reference Output Voltage
Initial Accuracy (% max) 1.2-2.8 0.08-0.8 0.08-0.4 0.06-0.1 0.04-0.2
Operating Current (A) 50 50 45 600 1000
AD589 AD1580 REF192 REF43 AD780
1.235 1.225 2.5 2.5 2.5
AD7938/ AD7939* AD780 NC VDD
0.1F 10nF 0.1F
1 2 VIN 3
Temp
OpSel
8 7
NC
VREF
Example 1: VINmax = VDD + 0.3 VINmax = VREF + VREF/2 If VDD = 5 V then VINmax = 5.3 V Therefore 3xVREF/2 = 5.3 V VREF max = 3.5 V REV. PrD -19-
Vout Trim
NC 6 2.5 V
0.1F
4 GND
5
NC
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 20. Typical VREF Connection Diagram
AD7938/AD7939
Digital Inputs
PRELIMINARY TECHNICAL DATA
the two LSBs of the low byte are zeros and are followed by 6-bits of conversion data. For a high byte read, DB0 to DB4 provide the 4MSBs of the 12-/10-bit word. The remainder of the bits in the high byte provide the Channel ID. Figure 1 shows the read cycle timing diagram for a 12-/10-bit transfer. When operated in Word mode, the HBEN input doesnt exist and only the first read operation is required to access data from the device. When operated in Byte mode, the two read cycles shown in figure 21 are required to access the full data word from the device. The CS and RD signals are gated internally and level triggered active low. In either Word mode or Byte mode, CS and RD may be tied together as the timing specification t8 and t9 is 0ns min. The data is placed onto the data bus a time t11 after both CS and RD go low. The RD rising edge can be used to latch data out of the device. After a time, t9, the data lines will become 3 stated.
HBEN t13 CS t8 RD t11 DB0-DB7
LOW BYTE
The digital inputs applied to the AD7938/AD7939 are not limited by the maximum ratings which limit the analog inputs. Instead, the digital inputs applied can go to 7V and are not restricted by the AVDD +0.3V limit as on the analog inputs. Another advantage of the digital inputs not being restricted by the AVDD + 0.3 V limit is the fact that power supply sequencing issues are avoided. If any of these inputs are applied before AVDD then there is no risk of latch-up as there would be on the analog inputs if a signal greater than 0.3 V was applied prior to AVDD. V DRIVE Input The AD7938/AD7939 has a VDRIVE feature. VDRIVE controls the voltage at which the Parallel Interface operates. VDRIVE allows the ADC to easily interface to both 3 V and 5 V processors. For example, if the AD7938/AD7939 were operated with an AVDD of 5V, and the VDRIVE pin could be powered from a 3V supply. The AD7938/ AD7939 has better dynamic performance with an AVDD of 5V while still being able to interface to 3V processors. Care should be taken to ensure VDRIVE does not exceed AVDD by more than 0.3 V. (See Absolute Maximum Ratings Section). PARALLEL INTERFACE The AD7938/AD7939 has a flexible, high speed, parallel interface. This interface is 12-bits (AD7938) or 10-bits (AD7939) wide and is capable of operating in either Word (W/B tied high) or Byte (W/B tied low) mode. The CONVST signal is used to power up the ADC and to initiate conversions. A falling edge on the CONVST signal is used to initiate conversions. Once the CONVST signal goes low, the BUSY signal goes high for the duration of the Conversion. At the end of the Conversion, BUSY goes low and can be used to activate an Interrupt Service Routine. The CS and RD lines are then activated in parallel to read the 12- or 10- bits of conversion data. When operating the device Auto Shutdown or Auto Standby mode, where the ADC powers down at the end of each conversion, a rising edge on the CONVST signal is used to power up the device. Reading Data from the AD7938/AD7939 With the W/B pin tied logic high, the AD7938/AD7939 interface operates in Word mode. In this case, a single read operation from the device accesses the Conversion data word on pins DB0 to DB11. The DB8/HBEN pin assumes its DB8 function. With the W/B pin tied to logic low, the AD7938/AD7939 interface operates in Byte mode. In this case, the DB8/HBEN pin assumes its HBEN function. Conversion data from the AD7938/ AD7939 must be acessed in two read operations with 8 bits of data provided on DB0 to DB7 for each of the read operations. The HBEN pin determines whether the read operation accesses the high byte or the low byte of the12or 10-bit word. For a low byte read, DB0 to DB7 provide the 8 LSBs of the 12-bit word. For 10-bit operation,
t14
t13
t14
t9 t10 t12
t15
HIGH BYTE
Figure 21. Read Cycle Timing for Byte Mode Operation
Writing Data to the AD7938/AD7939 With W/B tied logic high, a single Write operation transfers the full data word on DB0 to DB11/9 to either the Control register or the Shadow register on the AD7938/ AD7939. The DB8/HBEN pin assumes its DB8 function. Data to be written to the AD7938/AD7939 should be provided on the DB0 to DB11/9 inputs with DB0 being the LSB of the data word. With W/B tied logic low, the AD7938/AD7939 requires two write operations to transfer a full 12-/10-Bit word. DB8/HBEN assumes its HBEN function. Data to be written to the AD7938/AD7939 should be provided on the DB0 to DB7 inputs. HBEN determines whether the byte which is to be written is high byte or low byte data. The low byte of the data word should be written first with DB0 being the LSB of the full data word. For the high byte write, HBEN should be high and the data on the DB0 input should be data bit 8 of the 12-/10-bit word. Figure 1 shows the write cycle timing diagram of the AD7938/AD7939. When operated in Word mode, the HBEN input does not exist and only the first write operation is required to write data to the device. Data should be provided on DB0 to DB9/DB11. When operated in Byte mode, the two write cycles shown in Figure 22 are required to write the full data word to the AD7938/AD7939. In figure 23, the first write transfers the lower 8 bits of the full data from DB0 to DB7 and the second write transfers the upper 2 or 4 bits of the data word. The CS and WR signals are gated internally. CS and WR may be tied together as the timing specification for t2 REV. PrD
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PRELIMINARY TECHNICAL DATA AD7938/AD7939
and t3 is 0ns min. The data is latched into the device on the rising edge of WR. The data needs to be setup a time t5 before the WR rising edge and held for a time t6 after the WR rising edge.
HBEN t16 CS t2 WR DB0-DB7 t4 t5
LOW BYTE
that the power up time has elapsed before initiating a conversion. Auto Standby (PM1 = 0; PM0 = 0) In this mode of operation, the AD7938/AD7939 automatically enters Standby mode at the end of each conversion. When this mode is entered, all circuitry on the AD7938/ AD7939 is powered down except the internal reference. A rising edge on CONVST will power up the device which will take at least 1sec.
POWER VS. THROUGHPUT RATE
t17
t16
t17
t3
t6
HIGH BYTE
Figure 22. Write Cycle Timing for Byte Mode Operation
MODES OF OPERATION
A big advantage of powering the ADC down after a conversion is that the power consumption of the part is significantly reduced at lower throughput rates. When using the different power modes, the AD7938/AD7939 is only powered up for the duration of the conversion. Therefore, the average power consumption is significantly reduced.
MICROPROCESSOR INTERFACING AD7938/AD7939 To ADSP-2189 Interface
The AD7938/AD7939 has a number of different power modes of operation. These modes are designed to provide flexible power management options. Different options can be chosen to optimize the power dissipation/throughput rate ratio for differing applications. The mode of operation is selected by the power management bits, PM1 and PM0, in the Control register, as detailed in Table II. At power on reset, the default power up condition is normal mode. Normal Mode (PM1 = PM0 = 1) This mode is intended for the fastest throughput rate performance as the user does not have to worry about any power up times as the AD7938/AD7939 remaining fully powered up at all times. At power on reset, this mode is the default setting in the control register. Full Shutdown Mode (PM1 = 1; PM0 = 0) When this mode is entered, all circuitry on the AD7938/ AD7939 is powered down. The part retains the information in the Control Register during the Full Shutdown. The AD7938/AD7939 remains in Full Shutdown mode until the power management bits in the Control Register are changed. If a write to the Control register occurs while the part is in Full Shutdown mode, and the Power Management bits are changed to PM0 = PM1 = 1, i.e. Normal Mode, the part will begin to power up on the CONVST rising edge. To ensure the part is fully powered up before a conversion is initiated, the power up time, TBD, should be allowed before the CONVST falling edge, otherwise, invalid data will be read. AutoShutdown (PM1 = 0; PM0 = 1) In this mode of operation, the AD7938/AD7939 automatically enters shutdown at the end of each conversion. In shutdown mode, all internal circuitry on the device is powered. The part retains information in the Control register during shutdown. It remains in shutdown mode until the next rising edge of CONVST. On this rising edge, the part will begin to power up and the power up time will depend on whether the user is operating with the internal or external reference. The user should ensure
Figure 23 shows a typical interface between the AD7938/ AD7939 and the ADSP-2189. The ADSP-2189 can be used in one of two memory modes - Full Memory Mode and Host Mode. The Mode C pin determines in which mode the processor works. The interface, in Figure 23 is set up to have the processor working in Full Memory Mode, which allows full external addressing. When the AD7938/AD7939 has finished converting, the BUSY line goes low and thus requests an interrupt through the IRQ2 pin. The IRQ2 interrupt has to be set up in the interrupt control register as edge-sensitive. The DMS (Data Memory Select) pin latches in the address of the ADC into the address decoder and therefore starts a read operation.
TBD
Figure 23. Interfacing to the ADSP-2189
REV. PrD
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AD7938/AD7939
APPLICATION HINTS Grounding and Layout
PRELIMINARY TECHNICAL DATA
of the board, and clock signals should never run near the analog inputs. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This will reduce the effects of feedthrough through the board. A microstrip technique is by far the best but is not always possible with a doublesided board.
The printed circuit board that houses the AD7938/ AD7939 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. This facilitates the use of ground planes that can be easily separated. A minimum etch technique is generally best for ground planes as it gives the best shielding. Digital and analog ground planes should be joined in only one place and the connection should be a star ground point established as close to the Ground pins on the AD7938/AD7939 as possible. Avoid running digital lines under the device as this will couple noise onto the die. The analog ground plane should be allowed to run under the AD7938/AD7939 to avoid noise coupling. The power supply lines to the AD7938/AD7939 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching signals like clocks should be shielded with digital ground to avoid radiating noise to other sections
In this technique the component side of the board is dedicated to ground planes while signals are placed on the solder side. Good decoupling is also important. All analog supplies should be decoupled with 10F tantalum capacitors in parallel with 0.1F capacitors to GND. To achieve the best from these decoupling components, they must be placed as close as possible to the device.
OUTLINE DIMENSIONS
Dimensions shown in inches and mm
32 Lead LFCSP CP-32
0.197 (5.0) BSC SQ
0.024 (0.60) 0.017 (0.42) 0.009 (0.24) 0.024 (0.60) 0.017 (0.42) 25 0.009 (0.24) 24 0.187 (4.75) BSC SQ 0.012 (0.30) 0.009 (0.23) 0.007 (0.18) 0.020 (0.50) 0.016 (0.40) 0.012 (0.30)
17 16
0.010 (0.25) MIN
32
1
PIN 1 INDICATOR
TOP VIEW
BOTTOM VIEW
0.128 (3.25) 0.122 (3.10) SQ 0.116 (2.95)
98
12MAX 0.035 (0.90) MAX 0.033 (0.85) NOM SEATING PLANE
0.031 (0.80) MAX 0.026 (0.65) NOM
0.138 (3.50) REF
0.002 (0.05) 0.0004 (0.01) 0.020 (0.50) 0.008 (0.20) 0.0 (0.00) BSC REF CONTROLLING DIMENSIONS ARE IN MILLIMETERS DIMENSIONS MEET JEDEC MO=220-VHHD-2
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REV. PrD

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