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PLL702-01
Clock Generator for PowerPC Based Applications
FEATURES
* * * * * * * * * * *
*
PIN ASSIGNMENT (28 pin SSOP)
CPUDRV_SEL^ XIN XOUT / ASIC2_OE*^ VDD_ANA VDD_DIG VDD_PC I PCI / PCI_SEL*T GND_PCI GND_USB VDD_USB USB / USB_SEL*T VDD_ASIC2 ASIC2 A ASIC2 B Note :
1 CPU Clock output with selectable frequencies (50, 66, 75, 80, 83, 90, 100,125 or 133 MHz). 1 ASIC output clock (at CPU clock or CPU clock / 2). 2 ASIC output clocks (at CPU clock) w/ output enable. 1 PCI output clock w/ output enable 1 Selectable 48, 30 or 12MHz (USB) output. Selectable Spread Spectrum (SST) for EMI reduction on ASIC and CPU. PowerPC compatible output and drive CPU Clock. Selectable reduced 67% drive strength on CPU Clock Advanced, low power, sub-micron CMOS processes. 14.31818MHz fundamental crystal input. 3.3V and/or 2.5V operation. Available in 28-Pin 209mil SSOP (QSOP).
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
CLK_SEL0T CLK_SEL1T SSCO^ SSC1^ GND_ANA GND_CPU CP U o VDD_CPU VDD_ASIC1 ASIC1 GND_ASIC1 ^ ASIC1_SEL GND_DIG GND_ASIC2
o:
^: Internal pull-up resistor Selectable reduced drive strength
DESCRIPTION
The PLL702-01 is a low cost, low jitter, and high performance clock synthesizer for generic PowerPC based applications. It provides one CPU clock, three ASIC outputs, one PCI output, and a selectable 48, 30 or 12MHz (USB) output. The user can choose between 9 different CPU clock frequencies, while the ASIC output can be identical or half of the CPU frequency. Low EMI Spread Spectrum Technology is available for the CPU, ASIC and PCI clocks. The CPU drive strength is user selectable from 100% to 67%. All frequencies are generated from a single low cost 14.31818MHz crystal. The CPU and ASIC clock can be driven from an independent 2.5V power supply.
FREQUENCY TABLES
CLK_SEL1 CLK_SEL0 CPU (MHz)
ASIC1 (MHz)
ASIC1_SEL =1 ASIC1_SEL =0
PLL702-01
*: Bi-directional pin T Tri-level input :
ASIC2 (MHz)
PCI* (MHz)
PCI_SEL =0 PCI_SEL =M
0 0 0 M M M 1 1 1 Notes:
0 M 1 0 M 1 0 M 1
50 66 75 80 83 90 100 125 133
50 66 75 80 83 90 100 125 133
25 33 37.5 40 41.5 45 50 62.5 66.5
50 66 75 80 83 90 100 125 133
62.5 66.7 62.5 66.7 66.7 66.7 66.7 62.5 65.5
31.25 33.35 31.25 33.35 33.35 33.35 33.35 31.25 32.75
When CPU=90MHz, it implements 88.88MHz to meet PCI=33.3MHz/66.6MHz; When CPU=133MHz, it implements 130.9MHz to meet Power PC clock AC Timing Specification. * PCI_SEL=1 sets the Tri-state (output disabled) mode of the output.
BLOCK DIAGRAM
USB_SEL Control Logic PLL USB CPU_CLK PLL SST DIV 2 ASIC2_OE PCI PCI_OE Control Logic ASIC1 ASIC2(A:B)
XIN XOUT SSC(0:1) CLK_SEL(0:1) ASIC1_SEL PCI_SEL
XTAL OSC
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 07/18/05 Page 1
PLL702-01
Clock Generator for PowerPC Based Applications
PIN DESCRIPTIONS
Name
CPUDRV_SEL
Number
1
Type
I
Description
CPU drive strength selector pin. The CPU drive strength can be set to 67% of nominal strength with CPUDRV_SEL = 0. When CPUDRV_SEL = 1, the CPU drive strength will be 100% of the nominal strength. Internal pull-up of 60k. 0=connect to GND, 1=leave open. Crystal input to be connected to a 14.31818MHz fundamental crystal (CL = 20pF, parallel resonant mode). Load capacitors have been integrated on the chip. No external Load capacitor is required. Bi-directional pin. Upon power-on, the value of ASIC2_OE is latched in and used to enable / disable the ASIC2A and ASIC2B outputs (outputs are enabled if ASIC2_OE=1, otherwise, outputs are in tri-state). Internal pull-up of 120 k. After the input has been latched-in, the pin serves as Crystal connection. 3.3V power supply and GND. CPU, PCI, ASIC1 and ASIC2 outputs have separate power supply pins (VDD and GND). VDD_CPU, VDD_ASIC1 and VDD_ASIC2 can accept 3.3V and/or 2.5V power supply. Other VDD pins are to be supplied 3.3V Bi-directional pin. Upon power-on, the value of PCI_SEL is latched in and used to select the PCI clock output (see frequency table on p.1). PCI output is disabled (tri-state) when PCI_SEL=1. PCI clock will be 33MHz (min. 31.25MHz) if PCI_SEL=M (not connected), and 66MHz (min. 62.5MHz) if PCI_SEL=0. 0=15k to GND, M=leave open, 1=15k to VDD_PCI Bi-directional pin. Upon power-on, the value of USB_SEL is latched in and used to select the USB output (see USB selection table on page 3). After the input has been latched-in, the pin serves as USB (48, 30 or 12 MHz) output. 0=15k to GND, M=leave open, 1=15k to VDD_USB ASIC clock signal output pins. ASIC2A and ASIC2B will have the same frequency as CPU. These outputs can be disabled through ASIC2_OE. ASIC1 frequency select input pin (see also frequency table on p.1). ASIC1 will have the same frequency as CPU if ASIC1_SEL = 1, and have half of CPU if ASIC_SEL = 0. Internal pull-up of 60 k. 0=connect to GND, 1=leave open ASIC1 output pin (see frequency table on p.1 and ASIC1_SEL pin description). CPU clock signal output pin. The CPU clock frequency is selected as per the frequency table on page 1, depending on the value of CLK_SEL(0:1). Selectable drive strength through CPUDRV_SEL. Bi-level input with Pull-up for SST control (see Spread Spectrum selection table on p.3). 0=connect to GND, 1=leave open. Tri-level inputs for CPU clock frequency selection (see table on p.1). 0=connect to GND, M=not connected, 1=connect to VDD_ANA.
XIN
2
I
XOUT/ ASIC2_OE VDD_ANA / GND_ANA VDD_DIG / GND_DIG VDD_xxx / GND_xxx for USB, CPU, PCI, ASIC1 and ASIC2
3 4, 5, 16, 24 6, 8, 9, 10, 12, 15, 18, 20, 21, 23 7
B
P P
PCI / PCI_SEL
B
USB / USB_SEL ASIC2A and ASIC2B ASIC1_SEL ASIC1 CPU SSC(0:1) CLK_SEL(0:1)
11 13, 14 17 19 22 25, 26 27, 28
B O I O O I I
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 07/18/05 Page 2
PLL702-01
Clock Generator for PowerPC Based Applications
USB OUTPUT FREQUENCY AND CPU DRIVE STRENGTH SELECTION TABLES
USB_SEL
0 M 1
USB
48 MHz 30 MHz 12 MHz
CPUDRV_SEL
0 1
CPU drive strength
67% (reduced) 100% (nominal)
SPREAD SPECTRUM SELECTION TABLE
SSC1 0 0 1 1 SSC0 0 1 0 1 Spread Spectrum Modulation OFF - 0.50% - Downspread - 1.00% - Downspread - 1.25% - Downspread
FUNCTIONAL DESCRIPTION Tri-level and two-level inputs
In order to reduce pin usage, the PLL702-01 uses tri-level input pins. These pins allow 3 levels for input selection: namely, 0 = Connect to GND, 1 = Connect to VDD, M = Do not connect. Thus, unlike the two-level selection pins, the tri-level input pins are in the "M" (mid) state when not connected. In order to connect a tri-level pin to a logical "zero", the pin must be connected to GND. Likewise, in order to connect to a logical "one", the pin must be connected to VDD.
Connecting a bi-directional pin
The PLL702-01 also uses bi-directional pins. The same pin serves as input upon power-up, and as output as soon as the inputs have been latched. The value of the input is latched-in upon power-up. Depending on the pin (see pin description), the input can be tri-level or a standard two-level. Unlike unidirectional pins, bi-directional pins cannot be connected directly to GND or VDD in order to set the input to "0" or "1", since the pin also needs to serve as output. In the case of two level input pins, an internal pullup resistor is present. This allows a default value to be set when no external pull down resistor is connected between the pin and GND (by definition, a tri-level input has a the default value of "M" (mid) if it is not connected). In order to connect a bidirectional pin to a non-default value, the input must be connected to GND or VDD through an external pull-down/pull-up resistor. Note: when the output load presents a low impedance in comparison to the internal pull-up resistor, the internal pull-up resistor may not be sufficient to pull the input up to a logical "one", and an external pull-up resistor may be required. For bi-directional inputs, the external loading resistor between the pin and GND has to be sufficiently small (compared to the internal pull-up resistor) so that the pin voltage be pulled below 0.8V (logical "zero"). In order to avoid loading effects when the pin serves as output, the value of the external pull-down resistor should however be kept as large as possible. In general, it is recommended to use an external resistor of around one sixth to one quarter of the internal pull-up resistor (see Application Diagram). Note: when the output is used to drive a load presenting an small resistance between the output pin and VDD, this resistance is in essence connected in parallel to the internal pull-up resistor. In such a case, the external pull-down resistor may have to be dimensioned smaller to guarantee that the pin voltage will be low enough achieve the desired logical "zero". This is particularly true when driving 74FXX TTL components.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 07/18/05 Page 3
PLL702-01
Clock Generator for PowerPC Based Applications
APPLICATION DIAGRAM: BI-DIRECTIONAL PINS WITH INTERNAL PULL-UP
Internal to chip VDD
External Circuitry
Rup Power Up Reset
R RB
Output
EN
Bi-directional pin
Clock Load
Latched Input
Latch
RUP/4
Jumper options
NOTE: Rup=Internal pull-up resistor (see pin description). Power-up Reset : R starts from 1 to 0 while RB starts from 0 to 1.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 07/18/05 Page 4
PLL702-01
Clock Generator for PowerPC Based Applications
VDD Power Up Ramp requirements:
At startup, the chip reads a lot of settings for operation according to the application's requirements. Since reading the settings is done only at startup and then frozen for the time of operation, it is important that the power-up environment is somewhat controlled to facilitate proper reading of the settings. The important VDD pins are VDD_ANA and VDD_DIG and they should apply to the following two-startup requirements: 1. VDD_DIG should be equally fast or slower than VDD_ANA. VDD_DIG performs a chip reset when VDD has reached a certain level and VDD_ANA should have reached at least up to the same level as well to properly process the reset. 2. The VDD Power Up Ramp of VDD_DIG and VDD_ANA should pass through the section 1.8V to 2.5V no faster than 100s and with a continuously increasing slope. In this section the tri-level select inputs are read. 3. After VDD Power off, VDD should be allowed to go to 0V and stay there for at least 1ms before a new VDD Power on. It is important that proper preconditions exist at every startup. Remaining charges in the chip or in circuit filter capacitors may interfere with the preconditions so it is important that VDD has been at 0V for some time before each startup.
VDD off
3.3V
2.97V 2.5V 2.2V
1.8V
VDD on
GND (0V)
No limit
Reset enable
Min 1ms >100us
Min 1s
Reset disable
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 07/18/05 Page 5
PLL702-01
Clock Generator for PowerPC Based Applications
Electrical Specifications
1. Absolute Maximum Ratings PARAMETERS
Supply Voltage Input Voltage, dc Output Voltage, dc Storage Temperature Ambient Operating Temperature* Junction Temperature Lead Temperature (soldering, 10s) ESD Protection, Human Body Model
SYMBOL
VDD VI VO TS TA TJ
MIN.
-0.5 -0.5 -65 -40
MAX.
4.6 VDD+0.5 VDD+0.5 150 85 125 260 2
UNITS
V V V C C C C kV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. * Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only.
2. AC Specifications PARAMETERS
Crystal Input Frequency SST modulation sweep rate Output Rise Time Output Fall Time Duty Cycle Max. output skew CPU and ASIC1
CONDITIONS
MIN.
TYP.
14.31818 28
MAX.
UNITS
MHz kHz ns ns % ps
Max. output skew CPU and ASIC2 Max. Absolute Period Jitter Max. Jitter, cycle to cycle
0.8V to 2.0V with no load 2.0V to 0.8V with no load At VDD/2 Equal loading (20 pF) Equal frequency & drive strength Equal Power Supply for both ASIC and CPU Equal loading (20 pF) Equal frequency & drive strength Equal Power Supply for both ASIC and CPU Long term, No SST Long term + Short term
45
50 500
1.5 1.5 55 750
200
250 150 120
ps ps ps
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 07/18/05 Page 6
PLL702-01
Clock Generator for PowerPC Based Applications
3. DC Specifications PARAMETERS SYMBOL
VDD_ANA VDD_DIG VDD_USB VDD_PCI VDD_ASIC1 VDD_ASIC2 VDD_CPU VIH VIL VIH VIL VIH VIL VOH VOL VOH Iout IDD IS
CONDITIONS
Nominal voltage is 3.3V Nominal voltage is 2.5V Nominal voltage is 3.3V
MIN.
2.97 2.25 2.97
TYP.
MAX.
3.63 2.75 3.63
UNITS
V V V V V V V V V V
Operating Voltage
Input Input Input Input Input Input
High Voltage Low Voltage High Voltage Low Voltage High Voltage Low Voltage
VDD/2 VDD/2 For all Tri-level input For all Tri-level input For all normal input For all normal input IOH = -25mA VDD = 3.3V IOL = 25mA IOH = -8mA No Load VDD-0.5
VDD/2 - 1 0.5
2 0.8 2.4 0.4 VDD-0.4 25 35 100
Output High Voltage Output Low Voltage Output High Voltage At CMOS Level Nominal Output Current Operating Supply Current Short-circuit Current
V V mA mA mA
4. Crystal Specifications PARAMETERS
Crystal Resonator Frequency Crystal Loading Rating Recommended ESR
SYMBOL
FXIN CL (xtal) RE
CONDITIONS
Parallel Fundamental Mode AT cut
MIN.
TYP.
14.31818 21
MAX.
UNITS
MHz pF
30
Note: A detailed crystal specification document is also available for this part.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 07/18/05 Page 7
PLL702-01
Clock Generator for PowerPC Based Applications
PACKAGE INFORMATION
Package Pins#
E E1
SSOP (QSOP) 209mil 28 mm inches max 2.0 0.05 0.25 0.09 9.9 7.40 5.00 0.38 0.25 10.5 8.20 5.60 0.002 0.01 0.004 0.390 0.291 0.197 0.015 0.010 0.413 0.323 0.220 min max 0.079
Unit min A A1 B
D
B
e
C D
A
C
E E1
L A1
e
0.65BSC 0.55 0.95
0.0256BSC 0.022 0.038
28PIN SSOP
L
ORDERING INFORMATION
For part ordering, please contact our Sales Department: 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991
PART NUMBER
The order number for this device is a combination of the following: Device number, Package type and Operating temperature range
PLL702-01 X X X X
PART NUMBER NONE= TUBE R=TAPE AND REEL
NONE=NORMAL PACKAGE L=GREEN PACKAGE
PACKAGE TYPE X=SSOP Part / Order Number PLL702-01XC-R PLL702-01XC PLL702-01XCLR PLL702-01XCL Marking P702-01XC P702-01XC P702-01XCL P702-01XCL
TEMPERATURE C=COMMERCIAL, I=INDUSTRIAL Package Option SSOP SSOP SSOP SSOP -Tape and Reel -Tubes -Tape and Reel -Tubes Temperature 0 to +70C 0 to +70C 0 to +70C 0 to +70C
PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink's products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 07/18/05 Page 8

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