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CS7054
CS7054
Low Side PWM FET Controller
Description
The CS7054 is a monolithic integrated circuit designed primarily to control the rotor speed of permanent magnet, direct current (DC) brush motors. It drives the gate of an N channel power MOSFET or IGBT with a user-adjustable, fixed frequency, variable duty cycle, pulse width modulated (PWM) signal. The CS7054 can also be used to control other loads such as incandescent bulbs and solenoids. Inductive current from the motor or solenoid is recirculated through an external diode. The CS7054 accepts a DC level input signal of 0 to 5V to control the pulse width of the output signal. This signal can be generated by a potentiometer referenced to the onchip 5V linear regulator, or a filtered 0% to 100% PWM signal also referenced to the 5V regulator. The IC is placed in a sleep state by pulling the CTL lead below 0.5V. In this mode everything on the chip is shut down except for the on-chip regulator and the overall current draw is less than 275 A. There are a number of on-chip diagnostics that look for potential failure modes and can disable the external power MOSFET.
Features
s 200 mA Peak PWM Gate Drive Output s Patented Voltage Compensation Circuit s 100% Duty Cycle Capability s 5V, 3% Linear Reg. s Low Current Sleep Mode s Overvoltage Protection s Over Current Protection of External MOSFET / IGBT s Output Inhibit
Application Diagram
Package Options
MOT+
14 Lead PDIP
VBAT 42.5mH RS 51 1000mF 1000mF OUTPUT VCC Gnd PGnd FLT INH 1M 10mF RGATE 6 .01mF MOT-
OUTPUT 1 Gnd 2 FLT 3 COSC 4
RCS1 CCS 51 .022mF RCS2 RSENSE 4mW
14 13 12
VCC PGnd INH
CFLT COSC ROSC 105K
.25mF 390pF
COSC
ROSC CTL NC
IADJ
ISENSE+ ISENSE-
11 IADJ 10 ISENSE+ 9 8
ROSC 5 CTL 6 NC 7
ISENSEVREG
VREG
51
Input 10K 10K P1 100K N1 10K 10mF 10K 10K
10K
Consult factory for 16 lead SO wide package.
Cherry Semiconductor Corporation 2000 South County Trail, East Greenwich, RI 02818 Tel: (401)885-3600 Fax: (401)885-5786 Email: info@cherry-semi.com Web Site: www.cherry-semi.com
Rev. 4/21/99
1
A
Company
CS7054
Absolute Maximum Ratings Storage Temperature ................................................................................................................................................-65uC to 150uC VCC ................................................................................................................................................................................-0.3V to 30V Supply Voltage Range (load dump = 26Vw/series 511/2 resistor) VCC Peak Transient Voltage.....................................40V Input Voltage Range (at any input) ...........................................................................................................................-0.3V to 10V Maximum Junction Temperature ..........................................................................................................................................150uC ESD Capability (Human Body Model) ....................................................................................................................................2kV Lead Temperature Soldering: Wave Solder (through hole styles only)..........................................10 sec. max, 260C peak Electrical Characteristics: 8V < VCC < 16V, -40uC < TA < 125C, (unless otherwise specified)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
s VCC Supply Operating Current Supply Quiescent Current Overvoltage Shutdown Overvoltage Hysteresis VCC = 12V 18 150 5 170 19.5 325 10 275 21 500 mA A V mV
s Control (CTL) Control Input Current Sleep Mode Threshold Sleep Mode Hysteresis CTL = 0V to 5V -2 8% 50 0.1 10% 100 2 12% 150 A VREG mV
s Current Sense Differential Voltage Sense IADJ Input Current IADJ =51.2% VREG and RCS1= 511/2 IADJ = 0V to 5V 60.5 -5 0.3 79.5 2 mV A
s Linear Regulator VREG Output Voltage VCC = 13.2V 4.85 5.00 5.15 V
s Inhibit Inhibit Threshold Inhibit Hysteresis s External Drive (OUTPUT) Output Frequency Voltage to Duty Cycle Conversion Output Rise Time Output Fall Time Output Sink Current Output Source Current Output High Voltage Output Low Voltage ROSC = 105k1/2, COSC = 390pF VCC = 13V, CTL = 30% VREG VCC = 13V, CTL = 70% VREG VCC = 13V, RGATE = 61/2, CGATE = 5nF VCC = 13V, RGATE = 61/2, CGATE = 5nF VCC = 13V, RGATE = 61/2, CGATE = 5nF VCC = 13V, RGATE = 61/2, CGATE = 5nF IOUT = 1mA IOUT = -1mA 2 VCC - 1.7 1.3 17 26.3 69.5 .25 .30 400 400 20 23 38.5 81.5 1 1 kHz % % s s mA mA V V 40% 150 50% 325 60% 500 VREG mV
Package Lead Description
PACKAGE LEAD # LEAD SYMBOL FUNCTION
CS7054
14 Lead PDIP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 OUTPUT Gnd FLT COSC ROSC CTL NC VREG ISENSEISENSE+ IADJ INH PGnd VCC MOSFET Gate Drive Ground Fault time out capacitor Oscillator capacitor Oscillator resistor Pulse width control input No connection 5V linear regulator Current sense minus Current sense plus Current limit adjust Output Inhibit Power ground for on chip clamp Positive power supply input
Application Information Theory Of Operation Oscillator The IC sets up a constant frequency triangle wave at the COSC lead whose frequency is determined by the external components ROSC and COSC by the following equation: 0.83 ROSC COSC T = 2COSC (VPEAK - VVALLEY) ICOSC ICOSC = VCC ROSC IROSC is multiplied by two (2) internally and transferred to the COSC lead. Therefore:
The period of the oscillator is:
Frequency =
The peak and valley of the triangle wave are proportional to VCC by the following: VVALLEY = 0.2 VCC VPEAK = 0.8 VCC
This is required to make the voltage compensation function properly. In order to keep the frequency of the oscillator constant the current that charges COSC must also vary with supply. ROSC sets up the current which charges COSC. The voltage across ROSC is 50% of VCC and therefore: VCC ROSC
The ROSC and COSC components can be varied to create frequencies over the range of 15Hz to 25kHz. With the suggested values of 105k1/2 and 390pF for ROSC and COSC respectively, the nominal frequency will be approximately 20 kHz. IROSC, at VCC = 14V, will be 66.7 A. IROSC should not change over a more than 2:1 ratio and therefore COSC should be changed to adjust the oscillator frequency. Voltage Duty Cycle Conversion The IC translates an input voltage at the CTL lead into a duty cycle at the OUTPUT lead. The transfer function incorporates Cherry SemiconductorOs patented Voltage Compensation method to keep the average voltage and current across the load constant regardless of fluctuations 3
IROSC = 0.5
CS7054
Application Information: continued in the supply voltage. The duty cycle is varied based upon the input voltage and supply voltage by the following equation: 2.8 VCTL VCC tial voltage across these two leads is amplified internally and compared to the voltage at the IADJ lead. The gain, AV, is set internally and externally by the following equation: VI(ADJ) ISENSE+ - ISENSE-
Duty Cycle = 100%
AV =
=
37000 1000 + RCS
An internal DC voltage equal to: VDC = (1.683 VCTL) + (VVALLEY) is compared to the oscillator voltage to produce the compensated duty cycle. The transfer is set up so that at VCC = 14V the duty will equal VCTL divided by VREG. For example at VCC = 14V, VREG = 5V and VCTL = 2.5V, the duty cycle would be 50% at the output. This would place a 7V average voltage across the load. If VCC then drops to 10V, the IC would change the duty cycle to 70% and hence keep the average load voltage at 7V.
The current limit (ILIM) is set by the external current sense resistor (RSENSE) placed across the ISENSE+ and ISENSE- terminals and the voltage at the IADJ lead. (1000 + RCS) 37000 VI(ADJ) RSENSE
ILIM =
120% VCC = 8V 100%
80% Duty Cycle( %) VCC = 14V 60% VCC = 16V 40%
The RCS resistors and CCS components form a differential low pass filter which filters out high frequency noise generated by the switching of the external MOSFET and the associated lead noise. RCS also forms an error term in the gain of the ILIM equation because the ISENSE+ and ISENSEleads are low impedance inputs thereby creating a good current sensing amplifier. Both leads source 50A while the chip is in run mode. RCS should be much less than 1000 1/2 to minimize error in the ILIM equation. IADJ should be biased between 1V and 4V. When the current through the external MOSFET exceeds ILIM, an internal latch is set and the output pulls the gate of the MOSFET low for the remainder of the oscillator cycle (fault mode). At the start of the next cycle, the latch is reset and the IC reverts back to run mode until another fault occurs. If a number of faults occur in a given period of time, the IC Otimes outO and disables the MOSFET for a long period of time to let it cool off. This is accomplished by charging the CFLT capacitor each time an over current condition occurs. If a cycle goes by with no overcurrent fault occurring, an even smaller amount of charge will be removed from CFLT. If enough faults occur together, eventually CFLT will charge up to 2.4V and the fault latch will be set. The fault latch will not be reset until the CFLT discharges to 0.6V. This action will continue indefinitely if the fault persists. The off time and on time are set by the following: 2.4V - 0.6V 4.5A
20%
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% CTL Voltage (% of VREG)
Figure 1: Voltage Compensation
5V Linear Regulator There is a 5V, 5mA linear regulator available at the VREG lead for external use. This voltage acts as a reference for many internal and external functions. It has a drop out of approximately 1.5V at room temperature and does not require an external capacitor for stability. Current Sense and Timer The IC differentially monitors the load current on a cycle by cycle basis at the ISENSE+ and ISENSE- leads. The differen4
Off Time = CFLT
CS7054
Application Information: continued Overvoltage Shutdown On Time = CFLT 2.4V - 0.6V IAVG The IC will disable the output during an overvoltage event. This is a real time fault event and does not set the internal latch and therefore is independent of the oscillator timing (i.e. asynchronous). There is no undervoltage lockout. The device will shutdown gracefully once it runs out of headroom.
where: IAVG = ( 295.5A DC) - [4.5A (1 - DC)] IAVG = (300A DC) - 4.5A DC = PWM Duty Cycle Sleep State This device will enter into a low current mode (<275A) when CTL lead is brought to less than 0.5V. All functions are disabled in this mode, except for the regulator.
Reverse Battery The CS7054 will not survive a reverse battery condition. Therefore, a series diode is required between the battery and the VCC lead. Load Dump VCC is internally clamped to 30V. It is recommended that a 511/2 resistor, (RS) is placed in series with VCC to limit the current flow into the IC in the event of a 40V peak transient condition.
Inhibit When the inhibit voltage is greater than 2.5V the internal latch is set and the external MOSFET will be turned off for the remainder of the oscillator cycle. The latch is then reset at the start of the next cycle.
5
CS7054
Package Specification
PACKAGE DIMENSIONS IN mm (INCHES) PACKAGE THERMAL DATA
D Lead Count 14L PDIP Metric Max Min 19.69 18.67 English Max Min .775 .735
Thermal Data RQJC RQJA typ typ
14L PDIP 48 85
uC/W uC/W
Plastic DIP (N); 300 mil wide
7.11 (.280) 6.10 (.240)
8.26 (.325) 7.62 (.300) 3.68 (.145) 2.92 (.115)
1.77 (.070) 1.14 (.045)
2.54 (.100) BSC
.356 (.014) .203 (.008)
0.39 (.015) MIN. .558 (.022) .356 (.014) Some 8 and 16 lead packages may have 1/2 lead at the end of the package. All specs are the same.
REF: JEDEC MS-001
D
Ordering Information
Part Number CS7054YN14
Description 14 Lead PDIP
Cherry Semiconductor Corporation reserves the right to make changes to the specifications without notice. Please contact Cherry Semiconductor Corporation for the latest available information. 6
(c) 1999 Cherry Semiconductor Corporation
Rev. 4/21/99

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