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DS2227 Flexible NV SRAM Stik
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FEATURES
Flexibly organized as 128k x 32, 256k x 16, or 512k x 8 bits Data retention >10 years in the absence of VCC Nonvolatile circuitry transparent to and independent from host system Automatic write protection circuitry safeguards against data loss Separate chip enables allow access by byte, word, or long word Fast access times: 70 ns, 100 ns, or 120 ns Unlimited write cycles Read cycle time equals write cycle time Employs popular JEDEC standard 72-position SIMM connection scheme Lithium energy source is electrically disconnected to retain freshness until power is applied for the first time
PIN ASSIGNMENT
1 1M SRAM 1M SRAM 1M SRAM 1M SRAM 72-Pin SIP STIK 72
DESCRIPTION
The DS2227 Flexible NV SRAM Stik is a self-contained 4,194,304-bit nonvolatile static RAM which can be flexibly organized as 128k x 32 bits, 256k x 16 bits, or 512k x 8 bits. The nonvolatile memory contains all necessary control circuitry and lithium energy sources to maintain data integrity in the absence of power for more than 10 years. The DS2227 employs the popular JEDEC standard 72-position SIMM connection scheme requiring no additional circuitry.
OPERATION
The DS2227 Flexible NV SRAM Stik is used like any standard static RAM. All nonvolatile circuitry is transparent to the user. The flexibility of the part is achieved by providing separate read, write, and chip 1 of 10 112099
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select pins for each of the four banks of onboard memories (see Figure 1). For operation as a 512k x 8 NV SRAM Stik, tie all data lines from each bank together (i.e., all D0s together, all D1s together, etc.). Read enables and write enables are also tied together. For operation as a 256k x 16 NV SRAM Stik, tie the data lines from two banks together. Chip enables, read enables, and write enables from these banks are also tied together. Connection to the DS2227 is made by using an industry-standard, 72-position SIMM socket DS9072-72V (AMP part number 821824-8). These SIMM sockets are also available in perpendicular, inclined, or parallel mount, depending on the height available. See the DS907x SipStikTM connectors available from Dallas Semiconductor.
READ MODE
The DS2227 executes a read cycle whenever WE (Write Enable) is inactive (high) and CE (Chip Enable) and OE (Output Enable) are active (low). The unique address specified by the 17 address inputs (A0 - A16) defines which byte of data is to be accessed. Valid data will be available to the eight data I/O pins within tACC (access time) after the last address input signal is stable, providing that CE and OE access times are also satisfied. If OE and CE times are not satisfied, then data access must be measured from the later occurring signal ( CE or OE ) and the limiting parameter is either tCO for CE or tOE for OE rather than address access.
WRITE MODE
The DS2227 is in the write mode whenever both WE and CE signals are in the active (low) state after address inputs are stable. The latter occurring falling edge of CE or WE will determine the start of the write cycle. The write cycle is terminated by the earlier rising edge of CE or WE . All address inputs must be kept valid throughout the write cycle. WE must return to the high state for a minimum recovery time (tWR) before another cycle can be initiated. The OE control signal should be kept inactive (high) during write cycles to avoid bus contention. However, if the output bus has been enabled ( CE and OE active) then WE will disable the outputs to tODW from its falling edge.
DATA RETENTION MODE
The DS2227 provides fully functional capability for VCC greater than 4.5 volts and guarantees write protection for VCC less than 4.25 volts. Data is maintained in the absence of VCC without any additional support circuitry. The DS2227 constantly monitors VCC. Should the supply voltage decay, the NV SRAM automatically write-protects itself, all inputs become "don't care" and all outputs become high impedance. As VCC falls below approximately 3.0 volts, a power switching circuit connects a lithium energy source to RAM to retain data. During power-up, when VCC rises above approximately 3.0 volts, the power switching circuit connects the external VCC to RAM and disconnects the lithium energy source. Normal RAM operation can resume after VCC exceeds 4.5 volts. The DS2227 checks lithium status to warn of potential data loss. Each time that VCC power is restored to the DS2227, the battery voltage is checked with a precision comparator. If the battery supply is less than 2.0 volts, the second memory access to the device is inhibited. Battery status can, therefore, be determined by a three-step process. First, a read cycle is performed to any location in memory, in order to save the contents of that location. A subsequent write cycle can then be executed to the same memory location, altering data. If the next read cycle fails to verify the written data, then the battery voltage is less than 2.0V and data is in danger of being corrupted. The DS2227 also provides battery redundancy. In many applications data integrity is paramount. The DS2227 provides two batteries for each SRAM and an internal isolation switch to select between them. During battery backup, the battery with the highest voltage is selected for use. If one battery fails, the other automatically takes over. The switch between batteries is transparent to the user. 2 of 10
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PIN DESCRIPTION Table 1
PIN SIGNAL NAME 1 VCC 2 1-D0 3 1-D1 4 1-D2 5 1-D3 6 1-D4 7 1-D5 8 1-D6 9 1-D7 10 NC 11 1- CE 12 1- OE 13 1- WE 14 2-D0 15 2-D1 16 2-D2 17 2-D3 18 2-D4 19 2-D5 20 2-D6 21 2-D7 22 NC 23 2- CE 24 2- OE 25 2- WE 26 3-D0 27 3-D1 28 3-D2 29 3-D3 30 3-D4 31 3-D5 32 3-D6 33 3-D7 34 NC 35 3- CE 36 3- OE 37 3- WE NOTE: Leave all pins marked as NC unconnected. PIN 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 SIGNAL NAME 4-D0 4-D1 4-D2 4-D3 4-D4 4-D5 4-D6 4-D7 NC 4- CE 4- OE 4- WE GND VCC A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 NC NC NC GND
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SCHEMATIC (1 CELL) Figure 1
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ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground Operating Temperature Storage Temperature -0.3V to +7.0V 0C to 70C -40 to +85C
* This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
PARAMETER Power Supply Voltage Input High Voltage Input Low Voltage SYMBOL VCC VIH VIL MIN 4.5 2.2 0 TYP 5.0 MAX 5.5 VCC +0.8
(0C to 70C)
UNITS V V V NOTES
DC ELECTRICAL CHARACTERISTICS
PARAMETER Input Leakage Current I/O Leakage Current Output Current @ 2.4V Output Current @ 0.4V Operating Current Write Protection Voltage SYMBOL IIL ILO IOH IOL ICC VTP MIN -1.0 -5.0 -1.0 2.0 4.25
(0C to 70C; VCC = 5V 10%)
TYP MAX +1.0 +5.0 3.0 60 4.37 UNITS A A mA mA mA V NOTES
280 4.5
CAPACITANCE
PARAMETER Input Capacitance Output Capacitance SYMBOL CIN COUT MIN TYP 20 5 MAX 40 10 pF pF
(TA = 25C)
UNITS NOTES
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AC ELECTRICAL CHARACTERISTICS
DS2227-70 PARAMETER Read Cycle Time Access Time OE to Output Valid CE to Output Valid OE or CE to Output Active Output High Z from Deselection Output Hold from Address Change Write Cycle Time Write Pulse Width Address Setup Time Write Recovery Time Output High Z from WE Output Active from WE Data Setup Time Data Hold Time from WE SYMBOL MIN MAX MIN MAX MIN MAX tRC tACC tOE tCO tCOE tOD tOH tWC tWP tAW tWR tODW tOEW tDS tDH 5 30 20 5 70 55 0 20 25 5 40 20 5 25 5 100 75 0 20 35 5 50 20 70 70 35 70 5 35 5 120 90 0 20 40 100 100 50 100 5 40 120 120 60 120 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 10 10 10 10 10 10 10 10 3,10 10 10 10 8,10 4,10 4,5,10 DS2227-100 DS2227-120 UNITS NOTES
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READ CYCLE
SEE NOTE 1
WRITE CYCLE 1
SEE NOTES 2, 3, 4, 5, 6, 7 AND 8
WRITE CYCLE 2
SEE NOTES 2, 3, 4, 5, 6, 7 AND 8
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POWER-UP/POWER-DOWN CONDITION
POWER-DOWN/POWER-UP TIMING
PARAMETER at VIH Before Power-down VCC Slew from 4.5V to 4.25V ( CE at VIH ) VCC Slew from 0V to 4.5V ( CE at VIH ) CE at VIH after Power-up
CE
SYMBOL tPD tF tR tREC
MIN 0 300 0 2
TYP
MAX
UNITS s s s
NOTES
80
125
ms
(TA = 25C)
PARAMETER Expected Data Retention SYMBOL tDR MIN 10 TYP MAX UNITS years NOTES
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NOTES:
1. 2. 3. 4. 5. 6. 7. 8. 9.
WE
is high for a read cycle.
OE = VIH or VIL. If OE = VIH during write cycle, the output buffers remain in a high impedance state.
tWP is specified as the logical AND of CE and WE . tDH, tDS are measured from the earlier of CE or WE going high. tDH is measured from WE going high. If CE is used to terminate the write cycle then tDH = 20 ns. If the CE low transition occurs simultaneously with or later than the WE low transition, the output buffers remain in a high impedance state in this period. If the CE high transition occurs prior to or simultaneously with the WE high transition, the output buffers remain in a high impedance state in this period. If the WE is low or the WE low transition occurs prior to or simultaneously with the CE low transition, the output buffers remain in a high impedance state in this period. Each DS2227 is marked with a 4-digit date code AABB. AA designates the year of manufacture. BB designates the week of manufacture. The minimum expected tDR is defined as starting at the date of manufacture. Timings are valid only when CE is tied low.
10.
DC TEST CONDITIONS
Outputs Open Cycle = 200 ns All Voltages are Referenced to Ground
AC TEST CONDITIONS
Output Load: 100 pF + 1TTL gate Input Pulse Levels: 0 - 3.0 V Timing Measurements Reference Levels: Input - 1.5V Output - 1.5V Input Pulse Rise and Fall Times: 5 ns
ORDERING INFORMATION
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DS2227 72-PIN SIP STIK
DIM A B C D E F G H I J K L M N O P
NOTE: DIMENSIONS ARE SHOWN IN INCHES.
72-PIN MIN MAX 4.245 4.255 3.979 3.989 0.845 0.855 0.395 0.405 0.245 0.255 0.050 BASIC 0.075 0.085 0.245 0.255 1.750 BASIC 0.120 0.130 2.120 2.130 2.245 2.255 0.057 0.067 0.140 0.140 0.054
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