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DS91D176/DS91C176 Multipoint-LVDS (M-LVDS) Transceivers June 2006 DS91D176/DS91C176 Multipoint-LVDS (M-LVDS) Transceivers General Description The DS91C176 and DS91D176 are high-speed M-LVDS differential transceivers designed for multipoint applications with multiple drivers or receivers. Multipoint LVDS (M-LVDS) is a new bus interface standard (TIA/EIA-899) based on LVDS but including several enhancements to improve multipoint performance. M-LVDS devices have superior drive capability and can support up to 32 loads. Along with increased drive, M-LVDS devices are required to have a controlled edge rate to minimize reflections and EMI. The 1 nSec minimum edge rate is tolerant of stub lengths up to 2 inches in length. M-LVDS devices also have a very large common mode range for additional noise margin in heavily loaded and noisy backplane environments. The DS91C176/DS91D176 are half-duplex transceivers that accept LVTTL/LVCMOS signals at the driver inputs and convert them to differential M-LVDS signal levels. The receiver inputs accept low voltage differential signals (LVDS, B-LVDS, M-LVDS, LV-PECL) and convert them to 3V LVCMOS signals. The DS91D176 has a M-LVDS type 1 receiver input with no offset. The DS91C176 receiver contains an M-LVDS type 2 failsafe circuit with an internal 100 mV offset that provides a LOW output for both short and open input conditions. Features n n n n n n n n n n Meets TIA/EIA-899 M-LVDS Standard Capable of driving 32 LVDS loads Controlled Edge Rates Tolerant to Stubs Wide Common Mode for Increased Noise Immunity DS91D176 has type 1 receiver input DS91C176 has type 2 receiver with fail-safe Up to 200 Mbps operation Industrial temperature range Single 3.3V supply 8-lead SOIC package Typical Application in AdvancedTCA Clock Distribution 20024630 (c) 2006 National Semiconductor Corporation DS200246 www.national.com DS91D176/DS91C176 Connection and Logic Diagram 20024601 Top View Order Number DS91D176TMA, DS91C176TMA See NS Package Number M08A Ordering Information Order Number DS91D176TMA DS91C176TMA Receiver Input type 1 type 2 Function Data (0V threshold receiver) Control (100 mV offset fail-safe receiver) Package Type SOIC/M08A SOIC/M08A M-LVDS Receiver Types The EIA/TIA-899 M-LVDS standard specifies two different types of receiver input stages. A type 1 receiver has a conventional threshold that is centered at the midpoint of the input amplitude, VID/2. A type 2 receiver has a built in offset that is 100mV greater then VID/2. The type 2 receiver offset acts as a failsafe circuit where open or short circuits at the input will always result in the output stage being driven to a low logic state. 20024640 FIGURE 1. M-LVDS Receiver Input Thresholds www.national.com 2 DS91D176/DS91C176 Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage, VCC Control Input Voltages Driver Input Voltage Driver Output Voltages Receiver Input Voltages Receiver Output Voltage SOIC Package Derate SOIC Package Thermal Resistance JA JC Maximum Junction Temperature Storage Temperature Range Lead Temperature (Soldering, 4 seconds) -0.3V to +4V -0.3V to (VCC + 0.3V) -0.3V to (VCC + 0.3V) -1.8V to +4.1V -1.8V to +4.1V -0.3V to (VCC + 0.3V) 833 mW 6.67 mW/C above +25C 150C/W 63C/W 150C -65C to +150C 260C ESD Ratings: (HBM 1.5k, 100pF) (EIAJ 0, 200pF) (CDM 0, 0pF) 8 kV 1000 V 250 V Recommended Operating Conditions Min Supply Voltage, VCC Voltage at Any Bus Terminal (Separate or Common-Mode) Differential Input Voltage VID LVTTL Input Voltage High VIH LVTTL Input Voltage Low VIL Operating Free Air Temperature TA -40 +25 +85 C 2.0 0 2.4 VCC 0.8 V V V 3.0 -1.4 Typ Max Units 3.3 3.6 +3.8 V V Maximum Package Power Dissipation at +25C Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. (Notes 2, 3, 4, 8) Symbol M-LVDS Driver |VAB| VAB VOS(SS) Differential output voltage magnitude Change in differential output voltage magnitude between logic states Steady-state common-mode output voltage RL = 50, CL = 5pF Figure 2 and Figure 4 RL = 50, CL = 5pF Figure 2 and Figure 3 (VOS(PP) @ 500KHz clock) 0 0 RL = 50, CL = 5pF, CD = 0.5pF Figure 7 and Figure 8 (Note 9) -0.2VSS VIH = 2.0V VIL = 0.8V IIN = -18mA Figure 6 See Function Tables Type 1 Type 2 VIT- VOH VOL IOZ IOSR Negative-going differential input voltage threshold See Function Tables High-level output voltage (LVTTL output) Low-level output voltage (LVTTL output) TRI-STATE output current Short-circuit receiver output current (LVTTL output) IOH = -8mA IOL = 8mA VO = 0V or 3.6V VO = 0V -10 -48 Type 1 Type 2 -50 50 2.4 -15 -15 -1.5 -43 20 94 20 94 2.7 0.28 0.4 10 -90 43 50 150 480 -50 0.3 0 135 2.4 2.4 1.2VSS 15 15 0 1.8 650 +50 2.1 +50 mV mV V mV mV V V V V A A V mA mV mV mV mV V V A mA Parameter Conditions Min Typ Max Units |VOS(SS)| Change in steady-state common-mode output voltage between logic states VOS(PP) VA(OC) VB(OC) VP(H) VP(L) IIH IIL VIKL IOS VIT+ Peak-to-peak common-mode output voltage Maximum steady-state open-circuit output voltage Voltage overshoot, low-to-high level output Voltage overshoot, high-to-low level output High-level input current (LVTTL inputs) Low-level input current (LVTTL inputs) Input Clamp Voltage (LVTTL inputs) Differential short-circuit output current Positive-going differential input voltage threshold Maximum steady-state open-circuit output voltage Figure 5 M-LVDS Receiver 3 www.national.com DS91D176/DS91C176 Electrical Characteristics Symbol IA Parameter Transceiver input/output current M-LVDS Bus (Input and Output) Pins (Continued) Over recommended operating supply and temperature ranges unless otherwise specified. (Notes 2, 3, 4, 8) Conditions VA = 3.8V, VB = 1.2V VA = 0V or 2.4V, VB = 1.2V VA = -1.4V, VB = 1.2V -20 -32 32 -20 -32 -4 +4 32 -20 -32 32 -20 -32 -4 9 9 5.7 1.0 +4 +20 +20 +20 Min Typ Max 32 +20 Units A A A A A A A A A A A A A A pF pF pF IB Transceiver input/output current VB = 3.8V, VA = 1.2V VB = 0V or 2.4V, VA = 1.2V VB = -1.4V, VA = 1.2V IAB IA(OFF) Transceiver input/output differential current (IA - IB) Transceiver input/output power-off current VA = VB, -1.4V V 3.8V VA = 3.8V, VB = 1.2V, DE = VCC = 1.5V VA = 0V or 2.4V, VB = 1.2V, DE = VCC = 1.5V VA = -1.4V, VB = 1.2V, DE = VCC = 1.5V IB(OFF) Transceiver input/output power-off current VB = 3.8V, VA = 1.2V, DE = VCC = 1.5V VB = 0V or 2.4V, VA = 1.2V, DE = VCC = 1.5V VB = -1.4V, VA = 1.2V, DE = VCC = 1.5V IAB(OFF) CA CB CAB CA/B Transceiver input/output power-off differential current (IA(OFF) - IB(OFF)) Transceiver input/output capacitance Transceiver input/output capacitance Transceiver input/output differential capacitance Transceiver input/output capacitance balance (CA/CB) Driver Supply Current TRI-STATE Supply Current Receiver Supply Current VA = VB, -1.4V V 3.8V, VCC = 1.5V, DE = 1.5V VCC = OPEN SUPPLY CURRENT (VCC) ICCD ICCZ ICCR RL = 50, DE = VCC, RE = VCC DE = GND, RE = VCC DE = GND, RE = GND 20 6 14 29.5 9.0 18.5 mA mA mA www.national.com 4 DS91D176/DS91C176 Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. (Notes 3, 8) Symbol DRIVER AC SPECIFICATION tPLH tPHL tSKD1 (tsk(p)) tSKD3 tTLH (tr) tTHL (tf) tPZH tPZL tPLZ tPHZ tJIT fMAX tPLH tPHL tSKD1 (tsk(p)) tSKD3 tTLH (tr) tTHL (tf) tPZH tPZL tPLZ tPHZ fMAX Differential Propagation Delay Low to High Differential Propagation Delay High to Low Pulse Skew |tPLHD - tPHLD| (Notes 5, 9) Part-to-Part Skew (Notes 6, 9) Rise Time (Note 9) Fall Time (Note 9) Enable Time (Z to Active High) Enable Time (Z to Active Low ) Disable Time (Active Low to Z) Disable Time (Active High to Z) Random Jitter, RJ (Note 9) Maximum Data Rate Propagation Delay Low to High Propagation Delay High to Low Pulse Skew |tPLHD - tPHLD| (Notes 5, 9) Part-to-Part Skew (Notes 6, 9) Rise Time (Note 9) Fall Time (Note 9) Enable Time (Z to Active High) Enable Time (Z to Active Low) Disable Time (Active Low to Z) Disable Time (Active High to Z) Maximum Data Rate 200 RL = 500, CL = 15 pF Figure 14 and Figure 15 0.5 0.5 1.2 1.2 CL = 15 pF Figures 11, 12 and Figure 13 100 MHz Clock Pattern (Note 7) 200 2.0 2.0 4.7 5.3 0.6 7.5 7.5 1.7 1.3 2.5 2.5 10 10 10 10 2.5 RL = 50, CL = 5 pF, CD = 0.5 pF Figure 9 and Figure 10 1.0 1.0 1.8 1.8 RL = 50, CL = 5 pF, CD = 0.5 pF Figure 7 and Figure 8 1.3 1.3 3.4 3.1 300 5.0 5.0 420 1.3 3.0 3.0 8 8 8 8 5.5 ns ns ps ns ns ns ns ns ns ns psrms Mbps ns ns ns ns ns ns ns ns ns ns Mbps Parameter Conditions Min Typ Max Units RECEIVER AC SPECIFICATION Note 1: "Absolute Maximum Ratings" are those beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should be operated at these limits. The tables of "Electrical Characteristics" provide conditions for actual device operation. Note 2: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground unless otherwise specified. Note 3: All typicals are given for VCC = 3.3V and TA = 25C. Note 4: The algebraic convention, in which the least positive (most negative) limit is designated as minimum, is used in this datasheet. Note 5: tSKD1, |tPLHD - tPHLD|, is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edge of the same channel. Note 6: tSKD3, Part-to-Part Skew, is defined as the difference between the minimum and maximum specified differential propagation delays. This specification applies to devices at the same VCC and within 5C of each other within the operating temperature range. Note 7: Stimulus and fixture Jitter has been subtracted. Note 8: CL includes fixture capacitance and CD includes probe capacitance. Note 9: Not production tested. Guaranteed by a statistical analysis on a sample basis at the time of characterization. 5 www.national.com DS91D176/DS91C176 Test Circuits and Waveforms 20024614 FIGURE 2. Differential Driver Test Circuit 20024624 FIGURE 3. Differential Driver Waveforms 20024622 FIGURE 4. Differential Driver Full Load Test Circuit 20024612 FIGURE 5. Differential Driver DC Open Test Circuit www.national.com 6 DS91D176/DS91C176 Test Circuits and Waveforms (Continued) 20024625 FIGURE 6. Differential Driver Short-Circuit Test Circuit 20024616 FIGURE 7. Driver Propagation Delay and Transition Time Test Circuit 20024618 FIGURE 8. Driver Propagation Delays and Transition Time Waveforms 7 www.national.com DS91D176/DS91C176 Test Circuits and Waveforms (Continued) 20024619 FIGURE 9. Driver TRI-STATE Delay Test Circuit 20024621 FIGURE 10. Driver TRI-STATE Delay Waveforms 20024615 FIGURE 11. Receiver Propagation Delay and Transition Time Test Circuit www.national.com 8 DS91D176/DS91C176 Test Circuits and Waveforms (Continued) 20024617 FIGURE 12. Type 1 Receiver Propagation Delay and Transition Time Waveforms 20024623 FIGURE 13. Type 2 Receiver Propagation Delay and Transition Time Waveforms 20024613 FIGURE 14. Receiver TRI-STATE Delay Test Circuit 9 www.national.com DS91D176/DS91C176 Test Circuits and Waveforms (Continued) 20024620 FIGURE 15. Receiver TRI-STATE Delay Waveforms www.national.com 10 DS91D176/DS91C176 Function Tables DS91D176/DS91C176 Transmitting Inputs RE X X X DE 2.0V 2.0V 0.8V D 2.0V 0.8V X Outputs B L H Z A H L Z X -- Don't care condition Z -- High impedance state DS91D176 Receiving Inputs RE 0.8V 0.8V 0.8V 2.0V DE 0.8V 0.8V 0.8V 0.8V A-B +0.05V -0.05V 0V X Output R H L X Z RE 0.8V 0.8V 0.8V 2.0V DS91C176 Receiving Inputs DE 0.8V 0.8V 0.8V 0.8V A-B +0.15V +0.05V 0V X Output R H L L Z X -- Don't care condition Z -- High impedance state X -- Don't care condition Z -- High impedance state DS91D176 Receiver Input Threshold Test Voltages Applied Voltages VIA 2.400V 0.000V 3.800V 3.750V -1.400V -1.350V VIB 0.000V 2.400V 3.750V 3.800V -1.350V -1.400V Resulting Differential Input Voltage VID 2.400V -2.400V 0.050V -0.050V -0.050V 0.050V Resulting Common-Mode Input Voltage VIC 1.200V 1.200V 3.775V 3.775V -1.375V -1.375V Receiver Output R H L H L H L H -- High Level L -- Low Level Output state assumes that the receiver is enabled (RE = L) DS91C176 Receiver Input Threshold Test Voltages Applied Voltages VIA 2.400V 0.000V 3.800V 3.800V -1.250V -1.350V VIB 0.000V 2.400V 3.650V 3.750V -1.400V -1.400V Resulting Differential Input Voltage VID 2.400V -2.400V 0.150V 0.050V 0.150V 0.050V Resulting Common-Mode Input Voltage VIC 1.200V 1.200V 3.725V 3.775V -1.325V -1.375V Receiver Output R H L H L H L H -- High Level L -- Low Level Output state assumes that the receiver is enabled (RE = L) 11 www.national.com DS91D176/DS91C176 Pin Descriptions Pin No. 1 2 3 4 5 6 7 8 Name R RE DE D GND A B VCC Receiver output pin Receiver enable pin: When RE is high, the receiver is disabled. When RE is low or open, the receiver is enabled. Driver enable pin: When DE is low, the driver is disabled. When DE is high, the driver is enabled. Driver input pin Ground pin Non-inverting driver output pin/Non-inverting receiver input pin Inverting driver output pin/Inverting receiver input pin Power supply pin, +3.3V 0.3V Description Application Information STUB LENGTH Stub lengths should be kept to a minimum. For a general approximation, if the electrical length of a trace is greater than 1/5 of the transition edge, then the trace is considered a transmission line. If the velocity equals 160 ps per inch for a typical loaded backplane, then the maximum stub length is 312 ps/160 ps/inch or 1.95 inches (approximately 2 inches). To determine the maximum stub for your backplane, the propagation velocity for the backplane is required (refer to application notes AN-905 and AN-808). Typical Performance Characteristics Supply Current vs. Frequency Output VOD vs. Load Resistance 20024662 20024663 Supply Current measured using a clock pattern with driver terminated to 50ohms . VCC = 3.3V, TA = +25C. VCC = 3.3V, TA = +25C FIGURE 16. SOIC performance Characteristics www.national.com 12 DS91D176/DS91C176 Multipoint-LVDS (M-LVDS) Transceivers Physical Dimensions inches (millimeters) unless otherwise noted Order Number DS91D176TMA, DS91C176TMA See NS package Number M08A National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. For the most current product information visit us at www.national.com. LIFE SUPPORT POLICY NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. BANNED SUBSTANCE COMPLIANCE National Semiconductor follows the provisions of the Product Stewardship Guide for Customers (CSP-9-111C2) and Banned Substances and Materials of Interest Specification (CSP-9-111S2) for regulatory environmental compliance. Details may be found at: www.national.com/quality/green. Lead free products are RoHS compliant. National Semiconductor Americas Customer Support Center Email: new.feedback@nsc.com Tel: 1-800-272-9959 www.national.com National Semiconductor Europe Customer Support Center Fax: +49 (0) 180-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Francais Tel: +33 (0) 1 41 91 8790 National Semiconductor Asia Pacific Customer Support Center Email: ap.support@nsc.com National Semiconductor Japan Customer Support Center Fax: 81-3-5639-7507 Email: jpn.feedback@nsc.com Tel: 81-3-5639-7560 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. |
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