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INTEGRATED CIRCUITS
DATA SHEET
74LVC1G74 Single D-type flip-flop with set and reset; positive edge trigger
Product specification Supersedes data of 2004 Sep 09 2005 Feb 01
Philips Semiconductors
Product specification
Single D-type flip-flop with set and reset; positive edge trigger
FEATURES * Wide supply voltage range from 1.65 V to 5.5 V * 5 V tolerant inputs for interfacing with 5 V logic * High noise immunity * Complies with JEDEC standard: - JESD8-7 (1.65 V to 1.95 V) - JESD8-5 (2.3 V to 2.7 V) - JESD8B/JESD36 (2.7 V to 3.6 V). * 24 mA output drive (VCC = 3.0 V) * ESD protection: - HBM EIA/JESD22-A114-B exceeds 2000 V - MM EIA/JESD22-A115-A exceeds 200 V. * CMOS low power consumption * Latch-up performance exceeds 250 mA * Direct interface with TTL levels * Inputs accept voltages up to 5 V * Multiple package options * Specified from -40 C to +85 C and -40 C to +125 C. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 C; tr = tf 2.5 ns. SYMBOL tPHL/tPLH CP to Q, Q SD to Q, Q RD to Q, Q fmax CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD x VCC2 x fi x N + (CL x VCC2 x fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts; N = number of inputs switching; (CL x VCC2 x fo) = sum of the outputs. 2. The condition is VI = GND to VCC. maximum clock frequency input capacitance power dissipation capacitance VCC = 3.3 V; notes 1 and 2 PARAMETER propagation delay CL = 50 pF; VCC = 3.3 V CL = 50 pF; VCC = 3.3 V CL = 50 pF; VCC = 3.3 V CL = 50 pF; VCC = 3.3 V 3.5 3.0 3.0 280 4.0 15 CONDITIONS DESCRIPTION
74LVC1G74
The 74LVC1G74 is a high-performance, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. The 74LVC1G74 is a single positive edge triggered D-type flip-flop with individual data (D) inputs, clock (CP) inputs, set (SD) and (RD) inputs, and complementary Q and Q outputs. This device is fully specified for partial power down applications using Ioff. The Ioff circuitry disables the output, preventing damaging backflow current through the device when it is powered down. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition, for predictable operation. Schmitt-trigger action at all inputs makes the circuit highly tolerant to slower input rise and fall times.
TYPICAL ns ns ns
UNIT
MHz pF pF
2005 Feb 01
2
Philips Semiconductors
Product specification
Single D-type flip-flop with set and reset; positive edge trigger
FUNCTION TABLES Table 1 Asynchronous operation. See note 1. INPUT SD L H L Table 2 RD H L L CP X X X D X X X Q H L H
74LVC1G74
OUTPUT Q L H H
Synchronous operation. See note 1. INPUT SD H H RD H H CP D L H Qn+1 L H OUTPUT Qn+1 H L
Note to Tables 1 and 2 1. H = HIGH voltage level; L = LOW voltage level; X = don't care; = LOW-to-HIGH CP transition; Qn+1 = state after the next LOW-to-HIGH CP transition. ORDERING INFORMATION PACKAGE TYPE NUMBER 74LVC1G74DP 74LVC1G74DC 74LVC1G74GT PINNING SYMBOL CP D Q GND Q RD SD VCC PIN 1 2 3 4 5 6 7 8 data input complement flip-flop output ground (0 V) true flip-flop output asynchronous reset-direct input (active LOW) asynchronous set-direct input (active LOW) supply voltage DESCRIPTION clock input (LOW-to-HIGH, edge-triggered) TEMPERATURE RANGE -40 C to +125 C -40 C to +125 C -40 C to +125 C PINS 8 8 8 PACKAGE TSSOP8 VSSOP8 XSON8 MATERIAL plastic plastic plastic CODE SOT505-2 SOT765-1 SOT833-1 MARKING V74 V74 V74
2005 Feb 01
3
Philips Semiconductors
Product specification
Single D-type flip-flop with set and reset; positive edge trigger
74LVC1G74
74
CP 1 8 VCC
CP D Q GND
1 2 3 4
001aab659
8 7
VCC SD RD Q
D
2
7
SD
74
6 5
Q
3
6
RD
GND
4
5
Q
001aab658
Transparent top view
Fig.1 Pin configuration TSSOP8 and VSSOP8.
Fig.2 Pin configuration XSON8.
handbook, halfpage
7 SD 2 1 D CP SD D CP FF Q RD RD 6
MNB139
Q
Q
5
handbook, halfpage
7 1 2
S C1 1D R
MNB140
5
Q
3
6
3
Fig.3 Logic symbol.
Fig.4 IEC logic symbol.
2005 Feb 01
4
Philips Semiconductors
Product specification
Single D-type flip-flop with set and reset; positive edge trigger
74LVC1G74
handbook, full pagewidth
Q C C
C C D C RD
C C Q C
SD
MNA421
CP
C C
Fig.5 Logic diagram.
2005 Feb 01
5
Philips Semiconductors
Product specification
Single D-type flip-flop with set and reset; positive edge trigger
RECOMMENDED OPERATING CONDITIONS SYMBOL VCC VI VO Tamb tr, tf PARAMETER supply voltage input voltage output voltage ambient temperature input rise and fall times VCC = 1.65 V to 2.7 V VCC = 2.7 V to 5.5 V active mode VCC = 0 V; Power-down mode CONDITIONS 0 0 0 -40 0 0 MIN. 1.65
74LVC1G74
MAX. 5.5 5.5 VCC 5.5 +125 20 10 V V V V
UNIT
C ns/V ns/V
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V). SYMBOL VCC IIK VI IOK VO IO ICC, IGND Tstg Ptot Notes 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation. PARAMETER supply voltage input diode current input voltage output diode current output voltage output source or sink current VCC or GND current storage temperature power dissipation Tamb = -40 C to +125 C VI < 0 V note 1 VO > VCC or VO < 0 V active mode; notes 1 and 2 VO = 0 V to VCC CONDITIONS - -0.5 - -0.5 - - -65 - MIN. -0.5 MAX. +6.5 -50 +6.5 50 +6.5 50 100 +150 250 V mA V mA V mA mA C mW UNIT
VCC + 0.5 V
Power-down mode; notes 1 and 2 -0.5
2005 Feb 01
6
Philips Semiconductors
Product specification
Single D-type flip-flop with set and reset; positive edge trigger
DC CHARACTERISTICS At recommended operating conditions; voltages are referenced to GND (ground = 0 V). TEST CONDITIONS SYMBOL PARAMETER OTHER Tamb = -40 C to +85 C; note 1 VIH HIGH-level input voltage 1.65 to 1.95 2.3 to 2.7 2.7 to 3.6 4.5 to 5.5 VIL LOW-level input voltage 1.65 to 1.95 2.3 to 2.7 2.7 to 3.6 4.5 to 5.5 VOH HIGH-level output voltage VI = VIH or VIL IO = -100 A IO = -4 mA IO = -8 mA IO = -12 mA IO = -24 mA IO = -32 mA VOL LOW-level output voltage VI = VIH or VIL IO = 100 A IO = 4 mA IO = 8 mA IO = 12 mA IO = 24 mA IO = 32 mA ILI Ioff ICC ICC input leakage current power OFF leakage current quiescent supply current additional quiescent supply current per pin VI = 5.5 V or GND VI or VO = 5.5 V VI = VCC or GND; IO = 0 A VI = VCC - 0.6 V; IO = 0 A 1.65 to 5.5 1.65 2.3 2.7 3.0 4.5 5.5 0 5.5 2.3 to 5.5 - - - - - - - - - - 0.07 0.12 0.17 0.33 0.39 0.1 0.1 0.1 5 1.65 to 5.5 1.65 2.3 2.7 3.0 4.5 VCC - 0.1 1.2 1.9 2.2 2.3 3.8 - 1.54 2.15 2.50 2.62 4.11 0.65 x VCC - 1.7 2.0 0.7 x VCC - - - - - - - - - - - VCC (V) MIN. TYP.
74LVC1G74
MAX.
UNIT
- - - - 0.7 0.8 0.3 x VCC - - - - - - 0.10 0.45 0.30 0.40 0.55 0.55 5 10 10 500
V V V V V V V V V V V V V V V V V V V A A A A
0.35 x VCC V
2005 Feb 01
7
Philips Semiconductors
Product specification
Single D-type flip-flop with set and reset; positive edge trigger
TEST CONDITIONS SYMBOL PARAMETER OTHER Tamb = -40 C to +125 C VIH HIGH-level input voltage 1.65 to 1.95 2.3 to 2.7 2.7 to 3.6 4.5 to 5.5 VIL LOW-level input voltage 1.65 to 1.95 2.3 to 2.7 2.7 to 3.6 4.5 to 5.5 VOH HIGH-level output voltage VI = VIH or VIL IO = -100 A IO = -4 mA IO = -8 mA IO = -12 mA IO = -24 mA IO = -32 mA VOL LOW-level output voltage VI = VIH or VIL IO = 100 A IO = 4 mA IO = 8 mA IO = 12 mA IO = 24 mA IO = 32 mA ILI Ioff ICC ICC Note 1. All typical values are measured at Tamb = 25 C. input leakage current power OFF leakage current quiescent supply current additional quiescent supply current per pin VI = 5.5 V or GND VI or VO = 5.5 V VI = VCC or GND; IO = 0 VI = VCC - 0.6 V; IO = 0 1.65 to 5.5 1.65 2.3 2.7 3.0 4.5 5.5 0 5.5 2.3 to 5.5 - - - - - - - - - - - - - - - - - - - - 1.65 to 5.5 1.65 2.3 2.7 3.0 4.5 VCC - 0.1 0.95 1.7 1.9 2.0 3.4 - - - - - - 0.65 x VCC - 1.7 2.0 0.7 x VCC - - - - - - - - - - - VCC (V) MIN. TYP.
74LVC1G74
MAX.
UNIT
- - - - 0.7 0.8 0.3 x VCC - - - - - - 0.10 0.70 0.45 0.60 0.80 0.80 20 20 40 5000
V V V V V V V V V V V V V V V V V V V A A A A
0.35 x VCC V
2005 Feb 01
8
Philips Semiconductors
Product specification
Single D-type flip-flop with set and reset; positive edge trigger
AC CHARACTERISTICS GND = 0 V. TEST CONDITIONS SYMBOL PARAMETER WAVEFORMS Tamb = -40 C to +85 C; note 1 tPHL/tPLH propagation delay CP to Q, Q see Figs 6 and 8 1.65 to 1.95 2.3 to 2.7 2.7 3.0 to 3.6 4.5 to 5.5 propagation delay SD to Q, Q see Figs 7 and 8 1.65 to 1.95 2.3 to 2.7 2.7 3.0 to 3.6 4.5 to 5.5 propagation delay RD to Q, Q see Figs 7 and 8 1.65 to 1.95 2.3 to 2.7 2.7 3.0 to 3.6 4.5 to 5.5 tW clock pulse width HIGH or LOW see Figs 6 and 8 1.65 to 1.95 2.3 to 2.7 2.7 3.0 to 3.6 4.5 to 5.5 set or reset pulse width LOW see Figs 7 and 8 1.65 to 1.95 2.3 to 2.7 2.7 3.0 to 3.6 4.5 to 5.5 trem removal time set or reset see Figs 7 and 8 1.65 to 1.95 2.3 to 2.7 2.7 3.0 to 3.6 4.5 to 5.5 tsu set-up time D to CP see Figs 6 and 8 1.65 to 1.95 2.3 to 2.7 2.7 3.0 to 3.6 4.5 to 5.5 1.5 1.0 1.0 1.0 1.0 1.5 1.0 1.0 1.0 1.0 1.5 1.0 1.0 1.0 1.0 6.2 2.7 2.7 2.7 2.0 6.2 2.7 2.7 2.7 2.0 1.9 1.4 1.3 1.2 1.0 2.9 1.7 1.7 1.3 1.1 6.0 3.5 3.5 VCC (V) MIN.
74LVC1G74
TYP.
MAX.
UNIT
13.4 7.1 7.1 5.9 4.1 12.9 7.0 7.0 5.9 4.1 12.9 7.0 7.0 5.9 4.1 - - - - - - - - - - - - - - - - - - - -
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
3.5(2) 2.5 6.0 3.5 3.5 3.0(2) 2.5 5.0 3.5 3.5 3.0(2) 2.5 - - - 1.3(2) - - - - 1.6(2) - - - - -3.0(2) - - - - 0.5(2) -
2005 Feb 01
9
Philips Semiconductors
Product specification
Single D-type flip-flop with set and reset; positive edge trigger
TEST CONDITIONS SYMBOL th PARAMETER WAVEFORMS hold time D to CP VCC (V) 0.0 0.3 0.5 1.2 0.5 80 175 175 175 200 - - - see Figs 6 and 8 1.65 to 1.95 2.3 to 2.7 2.7 3.0 to 3.6 4.5 to 5.5 fmax maximum clock pulse frequency see Figs 6 and 8 1.65 to 1.95 2.3 to 2.7 2.7 3.0 to 3.6 4.5 to 5.5 Tamb = -40 C to +125 C tPHL/tPLH propagation delay CP to Q, Q see Figs 6 and 8 1.65 to 1.95 2.3 to 2.7 2.7 3.0 to 3.6 4.5 to 5.5 propagation delay SD to Q, Q see Figs 7 and 8 1.65 to 1.95 2.3 to 2.7 2.7 3.0 to 3.6 4.5 to 5.5 propagation delay RD to Q, Q see Figs 7 and 8 1.65 to 1.95 2.3 to 2.7 2.7 3.0 to 3.6 4.5 to 5.5 tW clock pulse width HIGH or LOW see Figs 6 and 8 1.65 to 1.95 2.3 to 2.7 2.7 3.0 to 3.6 4.5 to 5.5 set or reset pulse width LOW see Figs 7 and 8 1.65 to 1.95 2.3 to 2.7 2.7 3.0 to 3.6 4.5 to 5.5 1.5 1.0 1.0 1.0 1.0 1.5 1.0 1.0 1.0 1.0 1.5 1.0 1.0 1.0 1.0 6.2 2.7 2.7 2.7 2.0 6.2 2.7 2.7 2.7 2.0 - - - - - - - - - - - - - - - - - - - - - - - - - MIN.
74LVC1G74
TYP.
MAX. - - - - - - - - - -
UNIT ns ns ns ns ns MHz MHz MHz MHz MHz
0.6(2) - - - - 280(2) -
13.4 7.1 7.1 5.9 4.1 12.9 7.0 7.0 5.9 4.1 12.9 7.0 7.0 5.9 4.1 - - - - - - - - - -
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
2005 Feb 01
10
Philips Semiconductors
Product specification
Single D-type flip-flop with set and reset; positive edge trigger
TEST CONDITIONS SYMBOL trem PARAMETER WAVEFORMS removal time set or reset VCC (V) 1.9 1.4 1.3 1.2 1.0 2.9 1.7 1.7 1.3 1.1 0.0 0.3 0.5 1.2 0.5 80 175 175 175 200 - - - - - - - - - - - - - - - - - - - - see Figs 7 and 8 1.65 to 1.95 2.3 to 2.7 2.7 3.0 to 3.6 4.5 to 5.5 tsu set-up time D to CP see Figs 6 and 8 1.65 to 1.95 2.3 to 2.7 2.7 3.0 to 3.6 4.5 to 5.5 th hold time D to CP see Figs 6 and 8 1.65 to 1.95 2.3 to 2.7 2.7 3.0 to 3.6 4.5 to 5.5 fmax maximum clock pulse frequency see Figs 6 and 8 1.65 to 1.95 2.3 to 2.7 2.7 3.0 to 3.6 4.5 to 5.5 Notes 1. All typical values are measured at Tamb = 25 C. 2. These typical values are measured at VCC = 3.3 V. MIN.
74LVC1G74
TYP.
MAX. - - - - - - - - - - - - - - - - - - - -
UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz MHz MHz MHz
2005 Feb 01
11
Philips Semiconductors
Product specification
Single D-type flip-flop with set and reset; positive edge trigger
AC WAVEFORMS
74LVC1G74
handbook, full pagewidth
VI D input GND th t su 1/fmax VI CP input GND tW t PHL VOH Q output VOL VOH Q output VOL t PLH t PHL
MNB141
VM
th t su
VM
t PLH
VM
VM
The shaded areas indicate when the input is permitted to change for predictable output performance.
INPUT VCC 1.65 V to 1.95 V 2.3 V to 2.7 V 2.7 V 3.0 V to 3.6 V 4.5 V to 5.5 V VM 0.5 x VCC 0.5 x VCC 1.5 V 1.5 V 0.5 x VCC VCC VCC 2.7 V 2.7 V VCC VI tr = tf 2.0 ns 2.0 ns 2.5 ns 2.5 ns 2.5 ns
VOL and VOH are typical output voltage drop that occur with the output load.
Fig.6
The clock input (CP) to output (Q, Q) propagation delays, the clock pulse width, the D to CP set-up, the CP to D hold times and the maximum clock pulse frequency.
2005 Feb 01
12
Philips Semiconductors
Product specification
Single D-type flip-flop with set and reset; positive edge trigger
74LVC1G74
handbook, full pagewidth
VI CP input GND t rem VI SD input GND tW VI RD input GND t PLH VOH Q output VOL VOH Q output VOL t PHL t PLH
MNB142
VM
VM
tW
VM
t PHL
VM
VM
INPUT VCC 1.65 V to 1.95 V 2.3 V to 2.7 V 2.7 V 3.0 V to 3.6 V 4.5 V to 5.5 V VM 0.5 x VCC 0.5 x VCC 1.5 V 1.5 V 0.5 x VCC VCC VCC 2.7 V 2.7 V VCC VI tr = tf 2.0 ns 2.0 ns 2.5 ns 2.5 ns 2.5 ns
VOL and VOH are typical output voltage drop that occur with the output load.
Fig.7
The set (SD) and reset (RD) input to output (Q, Q) propagation delays, the set and reset pulse widths and the RD to CP removal time.
2005 Feb 01
13
Philips Semiconductors
Product specification
Single D-type flip-flop with set and reset; positive edge trigger
74LVC1G74
VEXT VCC PULSE GENERATOR VI D.U.T. RT CL RL VO RL
mna616
VCC 1.65 V to 1.95 V 2.3 V to 2.7 V 2.7 V 3.0 V to 3.6 V 4.5 V to 5.5 V
VI VCC VCC 2.7 V 2.7 V VCC
CL 30 pF 30 pF 50 pF 50 pF 50 pF
RL 1 k 500 500 500 500
VEXT tPLH/tPHL open open open open open tPZH/tPHZ GND GND GND GND GND tPZL/tPLZ 2 x VCC 2 x VCC 6V 6V 2 x VCC
Definitions for test circuit: RL = Load resistor. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
Fig.8 Load circuitry for switching times.
2005 Feb 01
14
Philips Semiconductors
Product specification
Single D-type flip-flop with set and reset; positive edge trigger
PACKAGE OUTLINES
74LVC1G74
TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm
SOT505-2
D
E
A
X
c y HE vMA
Z
8
5
A pin 1 index
A2 A1
(A3)
Lp L
1
e bp
4
wM
detail X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.00 A2 0.95 0.75 A3 0.25 bp 0.38 0.22 c 0.18 0.08 D(1) 3.1 2.9 E(1) 3.1 2.9 e 0.65 HE 4.1 3.9 L 0.5 Lp 0.47 0.33 v 0.2 w 0.13 y 0.1 Z(1) 0.70 0.35 8 0
Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT505-2 REFERENCES IEC JEDEC --JEITA EUROPEAN PROJECTION ISSUE DATE 02-01-16
2005 Feb 01
15
Philips Semiconductors
Product specification
Single D-type flip-flop with set and reset; positive edge trigger
74LVC1G74
VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm
SOT765-1
D
E
A X
c y HE vMA
Z
8
5
Q A pin 1 index A2 A1 (A3) Lp L
1
e bp
4
wM
detail X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1 A1 0.15 0.00 A2 0.85 0.60 A3 0.12 bp 0.27 0.17 c 0.23 0.08 D(1) 2.1 1.9 E(2) 2.4 2.2 e 0.5 HE 3.2 3.0 L 0.4 Lp 0.40 0.15 Q 0.21 0.19 v 0.2 w 0.13 y 0.1 Z(1) 0.4 0.1 8 0
Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT765-1 REFERENCES IEC JEDEC MO-187 JEITA EUROPEAN PROJECTION
ISSUE DATE 02-06-07
2005 Feb 01
16
Philips Semiconductors
Product specification
Single D-type flip-flop with set and reset; positive edge trigger
74LVC1G74
XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1.95 x 0.5 mm
SOT833-1
1
2
3
b 4 4x L
(2)
L1
e
8 e1
7 e1
6 e1
5
8x
(2)
A
A1 D
E
terminal 1 index area 0 DIMENSIONS (mm are the original dimensions) UNIT mm A (1) max 0.5 A1 max 0.04 b 0.25 0.17 D 2.0 1.9 E 1.05 0.95 e 0.6 e1 0.5 L 0.35 0.27 L1 0.40 0.32 1 scale 2 mm
Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. OUTLINE VERSION SOT833-1 REFERENCES IEC --JEDEC MO-252 JEITA --EUROPEAN PROJECTION ISSUE DATE 04-07-22 04-11-09
2005 Feb 01
17
Philips Semiconductors
Product specification
Single D-type flip-flop with set and reset; positive edge trigger
DATA SHEET STATUS LEVEL I DATA SHEET STATUS(1) Objective data PRODUCT STATUS(2)(3) Development DEFINITION
74LVC1G74
This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).
II
Preliminary data Qualification
III
Product data
Production
Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
2005 Feb 01
18
Philips Semiconductors - a worldwide company
Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
(c) Koninklijke Philips Electronics N.V. 2005
SCA76
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
R20/03/pp19
Date of release: 2005
Feb 01
Document order number:
9397 750 14529

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