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E2B0020-27-Y2 Semiconductor
Semiconductor MSM5299A
80-DOT LCD SEGMENT DRIVER
This version: MSM5299A Nov. 1997 Previous version: Mar. 1996
GENERAL DESCRIPTION
The MSM5299A is a dot matrix LCD segment driver LSI which is fabricated using CMOS low power metal gate technology. This LSI consists of an 80-bit bidirectional shift register, 80-bit latch, 80-bit level shifter and 80-bit 4-level driver. It receives the display data, which is transferred in 4-bit parallel from a microcomputer or LCD controller LSI such as MSM6255, then outputs the LCD driving waveform to the LCD.
FEATURES
* * * * * Supply voltage : 4.5 to 5.5V LCD driving voltage : 8 to 28V Applicable LCD duty : 1/64 to 1/256 LCD Output : 80 The 4-bit parallel data processing has improved the transfer speed to 1/4 that of the conventional serial transfer, thereby achieving low power consumption * Can be interfaced with the LCD controller LSI MSM6255 * Applicable common diriver : MSM5298A (68 outputs) * Package options: 100-pin plastic QFP (QFP100-P-1420-0.65-K) (Product name : MSM5299AGS-K) 100-pin plastic QFP (QFP100-P-1420-0.65-BK) (Product name : MSM5299AGS-BK)
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Semiconductor
MSM5299A
BLOCK DIAGRAM
O1 O2 O79 O80
V1 V3 80-Bit 4-Level Driver V4 VEE VEE VDD
DF DISP OFF
80-Bit Level Shifter VDD
LOAD
80-Bit Latch (Edge trigger D-F/F)
VSS
D0 D1 D2 D3 CP EL Control Circuit
4 x 20-Bit Bidirectional Shift Register
SHL VDD
SHIFT CP
VSS ER
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Semiconductor
MSM5299A
PIN CONFIGURATION (TOP VIEW)

O51 O52 O53 O54 O55 O56 O57 O58 O59 O60 O61 O62 O63 O64 O65 O66 O67 O68 O69 O70 O71 O72 O73 O74 O75 O76 O77 O78 O79 O80 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
O50 O49 O48 O47 O46 O45 O44 O43
O42 O41 O40 O39 O38 O37 O36 O35
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
O34 O33 O32 O31
O30 O29 O28 O27 O26 O25 O24 O23 O22 O21 O20 O19 O18 O17 O16 O15 O14 O13 O12 O11 O10 O9 O8 O7 O6 O5 O4 O3 O2 O1
ER NC VEE V4 V3 V1 NC DF DISPOFF VDD SHL VSS
D3 D2 D1 D0 CP NC LOAD
NC : No connection
100-Pin Plastic QFP
Note: The abbreviated part number "M5299A" is imprinted on the package surface.
EL
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
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Semiconductor
MSM5299A
ABSOLUTE MAXIMUM RATINGS
(VSS=0V) Parameter Supply Voltage (1) Supply Voltage (2) Input Voltage Storage Temperature Symbol VDD VLCD VI TSTG Condition Ta = 25C Ta = 25C, VDD - VEE Ta = 25C --
*1
Rating -0.3 to +6 0 to 30 -0.3 to VDD+0.3 -55 to +150
Unit V V V C
*1 VDDV1>V3>V4>VEE
RECOMMENDED OPERATING CONDITIONS
(VSS=0V) Parameter Supply Voltage (1) Supply Voltage (2) Operating Temperature Symbol VDD VLCD Top Condition -- VDD - VEE --
*1
Range 4.5 to 5.5 8 to 28 -20 to +85
Unit V V C
*1 VDDV1>V3>V4>VEE
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Semiconductor
MSM5299A
ELECTRICAL CHARACTERISTICS
DC Characteristics
Parameter "H" Input Voltage "L" Input Voltage "H" Input Current "H" Input Current "H" Output Voltage "L" Output Voltage ON Resistance Stand-by Current Supply Current (1) Supply Current (2) Input Capacitance Symbol VIH *1 VIL *1 VIH *1 VIL *1 VOH *2 VOL *2 RON *4 IDDSBY IDD1 IV CI Condition -- -- VIH = VDD, VDD = 5.5V VIL = 0V, VDD = 5.5V IO = -0.2mA, VDD = 4.5V IO = 0.2mA, VDD = 4.5V VDD - VEE = 23V fCP = 1MHz, VDD = 5.5V VDD - VEE = 26V, No load fCP =1MHz, VDD = 5.5V VDD - VEE = 26V, No load fCP = 1MHz, VDD = 5.5V VDD - VEE = 26V, No load f = 1MHz *7 *6 *5 *3 (VDD = 5V 10%, Ta = -20 to +85C) Min. 0.8VDD VSS -- -- VDD - 0.4 -- -- -- -- -- -- Typ. -- -- -- -- -- -- 2 -- -- -- 5 Max. VDD 0.2VDD 1 -1 -- 0.4 4 200 3 100 -- Unit V V mA mA V V kW mA mA mA pF
VN - VO = 0.25V, VDD = 4.5V
*1 Applicable to LOAD, CP, D0 - D3, EL, ER, SHL, DF, DISP OFF *2 Applicable to EL, ER. *3 VN = VDD to VEE, V4 = 2 13 (VDD - VEE), V3 = (VDD - VEE), V1 = VDD 15 15
*4 Applicable to O1 to O80. *5 Display data 1010 ......fDF = 40 Hz, Current from VDD to VSS when the display data is not processing. *6 Display data 1010 ......fDF = 40 Hz, Current from VDD to VSS when the display data is processing. *7 Display data 1010 ......fDF = 40 Hz, Current on V1, V3 and V4.
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Semiconductor Switching Characteristics
MSM5299A
(VDD = 5V 10%, Ta = -20 to +75C, CL = 15pF) Parameter Clock Frequency Clock, Load Pulse Width Clock Pulse Rise/Fall Time Data Set-up Time Data Hold Time Load Set-up Time Load AE Clock Time Propagation Delay Time ER, EL Set-up Time Symbol fCP tW tr, tf tDSU tDHD tLSU tLC tPHL tESU Condition DUTY=50% -- -- -- -- -- -- -- -- Min. -- 100 -- 50 80 90 200 -- 70 Typ. -- -- -- -- -- -- -- -- -- Max. 3.4 -- 50 -- -- -- -- 224 -- Unit MHz ns ns ns ns ns ns ns ns
tW CP 0.8VDD 0.8VDD tDSU D0 - D3
tf
tW 0.2VDD tDHD
tr 0.8VDD 0.2VDD
tW 0.8VDD
0.8VDD 0.8VDD 0.2VDD 0.2VDD tLSU 0.8VDD 0.2VDD tf 2 19 0.2VDD 0.8VDD 20
LOAD
0.2VDD tr
0.8VDD tW
tLC
CP
1
LOAD tPHL ER, EL (Output) 0.2VDD tESU 0.2VDD
EL, ER (Input)
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Semiconductor
MSM5299A
FUNCTIONAL DESCRIPTION
Pin Functional Description * ER, EL
Pin ER EL EL ER Input/Output Input Output Input Output H L SHL Description Input pin to ENABLE F/F of MSM5299A. Output pin of ENABLE F/F. EL is connected to next MSM5299A's ER when MSM5299As are connected in series (cascade connection). Input pin to ENABLE F/F of MSM5299A. Output pin of ENABLE F/F. ER is connected to next MSM5299A's EL when MSM5299As are connected in series (cascade connection).
When single MSM5299A is used, ER (EL) should be set at "L" level. When a cascade connection is required, set the ER (EL) pin of the first MSM5299A at "L" level and connect the EL (ER) pin of the first MSM5299A to the ER (EL) pin of the second MSM5299A, then connect the EL (ER) pin of the second MSM5299A to the ER (EL) pin of the third MSM5299A. * CP Clock pulse input pin for the 4-bit parallel shift register. The data is shifted to 4 20-bit shift register at the falling edge of the clock pulse. The clock pulse is activated when the ENABLE F/F is set and is deactivated when the ENABLE F/F is not set. * SHL Input pin to switch the input or output of pins ER and EL, and the shift direction of the 4-bit parallel bidirectional shift register. The shift direction of the 4-bit parallel data, the correspondence of the data D0 to D3 to the driver outputs O1 to O80, and the input and output state of pins ER and EL are shown in the table below.
SHL ER EL D0 D1 D2 D3 D0 D1 D2 D3 Shift direction O1 O2 O3 O4 O80 O79 O78 O77 O5 O6 O7 O8 O76 O75 O74 O73 O77 O78 O79 O80 O4 O3 O2 O1
L
Input
Output
H
Output
Input
end data
start data
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Semiconductor
MSM5299A
* D0, D1, D2, D3 Display data input pins for 4 20-bit shift register. The display data is clocked into the shift register at the falling edge of the clock pulse. The combinations of D0 to D3 level, DF signal level, display data output level and the display on the LCD panel are described on the table below.
D0 to D3 L H L H DF L L H H Display data output level Nonselect level (V3) Select level (V1) Nonselect level (V4) Select level (VEE) Display on the LCD OFF ON OFF ON
* LOAD The signal for latching the shift register contents is input to this pin. The display data stored in the shift register is latched at the falling edge of the load pulse. * DF Synchronous signal input pin for alternate signal for LCD driving. * VDD, VSS Supply voltage pins, VDD should be 4.5 to 5.5V. VSS is a ground pin (VSS = 0V) * V1, V3, V4, VEE Bias supply voltage pin to drive the LCD. Use an external bias voltage supply for driving the LCD.
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MSM5299A
* O1 - O80 Display data output pins, which correspond to the respective latch contents. One of V1, V3, V4 and VEE is selected as a display driving voltage source according to the combination of the latched data level and DF signal. Refer to the Truth Table. The outputs O1 to O80 are connected to the segment side of the LCD panel. * DISP OFF Input pin to control outputs of O1 to O80. V1 level is output from O1 to O80 pins during "L" level input. Refer to the Truth Table. Truth Table
DF L L H H X Latched data L H L H X DISP OFF H H H H L LCD driver output (O1 - O80) V3 V1 V4 VEE V1
X : Don't care
NOTES ON USE
Note the following when turning power on and off: The LCD drivers of this IC require a high voltage. For this reason, if a high voltage is applied to the LCD drivers with the logic power supply floating, excess current flows. This may damage the IC. Be sure to carry out the following power-on and power-off sequences: When turning power on: First VDD ON, next VEE, V4, V3, V1 ON. Or both ON at the same time. When turning power off: First VEE, V4, V3, V1 OFF, next VDD OFF. Or both OFF at the same time.
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Semiconductor
MSM5299A
PACKAGE DIMENSIONS
(Unit : mm)
QFP100-P-1420-0.65-K
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 1.29 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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Semiconductor
MSM5299A
(Unit : mm)
QFP100-P-1420-0.65-BK
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 1.29 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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