View S6A0092_537046.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

S6A0092
80 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD
June. 2000. Ver. 0.2
Contents in this document are subject to change without notice. No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express written permission of LCD Driver IC Team.
80 COM / 26 COM DRIVER & CONTROLLER FOR STN LCD
S6A0092
S6A0092 Specification Revision History Version 0.0 0.1 0.2 Content Original Pin coordinate change at table 2 VDD change (2.4V~5.5V -> 2.4V~3.6V) Inspection Date May.1999 May.1999 Nov.1999 Jun.2000
1
S6A0092
26 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
CONTENTS
INTRODUCTION.......................................................................................................................................... 1 FEATURES ................................................................................................................................................. 1 BLOCK DIAGRAM ...................................................................................................................................... 3 PAD CONFIGURATION............................................................................................................................... 4 PAD DIAGRAM .................................................................................................................................... 4 PAD LOCATION ................................................................................................................................... 5 PIN DESCRIPTION...................................................................................................................................... 6 FUNCTION DESCRIPTION.......................................................................................................................... 9 SYSTEM INTERFACE.......................................................................................................................... 9 ADDRESS COUNTER (AC)................................................................................................................ 13 DISPLAY DATA RAM (DDRAM) ......................................................................................................... 13 CHARACTER GENERATOR ROM (CGROM)..................................................................................... 13 CHARACTER GENERATOR RAM (CGRAM) ..................................................................................... 14 SEGMENT ICON RAM (ICONRAM).................................................................................................... 16 LOW POWER CONSUMPTION MODE .............................................................................................. 17 LCD DRIVER CIRCUIT....................................................................................................................... 17 INSTRUCTION DESCRIPTION.................................................................................................................. 18 RETURN HOME ................................................................................................................................. 20 DOUBLE HEIGHT MODE ................................................................................................................... 20 POWER SAVE SET............................................................................................................................ 23 FUNCTION SET ................................................................................................................................. 23 LINE SHIFT MODE............................................................................................................................. 24 BIAS CONTROL ................................................................................................................................. 24 POWER CONTROL SET .................................................................................................................... 25 DISPLAY CONTROL .......................................................................................................................... 25 DDRAM / CGRAM ADDRESS SET..................................................................................................... 26 ICONRAM ADDRESS SET ................................................................................................................. 27 WRITE DATA ..................................................................................................................................... 28
2
80 COM / 26 COM DRIVER & CONTROLLER FOR STN LCD
S6A0092
READ DATA........................................................................................................................................28 INITIALIZING & POWER SAVE MODE SETUP..........................................................................................29 HARDWARE RESET...........................................................................................................................29 INITIALIZING AND POWER SAVE SETUP .........................................................................................30 LCD DRIVING POWER SUPPLY CIRCUIT ................................................................................................33 VOLTAGE CONVERTER ....................................................................................................................34 VOLTAGE REGULATOR.....................................................................................................................35 ELECTRONIC CONTRAST CONTROL (32 STEPS)............................................................................36 VOLTAGE GENERATOR CIRCUIT .....................................................................................................38 MPU INTERFACE ......................................................................................................................................39 APPLICATION INFORMATION FOR LCD PANEL.....................................................................................41 FRAME FREQUENCY................................................................................................................................43 1/17 DUTY (2-LINE MODE).................................................................................................................43 1/25 DUTY (3-LINE MODE).................................................................................................................43 MAXIMUM ABSOLUTE RATE....................................................................................................................44 ELECTRICAL CHARACTERISTICS...........................................................................................................45 DC CHARACTERISTICS.....................................................................................................................45 AC CHARACTERISTICS .....................................................................................................................46
3
80 COM / 26 COM DRIVER & CONTROLLER FOR STN LCD
S6A0092
INTRODUCTION
The S6A0092 is an LCD driver and controller LSI for liquid crystal dot matrix character display systems. It can display 2 or 3 lines of 16 characters with 5 x 8 dots format. It is capable of interfacing various microprocessors, supporting the 4-bit, 8-bit parallel modes and the clock synchronized serial mode. Voltage converter, oscillator, voltage regulator, voltage follower and bias circuit are built in the IC. The double height character mode and line vertical scroll functions are supported.
FEATURES
Driver Outputs - Common outputs: 26 common - Segment outputs: 80 segment Applicable Panel Size Font 5x8 Internal Memory - Character Generator ROM (CGROM): 10,240 bits (256 characters x 5 x 8 dots) - Character Generator RAM (CGRAM): 320 bits (8 characters x 5 x 8 dots) - Display Data RAM (DDRAM): 512 bits (16 characters x 4 lines) - Segment Icon RAM (ICONRAM): 80 bits (80 icons) MPU Interface - No busy MPU interface (no busy check or no execution waiting time) - 8-bit parallel interface mode: 68-series and 80-series are available - 4-bit parallel interface mode: 68-series and 80-series are available - Serial interface mode: 4 pins clock synchronized serial interface Function Set - Various instruction set: display control, power save, power control, etc. - COM / SEG bi-directional (4-type LCD application available) - H/W reset (RESETB) Built-in Analog Circuit - Internal RC oscillator circuit or external clock - Electronic volume for contrast control (32 steps) - Voltage converter / voltage regulator / voltage follower & bias circuit Low Power Operation - Sleep mode operation (5A Max.) - Normal mode operation (80A Max.) Display 2-line x 16 characters 3-line x 16 characters Duty 1 / 17 1 / 25 Contents of outputs 2 x 16 characters + 80 icons 3 x 16 characters + 80 icons
1
S6A0092
26 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
Operating Voltage Range - Power supply voltage (VDD): 2.4 ~ 3.6V - LCD driving voltage (VLCD = V0 - VSS): 6.0V Max. Package Type - Au bump chip or TCP
2
80 COM / 26 COM DRIVER & CONTROLLER FOR STN LCD
S6A0092
BLOCK DIAGRAM
RESETB PS IF MI CSB RS RW_WR E_RD DB7 (SI) DB6 (SCL) DB5DB4 DB3DB0 Input Buffer 8 Serial Interface 8 Instruction Register (IR)
CK
Oscillator
Timing Generator
Parallel Interface 4 bit/8 bit
8
Instruction Decoder Display Data RAM (DDRAM) 512 bits 7 8 8 80 bits Shift Register 8 Character Generator ROM (CGROM) 10240 bits 5 80 bits Latch Circuit 25 bits Shift Register
COM1Common COM24 Driver COM I1 COM I2
Address Counter Data Register (DR)
8 Data Output Register (OR)
SEG1Segment SEG80 Driver
5 Character Generator RAM (CGRAM) 320 bits 5
Icon RAM 80 bits
Cursor and Blink Controlle r
LCD Driver Voltage Selector
VDD GND Segment Data Conversion
LCD Driving Power Circuit Voltage Converter Voltage Regulator Voltage Follower & Bias Resistor
CAP1+ CAP1- CAP2+ CAP2-
VOUT V0 VEXT REF
VR
V1
V2
V3
V4
DIRS
Figure 1. Block Diagram
3
S6A0092
26 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
PAD CONFIGURATION
PAD DIAGRAM
166 167
87
............................
Y
86
179
Bumped pad height COG Align Key Coordinate
30m 30m 30m 30m 30m 30m
(-3065, -445)
... ..
Item Chip size Pad pitch Bumped pad size
1
...
(0,0)
X
74
...........................
73
DUMMY PAD PAD
Figure 2. Pad Configuration Table 1. S6A0092 Pad Dimensions Pad No. 1 ~ 73 74 ~ 179 1 ~ 73 74 ~ 86 87 ~ 166 167 ~ 179 All pad 60 100 50 100 17 ILB Align Key Coordinate
30m 30m 30m 42m 108m 42m 108m
Size X 7020 90 80 100 50 100 50 Y 1620
Unit
m
(-3440, +740) 60m 30m
(+3440, +740)
42m
42m
(-2965, -405)
108m
108m
4
80 COM / 26 COM DRIVER & CONTROLLER FOR STN LCD
S6A0092
PAD LOCATION
Table 2. PAD Center Coordinates
PAD NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 PAD NAME DUMMY DUMMY DUMMY DUMMY DUMMY CK CSB VSS RESETB RS VSS RW_WR VDD E_RD DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 VDD VDD VDD VSS VSS VSS VOUT VOUT VEXT VDD REF VSS VR VR VSS DIRS VDD CAP1CAP1CAP1+ CAP1+ CAP2+ CAP2+ CAP2CAP2V1 V1 V2 V2 V3 V3 V4 V4 V0 V0 V0 V0 VSS X -3240 -3150 -3060 -2970 -2880 -2790 -2700 -2610 -2520 -2430 -2340 -2250 -2160 -2070 -1980 -1890 -1800 -1710 -1620 -1530 -1440 -1350 -1260 -1170 -1080 -990 -900 -810 -720 -630 -540 -450 -360 -270 -180 -90 0 90 180 270 360 450 540 630 720 810 900 990 1080 1170 1260 1350 1440 1530 1620 1710 1800 1890 1980 2070 Y -700 -700 -700 -700 -700 -700 -700 -700 -700 -700 -700 -700 -700 -700 -700 -700 -700 -700 -700 -700 -700 -700 -700 -700 -700 -700 -700 -700 -700 -700 -700 -700 -700 -700 -700 -700 -700 -700 -700 -700 -700 -700 -700 -700 -700 -700 -700 -700 -700 -700 -700 -700 -700 -700 -700 -700 -700 -700 -700 -700 PAD NO. 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 PAD NAME VSS IF VDD MI VSS PS VDD TEST DUMMY DUMMY DUMMY DUMMY DUMMY COMI1 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM17 COM18 COM19 COM20 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 X 2160 2250 2340 2430 2520 2610 2700 2790 2880 2970 3060 3150 3240 3400 3400 3400 3400 3400 3400 3400 3400 3400 3400 3400 3400 3400 3160 3080 3000 2920 2840 2760 2680 2600 2520 2440 2360 2280 2200 2120 2040 1960 1880 1800 1720 1640 1560 1480 1400 1320 1240 1160 1080 1000 920 840 760 680 600 520 Y -700 -700 -700 -700 -700 -700 -700 -700 -700 -700 -700 -700 -700 -520 -440 -360 -280 -200 -120 -40 40 120 200 280 360 440 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 PAD NO. 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 PAD NAME SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 SEG64 SEG65 SEG66 SEG67 SEG68 SEG69 SEG70 SEG71 SEG72 SEG73 SEG74 SEG75 SEG76 SEG77 SEG78 SEG79 SEG80 COMI2 COM24 COM23 COM22 COM21 COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9 X 440 360 280 200 120 40 -40 -120 -200 -280 -360 -440 -520 -600 -680 -760 -840 -920 -1000 -1080 -1160 -1240 -1320 -1400 -1480 -1560 -1640 -1720 -1800 -1880 -1960 -2040 -2120 -2200 -2280 -2360 -2440 -2520 -2600 -2680 -2760 -2840 -2920 -3000 -3080 -3160 -3400 -3400 -3400 -3400 -3400 -3400 -3400 -3400 -3400 -3400 -3400 -3400 -3400 Y 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 700 440 360 280 200 120 40 -40 -120 -200 -280 -360 -440 -520
5
S6A0092
26 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
PIN DESCRIPTION
Table 3. Pin Description Name Power supply Power supply VDD VSS Power Connect to MPU power supply pin 0V (GND) Bias voltage level for LCD driving Voltages should have the following relationship; V0 V1 V2 V3 V4 VSS V0 V1 V2 V3 V4 I/O
1/5 bias
I/O
Description
When the built-in power circuit is active and internal 1/5 bias resistors are used.
LCD bias
V1
V2
V3 (2/5) x V0
V4 (1/5) x V0
(4/5) x V0 (3/5) x V0
When the built-in power circuit is active and internal 1/4 bias resistors are used.
LCD bias 1/4 bias
V1 (3/4) x V0
V2
V3 (2/4) x V0
V4 (1/4) x V0
LCD driver supply CAP1+ CAP1CAP2+ CAP2VOUT VR O O O O I/O I Capacitor + connecting pin for the internal voltage converter Capacitor - connecting pin for the internal voltage converter Capacitor + connecting pin for the internal voltage converter Capacitor - connecting pin for the internal voltage converter DC/DC voltage converter output (7.2V) Voltage adjust pin This pin gives a voltage between V0 and VSS by resistance-division of voltage. External reference voltage for internal regulator (instead of the internal VREF, 2V) REF = "Low (VSS)": VEXT is not used (open) REF = "High (VDD)": VEXT is reference input voltage of internal voltage regulator. Select the input voltage of internal voltage regulator REF = "Low (VSS)": The input voltage of internal Voltage regulator is the internal VREF(2V). REF = "High (VDD)": The input voltage of internal Voltage regulator is the voltage of VEXT.
VEXT
I
REF
I
6
80 COM / 26 COM DRIVER & CONTROLLER FOR STN LCD
S6A0092
Table 3. Pin Description (Continued) Name System control CK I External clock input. It must be fixed to "High" or "Low" when the internal oscillation circuit is used. In case of the external clock mode, CK is used as the clock and OS bit should be OFF. MPU interface selection input MI = "Low": 80-series MPU MI = "High": 68-series MPU Parallel / serial selection input When PS = "Low": serial mode When PS = "High": 4-bit/8-bit bus mode Interface data length selection pin for parallel data input When PS = "Low" IF = "Low" or "High": serial interface mode When PS = High IF = "Low": 4-bit bus mode IF = "High": 8-bit bus mode SEG direction selection input When DIRS = "Low" SEG1 SEG2 SEG79 SEG80 When DIRS = "High" SEG80 SEG79 SEG2 SEG1 I/O Description
MI
I
PS
I
IF
I
DIRS
I
MPU interface RESETB CSB I I Reset input S6A0092 is initialized while RESETB is low. Chip selection input S6A0092 is selected while CSB is low. Register selection input When RS = "Low", instruction register When RS = "High", data register. In 80-series MPU interface mode This pin is connected to WR pin of MPU and is a active low write signal In 68-series MPU interface mode This pin is connected to R/W pin of MPU When RW_WR = "Low", write mode When RW_WR = "High", read mode In 80-series MPU interface mode This pin is connected to RD pin of MPU and is a active low read signal In 68-series MPU interface mode This pin is connected to E pin of MPU and enable read or write command according to RW_WR signal.
RS
I
RW_WR
I
E_RD
I
7
S6A0092
26 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
Table 3. Pin Description (Continued) Name DB0 DB3 DB4 DB5 DB6 (SCL), DB7 (SI) LCD driver outputs COM1 COM24 COMI1, COMI2 SEG1 SEG80 Test TEST I Test pin This pin is not used for normal operation. TEST: These pins should be opened or floated. O O O Common signal output for driving LCD Common signal output for icon display These are the same signal but the name is different. Segment signal output for driving LCD I/O I/O Description When 8-bit bus mode, used as bi-directional data bus DB0 DB7 During 4-bit bus mode, only DB4 DB7 are used. In this case DB0 DB3 pins are not used. When serial mode, DB6 (SCL) is used as serial clock input pin and DB7 (SI) is used as serial data input pin.
8
80 COM / 26 COM DRIVER & CONTROLLER FOR STN LCD
S6A0092
FUNCTION DESCRIPTION
SYSTEM INTERFACE
S6A0092 has two kinds of interface type with MPU: bus mode, serial mode. Serial or bus mode is selected by PS pin. In bus mode, 4-bit bus or 8-bit bus is selected by IF pin, and 68 series MPU or 80 series MPU is selected by MI pin. Table 4. Various Kinds of MPU Interface according to PS, MI and IF
PS MI 68 series Bus mode (H) (H) 80 series (L) Serial mode (L) NOTES: 1. Don' t care (high, low or open) 2. Fixed high (VDD) or low (VSS) (H)/(L)(2) IF 8 bit (H) 4 bit (L) 8 bit (H) 4 bit (L) (H)/(L) CSB CSB CSB CSB CSB CSB RS RS RS RS RS RS RW_WR R/W R/W WR WR (H)/(L) E_RD E E RD RD (H)/(L) DB0DB3 DB0DB3
(1)
DB4DB5 DB4DB5 DB4DB5 DB4DB5 DB4DB5
DB6 DB6 DB6 DB6 DB6 SCL
DB7 DB7 DB7 DB7 DB7 SI
DB0DB3
PS: "High" = bus mode, "Low" = serial mode MI: "High" = 68-series MPU, "Low" = 80-series MPU IF: "High" = 8 bit mode, "Low" = 4 bit mode (PS: "High") CSB: "High" = chip is not selected, "Low" = chip is selected RS: "High" = data register, "Low" = instruction register RW_WR: Read / Write indicating signal in 68 mode or active low signal for enabling write in 80 mode E_RD: Active high signal for enabling command is 68 mode or active low signal for enabling read in 80 mode. SCL (DB6): Serial clock input SI (DB7): Serial data input
9
S6A0092
26 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
Interface with MPU in Parallel Mode (PS = "High") During writing operation, two 8-bit registers, data register (DR) and instruction register (IR), are used. The data register (DR) is used as temporary data storage place for being written into DDRAM / CGRAM / ICONRAM and one of these RAMs is selected by RAM address setting instruction. The Instruction register (IR) is used only to store instruction code transferred from MPU. To select DR or IR register, RS input pin is used. During reading operation, 8-bit register, output data register (OR) is used. The output data register (OR) is used as temporary data storage place for being read from DDRAM / CGRAM / ICONRAM and one of these RAMs is selected by RAM address setting instruction. After RAM address setting, first reading is a dummy cycle in 8-bit bus mode (figure 3, 4). The valid data comes from second reading. In 4-bit bus mode, after RAM address setting, first and second reading are dummy cycles (figure 5, 6). The valid data comes from third reading. The dummy read make the address counter (AC) increased by 1. So it is recommended to set address again before writing. The instruction read cycle is not supported and it is regarded as a no operation cycle. In 4-bit bus mode, it is needed to transfer 4-bit data (through DB7DB4) by two times. The high order bits (for 8-bit mode DB7DB4) are written before the low order bits (for 8-bit mode DB3DB0) in write and low order bits (for 8-bit mode DB3DB0) are read before the high order bits (for 8-bit mode DB7DB4) in read transaction. The DB0DB3 pins are floated in this 4-bit bus mode. After RESETB resets, S6A0092 considers first 4-bit data from MPU as the high order bits.
IF MI CSB RS RW_WR E_RD DB7 DB0
Instruction Write NOP Dummy Read
Valid Data
RAM Read
Data Write
Figure 3. Timing Diagram of 8-bit Parallel Bus Mode Data Transfer (68-series MPU Mode)
10
80 COM / 26 COM DRIVER & CONTROLLER FOR STN LCD
S6A0092
IF MI CSB RS RW_WR E_RD DB7 DB0
Instruction W rite NOP Dummy Read
Valid Data
RAM Read
Data W rite
Figure 4. Timing Diagram of 8-bit Parallel Bus Mode Data Transfer (80-series MPU Mode)
IF MI CSB RS RW_WR E_RD DB7 DB4
upper 4-bit lower 4-bit lower 4-bit upper 4-bit upper 4-bit lower 4-bit
Instruction Write
NOP
Dummy Read
RAM Read
Data Write
Figure 5. Timing Diagram of 4-bit Parallel Bus Mode Data Transfer (68-series MPU Mode)
11
S6A0092
26 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
IF MI CSB RS RW_WR E_RD DB7DB4
upper 4-bit lower 4-bit lower 4-bit upper 4-bit upper 4-bit lower 4-bit
Instruction Write
NOP
Dummy Read
RAM Read
Data Write
Figure 6. Timing Diagram of 4-bit Parallel Bus Mode Data Transfer (80-series MPU Mode)
Interface with MPU in Serial Mode (PS = "Low") When PS input pin is "Low", clock synchronized serial interface mode is selected. At this time, five ports, RESETB (reset input), SCL (DB6, synchronizing transfer clock), SI (DB7, serial input data), RS (register selection input) and CSB (chip selection input) are used. By setting CSB to "Low", S6A0092 can receive SCL input. If CSB is set to "High", S6A0092 resets the internal 8-bit shift register and 3-bit counter. Serial data is input in the order of "D7, D6, D5, D4, D3, D2, D1, D0" from the serial data input pin (SI = DB7) at the rising edge of serial clock (SCL = DB6). At the rising edge of the 8th serial clock, the serial data (D7-D0) is converted into 8 bit bus mode data. The RS input of the DR/IR selection is latched at the rising edge of the 8th serial clock (SCL).
CSB S I (D B 7 ) SCL (DB6) RS 1
D7
2
D6
3
D5
4
D4
5
D3
6
D2
7
D1
8
D0
9
D7
Figure 7. Timing Diagram of Serial Data Transfer
12
80 COM / 26 COM DRIVER & CONTROLLER FOR STN LCD
S6A0092
ADDRESS COUNTER (AC)
Address Counter (AC) in S6A0092 stores DDRAM / CGRAM / ICONRAM address. After writing into or reading from DDRAM / CGRAM / ICONRAM, AC is automatically increased by 1. The address counter is only one and stores the address among DDRAM / CGRAM / ICONRAM.
DISPLAY DATA RAM (DDRAM)
DDRAM stores display data of maximum 64 x 8 bits (Max. 64 characters). DDRAM address is set in the address counter (AC) as a hexadecimal number.
1st Ch.
16th Ch.
COM1 COM9
COM8 COM16
00 10 20 30
01 11 21 31
02 12 22 32
03 13 23 33
04 14 24 34
05 15 25 35
06 16 26 36
07 17 27 37
08 18 28 38
09 19 29 39
0A 1A 2A 3A
0B 1B 2B 3B
0C 1C 2C 3C
0D 1D 2D 3D
0E 1E 2E 3E
0F 1F 2F 3F
Hidden Line Hidden Line
SEG1
SEG80
(1)
2 line mode DDRAM Address
COM1 COM9
COM8 COM16
00 10 20 30
01 11 21 31
02 12 22 32
03 13 23 33
04 14 24 34
05 15 25 35
06 16 26 36
07 17 27 37
08 18 28 38
09 19 29 39
0A 1A 2A 3A
0B 1B 2B 3B
0C 1C 2C 3C
0D 1D 2D 3D
0E 1E 2E 3E
0F 1F 2F 3F
COM17 COM24 Hidden Line
SEG1
SEG80
(2)
3 line mode DDRAM Address
Figure 8. DDRAM Address
CHARACTER GENERATOR ROM (CGROM)
CGROM has 5 x 8-dot 256 characters. The CG bit of the instruction table selects the 8 characters (00h ~ 07h) of CGROM or CGRAM.
13
S6A0092
26 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
CHARACTER GENERATOR RAM (CGRAM)
CGRAM has up to 5 x 8-dot 8 characters. By writing font data to CGRAM, user defined character can be used. CGRAM can be written regardless of CG bit.
Table 6. Relationship between Character Code (DDRAM) and Character Pattern (CGRAM)
Character code (DDRAM data) D7 D6 D5 D4 D3 D2 D1 D0
DDRAM / CGRAM address A6 A5 A4 A3 A2 A1 A0 1000000 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
CGRAM data P7 P6 P5 P4 P3 P2 P1 P0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 1 1 1 0 1 1 1 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 0 1 0 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 1 1 0 1 1 1 1 1 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 0 1 0 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 1 1 1 0 1 1 1
Pattern number
00000000 (00h)
Pattern 1
00000001 (01h)
Pattern 2
00000010 (02h)
Pattern 3
00000011 (03h)
Pattern 4
14
80 COM / 26 COM DRIVER & CONTROLLER FOR STN LCD
S6A0092
Table 6. Relationship between Character Code (DDRAM) and Character Pattern (CGRAM) (continued)
Character code (DDRAM data) D7 D6 D5 D4 D3 D2 D1 D0 DDRAM / CGRAM address A6 A5 A4 A3 A2 A1 A0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CGRAM data P7 P6 P5 P4 P3 P2 P1 P0 1 1 0 1 1 1 1 1 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 1 1 1 0 0 0 1 1 1 1 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 0 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 0 0 0 1 1 1 1 1 1 0 0 1 1 0 0 1 1 1 1 1 1 1 1 0 0 1 0 0 0 1 1 1 1 0 1 1 1 1 1 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 1 1 Pattern number
00000100 (04h)
Pattern 5
00000101 (05h)
Pattern 6
00000110 (06h)
Pattern 7
00000111 (07h)
Pattern 8
NOTE: "-" Don' t care
15
S6A0092
26 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
SEGMENT ICON RAM (ICONRAM)
ICONRAM has segment control data and segment pattern data. COMI1 and COMI2 are the same signal but the name is different. So the icons on the same SEG are displayed at the same time. The number of icons is 80.
COMI 1
COMI 2
SEG 76 SEG 77 SEG 78 SEG 79 SEG 80 SEG 1 SEG 2 SEG 3 SEG 4 SEG 5
Figure 9. Relationship between ICONRAM and Icon Display
Table 7. Relationship between ICONRAM Address and Display Pattern ICONRAM address 00h 01h 02h . . 0Dh 0Eh 0Fh
NOTE: "-" Don' t care
ICONRAM bits D7 . . D6 . . D5 . . D4 S1 S6 S11 . . S66 S71 S76 D3 S2 S7 S12 . . S67 S72 S77 D2 S3 S8 S13 . . S68 S73 S78 D1 S4 S9 S14 . . S69 S74 S79 D0 S5 S10 S15 . . S70 S75 S80
16
80 COM / 26 COM DRIVER & CONTROLLER FOR STN LCD
S6A0092
LOW POWER CONSUMPTION MODE
S6A0092 provides with sleep mode for saving power consumption during standby period. Sleep Mode (Power Save Bit ON, Oscillation Bit OFF) To enter the sleep mode, the power circuit and oscillation circuit should be turned off by using the power save command and the power control command. This mode helps to save power consumption by reducing current to reset level. 1. Liquid Crystal Display Output COM1 ~ COM24, COMI1, COMI2: VSS level SEG1 ~ SEG80: VSS level 2. Data written in DDRAM, CGRAM, ICONRAM and registers are remained as previous value. 3. Operation mode is retained the same as it was prior to execution of the sleep mode. All internal circuits are stopped. 4. Power Circuit and Oscillation Circuit The built-in power supply circuit and oscillation circuit are turned off by power save command and power control command.
LCD DRIVER CIRCUIT
LCD Driver circuit has 26 common and 80 segment signals for driving LCD. Data from ICONRAM / CGRAM / CGROM are transferred to 80-bit segment register serially, and then they are stored to 80-bit shift latch. In case of 2-line display mode, COM1 ~ COM16, COMI1 and COMI2 have 1/17 duty, and in 3-line mode, COM1 ~ COM24, COMI1 and COMI2 have 1/25 duty ratio. SEG bi-directional function is selected by DIRS input pin, and COM shift direction is selected by function set instruction "S" bit. Table 8. SEG Data Shift Direction DIRS pin Low High
SEG1 SEG80
SEG data shift direction
SEG2
SEG3
.... ........................ ............. .
SEG78

SEG79 SEG2

SEG80 SEG1
SEG79
SEG78
....... ..................... . ......... SEG3 .
Table 9. COM Data Shift Direction Line mode 2-line mode 3-line mode S 0 (left) 1 (right) 0 (left) 1 (right) COM data shift direction COM1 COM2 ...... ............ COM15 COM16 COMI1 (COMI2) .... COMI1 (COMI2) COM16 COM15 .... ......... .. ...... COM2 COM1 ... COM1 COM2 ... ............ ....... COM23 COM24 COMI1 (COMI2) COMI1 (COMI2) COM24 COM23 ..... ......... ... .. COM2 COM1 ....
17
S6A0092
26 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
INSTRUCTION DESCRIPTION
Table 10. Instruction Table
Instruction Return home RS DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Description DDRAM address is set to 00h from AC and the cursor returns 0 0 0 0 0 0 0 1 to 00h position The contents of DDRAM are not changed. Double height mode DH2, DH1 = 00: normal display (default) 01: COM1 COM16 is a double height, Double height mode COM17COM24 is normal 0 0 0 0 0 1 0 DH2 DH1 10: 1) 2-line mode : normal display 2) 3-line mode : COM1COM8 is normal, COM9 COM24 is a double height 11: normal display Power save Power save / oscillation circuit ON / OFF 0 0 0 0 0 1 1 OS PS OS = 0: oscillator OFF (default) Display line mode N = 0: 2-line display mode (default) 1: 3-line display mode shifting direction of COM. Function set S = 0: 1) 2-line mode: COM1 -> COM16 (default) 0 0 0 0 1 0 N S CG 2) 3-line mode: COM1 -> COM24 (default) 1: 1) 2-line mode: COM16 -> COM1 2) 3-line mode: COM24 -> COM1 Select CGRAM or CGROM CG = 0: CGROM (default) line at LCD Line shift mode LS2, LS1 = 00: DDRAM line 1 shows at the first line of 0 0 0 0 1 1 0 LS2 LS1 LCD (default). 01: DDRAM line 2 shows at the first line of LCD. 10: DDRAM line 3 shows at the first line of LCD. 11: DDRAM line 4 shows at the first line of LCD Determination of bias Bias control 0 0 0 0 1 1 1 BS BS = 0: 1/5 bias (default) 1: 1/4 bias LCD power control VC = 0: voltage converter OFF (default) Power control 1: voltage converter ON 0 0 0 1 0 0 VC VR VF VR = 0: voltage regulator OFF (default) 1: voltage regulator ON VF = 0: voltage follower OFF (default) 1: voltage follower ON 1: CGRAM Determination of the DDRAM line which is displayed at the first 1: oscillator ON PS = 0: power save OFF (default) 1: power save ON
18
80 COM / 26 COM DRIVER & CONTROLLER FOR STN LCD
S6A0092
Table 10. Instruction Table (Continued)
Instruction RS DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Description Cursor / blink / display ON / OFF Display control 0 0 0 1 0 1 C B D C = 0: cursor OFF (default), 1: cursor ON B = 0: blink OFF (default), 1: blink ON D = 0: display OFF (default), 1: display ON DD/CGRAM address set ICONRAM address set Write Data Read Data NOP Test NOTE: 1. "-": Don' t care 2. "*": Don' t use 3: Instruction execution time depends on the internal process time of S6A0092, therefore it is necessary to provide a time larger than one MPU interface cycle time (tc) between execution of two successive instructions. 0 0 0 0 0 0 0 1 0 1 0 * 0 * 0 * 0 * 1 1 D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 0 0 1 0 IA4 IA3 IA2 IA1 0 1 AC6 AC5 AC4 AC3 AC2 AC1 DDRAM / CGRAM address AC0 range: DDRAM 00h 3Fh CGRAM 40h 7Fh ICONRAM address, electronic volume and test byte address IA0 range: ICONRAM 00h 0Fh EV 10h (electronic volume byte), TE 11h (test byte) Write DDRAM / CGRAM / ICONRAM
Read DDRAM / CGRAM / ICONRAM or registers data (note1) Non-operation Instruction Don' t use this Instruction.
19
S6A0092
26 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
RETURN HOME
RS 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 0 DB2 0 DB1 1 DB0 -
Return Home instruction field makes cursor return home. DDRAM address is set to 00h from AC and the cursor returns to 00h position. The contents of DDRAM are not changed.
DOUBLE HEIGHT MODE
RS 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 1 DB2 0 DB1 DH2 DB0 DH1
Double Height Mode instruction field selects double height line type. DH2, DH1 = 00: normal display line mode (default) 01: COM1 COM16 is a double height, COM17 COM24 is normal 10: 1) 2-line mode: normal display 2) 3-line mode: COM1 COM8 is normal COM9 COM24 is a double height 11: normal display
Figure 10. 3-line Normal Mode Display (DH2, DH1 = 00)
20
80 COM / 26 COM DRIVER & CONTROLLER FOR STN LCD
S6A0092
Figure 11. COM1 ~ 16 is a Double Height Line, COM17 ~ 24 is Normal (DH2, DH1 = 01)
Figure 12. COM1 ~ 8 is Normal, COM9 ~ COM24 is a Double Height Line (DH2, DH1 = 10)
Figure 13. 2-Line Normal Mode Display (DH2, DH1 = 00)
21
S6A0092
26 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
Figure 14. COM1 ~ 16 is a Double Height Line (DH2, DH1 = 01)
22
80 COM / 26 COM DRIVER & CONTROLLER FOR STN LCD
S6A0092
POWER SAVE SET
RS 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 1 DB2 1 DB1 OS DB0 PS
Power Save instruction field is used to control the oscillator and to set or to reset the power save mode. OS: Oscillator ON / OFF Control Bit When OS = "High", oscillator is turned ON. When OS = "Low", oscillator is turned OFF (default). PS: Power Save ON / OFF Control Bit When PS = "High", power save mode is turned ON. When PS = "Low", power save mode is turned OFF (default).
FUNCTION SET
RS 0 DB7 0 DB6 0 DB5 0 DB4 1 DB3 0 DB2 N DB1 S DB0 CG
N: Display Line Mode Instruction field selects 2 line or 3 line display mode When N = "High", 3-line display mode When N = "Low", 2-line display mode (default) S: Data Shift Direction of Common S sets the shift direction of common display data When S = "High", COM right shift. When S = "Low", COM left shift (default). (Refer to table 9) CG: CGRAM Enable Bit When CG = "High", CGRAM can be accessed and you can use this RAM for eight special character area. (00h - 07h = CGRAM font display) When CG = "Low", CGRAM is disabled. CGROM (00h~07h) can be accessed and the additional current consumption is saved by using this mode (default). (00h - 07h = CGROM font display)
23
S6A0092
26 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
LINE SHIFT MODE
RS 0 DB7 0 DB6 0 DB5 0 DB4 1 DB3 1 DB2 0 DB1 LS2 DB0 LS1
Line Shift Mode instruction field selects the DD RAM to be displayed in first line. LS2, LS1 = 00: DDRAM line 1 shows at the first line of LCD (default). 01: DDRAM line 2 shows at the first line of LCD. 10: DDRAM line 3 shows at the first line of LCD. 11: DDRAM line 4 shows at the first line of LCD.
LCD
LCD
LCD
LCD
DD RAM Line1 (00h~0Fh) DD RAM Line2 (10h~1Fh) DD RAM Line3 (20h~2Fh) DD RAM Line4 (30h~3Fh)
LS2, LS1 = 00
DD RAM Line2 (10h~1Fh) DD RAM Line3 (20h~2Fh) DD RAM Line4 (30h~3Fh) DD RAM Line1 (00h~0Fh)
LS2, LS1 = 01
DD RAM Line3 (20h~2Fh) DD RAM Line4 (30h~3Fh) DD RAM Line1 (00h~0Fh) DD RAM Line2 (10h~1Fh)
LS2, LS1 = 10
DD RAM Line4 (30h~3Fh) DD RAM Line1 (00h~0Fh) DD RAM Line2 (10h~1Fh) DD RAM Line3 (20h~2Fh)
LS2, LS1 = 11
Figure 15. Line Shift Mode Display at 3-line LCD
LCD
LCD
LCD
LCD
DD RAM Line1 (00h~0Fh) DD RAM Line2 (10h~1Fh) DD RAM Line3 (20h~2Fh) DD RAM Line4 (30h~3Fh)
LS2, LS1 = 00
DD RAM Line2 (10h~1Fh) DD RAM Line3 (20h~2Fh) DD RAM Line4 (30h~3Fh) DD RAM Line1 (00h~0Fh)
LS2, LS1 = 01
DD RAM Line3 (20h~2Fh) DD RAM Line4 (30h~3Fh) DD RAM Line1 (00h~0Fh) DD RAM Line2 (10h~1Fh)
LS2, LS1 = 10
DD RAM Line4 (30h~3Fh) DD RAM Line1 (00h~0Fh) DD RAM Line2 (10h~1Fh) DD RAM Line3 (20h~2Fh)
LS2, LS1 = 11
Figure 16. Line Shift Mode Display at 2-line LCD
BIAS CONTROL
RS 0 DB7 0 DB6 0 DB5 0 DB4 1 DB3 1 DB2 1 DB1 DB0 BS
Bias Control instruction field sets LCD bias voltages generated internally. This bit is used when the internal voltage follower is ON. BS = 0: 1/5 bias (default) 1: 1/4 bias (V2 = V3)
24
80 COM / 26 COM DRIVER & CONTROLLER FOR STN LCD
S6A0092
POWER CONTROL SET
RS 0 DB7 0 DB6 0 DB5 1 DB4 0 DB3 0 DB2 VC DB1 VR DB0 VF
Power Control instruction field sets voltage regulator / converter / follower ON / OFF. VC: Voltage Converter Circuit Control Bit When VC= "High", voltage converter is turned ON. When VC = "Low", voltage converter is turned OFF (default). VR: Voltage Regulator Circuit Control Bit When VR = "High", voltage regulator is turned ON. When VR = "Low", voltage regulator is turned OFF (default). VF: Voltage Follower Circuit Control Bit When VF = "High", voltage follower is turned ON. When VF = "Low", voltage follower is turned OFF (default).
NOTE: The oscillation circuit must be turned on for the voltage converter circuit to be active.
DISPLAY CONTROL
RS 0 DB7 0 DB6 0 DB5 1 DB4 0 DB3 1 DB2 C DB1 B DB0 D
Display Control instruction field controls cursor / blink / display ON / OFF. C: Cursor ON / OFF Control Bit When C = "High", cursor is turned ON. When C = "Low", cursor is disappeared in current display (default). B: Cursor Blink ON / OFF Control Bit When C = "High" and B = "High", S6A0092 make LCD alternate between inverting display character and normal display character at the cursor position with about a half second. On the contrary, if C = "Low", only a normal character is displayed regardless of "B" flag. When B = "Low", blink is OFF (default). D: Display ON / OFF Control Bit When D = "High", entire display is turned ON. When D = "Low", display is turned OFF, but display data are remained in DDRAM (default).
25
S6A0092
26 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
Table 11. Cursor Attributes C, B 1, 0 Display state
1, 1 (Blinking mode)
0, 0 0, 1
DDRAM / CGRAM ADDRESS SET
RS 0 DB7 1 DB6 AC6 DB5 AC5 DB4 AC4 DB3 AC3 DB2 AC2 DB1 AC1 DB0 AC0
DDRAM / CGRAM Address Set instruction field sets DDRAM / CGRAM address. Before writing / reading data into / from the RAM, set the address by RAM Address Set instruction. Next, when data are written / read in succession, the address is automatically increased by 1. After accessing 7Fh, the address of AC is 00h. The address ranges are 00h 7Fh.
26
80 COM / 26 COM DRIVER & CONTROLLER FOR STN LCD
S6A0092
Table 12. DDRAM / CGRAM Address Mapping Address 00h 10h 20h 30h 40h 50h 60h 70h CGRAM (pattern 0) CGRAM (pattern 2) CGRAM (pattern 4) CGRAM (pattern 6) 0 1 2 3 4 5 6 7 8 9 A B C D E F
DDRAM line 1 (00h 0Fh) DDRAM line 2 (10h 1Fh) DDRAM line 3 (20h 2Fh) DDRAM line 4 (30h 3Fh) CGRAM (pattern 1) CGRAM (pattern 3) CGRAM (pattern 5) CGRAM (pattern 7)
ICONRAM ADDRESS SET
RS 0 DB7 0 DB6 1 DB5 0 DB4 IA4 DB3 IA3 DB2 IA2 DB1 IA1 DB0 IA0
ICONRAM Address Set instruction field sets ICONRAM / Registers address. Before writing/reading data into / from the ICON RAM, set the address by ICONRAM Address Set instruction. Next, when data are written/read in succession, the address is automatically increased by 1. The 5 icons at a time can blink, if C and B bit of the display instruction are enabled. The blink attributes of ICON are same as the cursor blink. For accessing DD/CGRAM, the DD/CGRAM Address Set instruction should be set before. After accessing 0Fh, the address of ICONRAM address is 00h. The ICONRAM address ranges are 00h 1Fh.
Table 13. ICONRAM Address Mapping Address 00h 10h EV TE 0 1 2 3 4 5 6 7 8 9 A B C D E F
ICON RAM (00h 0Fh) Reserved
EV: Electronic volume register (10h) - default (00000) TE: Test register (Do not use) (11h) When the EV and TE registers are written, the address counter (AC) is not increased.
27
S6A0092
26 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
WRITE DATA
RS 1 DB7 D7 DB6 D6 DB5 D5 DB4 D4 DB3 D3 DB2 D2 DB1 D1 DB0 D0
This instruction field make S6A0092 write binary 8-bit data to DDRAM / CGRAM / ICONRAM or register. The RAM address to be written into is determined by previous DD/CGRAM Address Set or ICONRAM Address Set instruction. After writing operation, the address is automatically increased by 1.
READ DATA
RS 1 DB7 D7 DB6 D6 DB5 D5 DB4 D4 DB3 D3 DB2 D2 DB1 D1 DB0 D0
DDRAM / CGRAM / ICONRAM data read instruction. Each RAM is selected by address set instruction. And then you can read the RAM data. You can get correct RAM data from second read transaction. The first read data after setting RAM address is dummy data, so the correct RAM data come from the second read transaction. After reading operation, the address is increased by 1 automatically.
28
80 COM / 26 COM DRIVER & CONTROLLER FOR STN LCD
S6A0092
INITIALIZING & POWER SAVE MODE SETUP
HARDWARE RESET
When RESETB pin = "Low", S6A0092 can be initialized as the following state. (1) Control Display ON / OFF Instruction C = 0: Cursor OFF B = 0: Blink OFF D = 0: Display OFF (2) Power Save Set Instruction OS = 0: Oscillator OFF PS = 0: Power save OFF (3) Power Control Set Instruction VR = 0: Voltage regulator OFF VC = 0: Voltage converter OFF VF = 0: Voltage follower OFF (4) Function Set instruction N = 0: 2 Line display mode S = 0: COM Left shift CG = 0: CGRAM is not used. (5) Return Home Address counter = 00h (6) Electronic Contrast Control Register: 10h = (0, 0, 0, 0, 0) (7) In Case of 4-bit Interface Mode Selection S6A0092 considers the first 4-bit data from MPU as the high order bits. NOTE: If initialization is not done by the RESETB pin at application, unknown condition might result. Then you can initialize by instruction.
VDD
tRESETB
RESETB
tRW RESET pulse width RESET start time tRW tRESETB 10us 50ns
Figure 17. RESET Timing
29
S6A0092
26 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
INITIALIZING AND POWER SAVE SETUP
Initializing by Instruction
VDD-VSS Power ON Keep RESETB Pin = "L" When the power is stable, release the reset state (RESETB = "H"). Waiting for 10us or more Command Input 1. Function Set (N, S, CG) 2. Electronic Volume Register Setup (ICONRAM 10h) 3. Power Save (PS: Power Save OFF, OS: OSC ON) 4. Power Control (VC, VR, VF are all ON) Waiting for 20ms or more Command Input 5. RAM Address Set Command Input 6. Data Writing (RAM Clear) (DDRAM = 20h, CG/ICONRAM = 00h)
NOTE: At command 5 and 6, the internal RAM should be cleared. To clear DDRAM, Set address at 00h (first DDRAM) and then write 20h (space character code) 64 times To clear CGRAM, set address at 40h (first
CGRAM) and then write 00h (null data) 64 times To clear ICONRAM, set ICONRAM address at 00h (first ICONRAM) and then write 00h (null data) 16 times.
Command Input 7. Display Control (D: ON)
End of Initialization
30
80 COM / 26 COM DRIVER & CONTROLLER FOR STN LCD
S6A0092
Sleep Mode Set or Release by Instruction
a) Sleep Mode Set End of Initialization
Normal Operation Status (Power save is OFF and Oscillator is ON.)
Command Input 1. Display Control (D: OFF) 2. Power Save (PS: Power Save ON, OS: OSC OFF) 3. Power Control (VC, VR, VF are all OFF)
Enter the Sleep Mode
b) Sleep Mode Release Sleep Mode
Command Input 1. Power Save (PS: Power Save OFF, OS: OSC ON) 2. Power Control (VC, VR, VF are all ON)
Waiting for 20ms or more
Command Input 3. Display Control (D: ON)
Return to Normal Operation
31
S6A0092
26 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
Recommendation of Power ON / OFF Sequence
a) Power ON Sequence Power ON
Voltage Converter ON [VC, VR, VF = 1, 0, 0] Waiting for 1ms Voltage Regulator ON [VC, VR, VF = 1, 1, 0] Waiting for 1ms Voltage Follower ON [VC, VR, VF = 1, 1, 1]
Operation Command Input
b) Power OFF Sequence Operation Command Input
Display OFF
Voltage Regulator OFF [VC, VR, VF = 1, 0, 1] Waiting for 50ms Voltage Follower OFF [VC, VR, VF = 1, 0, 0] Waiting for 1ms Voltage Converter OFF [VC, VR, VF = 0, 0, 0] Waiting for 1ms Operation Command Input
32
80 COM / 26 COM DRIVER & CONTROLLER FOR STN LCD
S6A0092
LCD DRIVING POWER SUPPLY CIRCUIT
The Power Supply circuit produces LCD panel driving voltage at low power consumption. The LCD Driving Power Supply circuit consists of Voltage converter, Voltage regulator, and Voltage follower. It is controlled by power control instruction. Table 14 shows how the LCD Driving Power Supply circuit works by power control instruction sets.
Table 14. Power Supply Control Mode Set VC VR VF Voltage Converter Enable Voltage regulator Enable Voltage follower Enable VOUT pin Internal voltage output External voltage input Open VR pin Used for voltage adjustment Used for voltage adjustment Open V0, V1, V2, V3, V4 pin Internal voltage output
111
Internal voltage output
011
Disable
Enable
Enable
001
Disable
Disable
Enable
V1V4: internal voltage output V0: external voltage input V0V4: external voltage input
000
Disable
Disable
Disable
Open
Open
NOTE: Any other case which is not written in this table is prohibited.
33
S6A0092
26 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
VOLTAGE CONVERTER
The Voltage Converter circuit generates positive 4 times voltage of 1.8V that is generated internally. VOUT is generated from the voltage converter. And this conversion voltage is used in the built-in Voltage Regulator circuit. This application circuit is same as 3 times DC/DC converter.
VOUT
VDD
S6A0092 VDD
+
+ -
CAP1+ CAP1CAP2+ CAP2VOUT
4 x 1.8V = 7.2V
+
1.8V (Internal) VSS
-
Figure 18. DC/DC Converter Output and Circuit
34
80 COM / 26 COM DRIVER & CONTROLLER FOR STN LCD
S6A0092
VOLTAGE REGULATOR
The Voltage Regulator circuit is used to obtain an appropriate LCD panel driving voltage. This voltage is obtained by adjusting resistors Ra and Rb as shown in equation (1) or (2), and by setting Electronic Contrast Control data bits, see equation (3) or (4). The potential of V0 Pin can be adjusted within VOUT - VREF. VREF is the internal constant voltage source of the chip and this value is 2.0V in the condition VDD 2.4V The REF selects which voltage is used for voltage regulator between the external VEXT and the internal VREF. Voltage regulation by adjusting resistors Ra, Rb When REF is "Low" Rb V0 = ( 1 + Ra ) x VREF --- (1) V0 = ( 1 + Ra When REF is "High" Rb ) x VEXT --- (2)
The internal VREF of voltage regulator has the temperature compensation function, and the temperature coefficient is about 0.0%/C.
Rb VOUT VR
_ +
V0
Ra
VEXT VREF
REF
Inside Chip
VSS GND Figure 19. Voltage Regulator Circuit
35
S6A0092
26 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
ELECTRONIC CONTRAST CONTROL (32 STEPS)
Electronic Contrast Control data bits is 10h = (C4, C3, C2, C1, C0). Voltage regulation is adjusted as 32-contrast step according to the value of Electronic Contrast Control data bits. LCD drive voltage V0 has one of 32 voltage values if 5-bit data is set to the electronic contrast control register (ICONRAM address 10h). When using the electronic contrast control function, you need to turn the voltage regulators on using power control instruction.
When REF = "Low" Rb V0 = ( 1 + Ra VEV = VREF - n (n = 0, 1, 2, ..., 30, 31) = VREF / 150 ) x VEV --- (3)
When REF = "High" Rb V0 = ( 1 + Ra VEV = VEXT - n (n = 0, 1, 2, ..., 30, 31) = VEXT / 150 ) x VEV --- (4)
Table 15. Electronic Contrast Control Register No. 1 2 3 4 . . . 31 32 C7 . . . C6 . . . C5 . . . C4 0 0 0 0 . . . 1 1 C3 0 0 0 0 . . . 1 1 C2 0 0 0 0 . . . 1 1 C1 0 0 1 1 . . . 1 1 C0 0 1 0 1 . . . 0 1 n 0 (default) 1 2 3 . . . 30 31 V0 Maximum . . . . . . . Minimum Contrast High . . . . . . . Low
("-" Dont care )
36
80 COM / 26 COM DRIVER & CONTROLLER FOR STN LCD
S6A0092
Rb VOUT VR
_ +
V0
Ra
VEXT VREF + VEV
-
REF
Inside Chip
VSS GND Figure 20. Electronic Contrast Control Circuit
37
S6A0092
26 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
VOLTAGE GENERATOR CIRCUIT
VDD VDD + C1 C1 CAP1+ CAP1CAP2+ CAP2VOUT
C1
VR
Rb Ra
GND C2 C2 C2 C2 C2 C3 +
+
V0 V1 V2 V3 V4 VSS
GND
C1: 0.1 ~ 4.7uF C2: 0.1 ~ 4.7uF C3: 1 ~ 10nF
Figure 21. When Built-in Power Supply is used (VC, VR, VF = 1, 1, 1)
VDD VDD CAP1+ CAP1CAP2+ CAP2VOUT
VDD VDD CAP1+ CAP1CAP2+ CAP2VOUT
VDD VDD CAP1+ CAP1CAP2+ CAP2VOUT
External Power Supply
GND
VR
VR
VR
Rb Ra
GND C2 C2 C2 C2 C2 -+
V0 V1 V2 V3 V4 VSS
External Power Supply
-+
V0 V1 V2 V3 V4 VSS
External Power Supply
V0 V1 V2 V3 V4 VSS
GND
GND
GND
(VC, VR, VF = 0, 1, 1)
(VC, VR, VF = 0, 0, 1)
(VC, VR, VF = 0, 0, 0) All capacitor is C2. C2: 0.1 ~ 4.7uF
Figure 22. When External Power Supply is used
38
80 COM / 26 COM DRIVER & CONTROLLER FOR STN LCD
S6A0092
MPU INTERFACE
VCC
A0 A1-A7 IORQ Decoder
RS CSB
VDD PS
S6A0092
E_RD RW_WR DB[0:7] RESETB RESETB IF VSS MI
MPU
RD WR D0-D7 GND RES
Figure 23. Parallel Interfacing with 8080-series Microprocessors
VCC
A0 A1-A7 VMA Decoder
RS CSB
VDD PS
S6A0092
RW_WR E_RD DB[0:7] RESETB RESETB IF VSS MI
MPU
R/W E D0-D7 GND RES
Figure 24. Parallel Interfacing with 6800-series Microprocessors
39
S6A0092
26 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
VCC
PORT4 PORT3
RS CSB
VDD VDD or VSS
S6A0092
MPU
PORT1 PORT2 GND RES RESETB SCL(DB6) SI(DB7) RESETB VSS
MI IF E_RD RW_WR PS
Figure 25. Clock Synchronized Serial Interfacing with any Microprocessors
40
80 COM / 26 COM DRIVER & CONTROLLER FOR STN LCD
S6A0092
APPLICATION INFORMATION FOR LCD PANEL
Chip Bottom & Lower View (S bit = "0", DIRS = "0")
Chip Bottom & Upper View (S bit = "1", DIRS = "1")
C C C C C C C C C C C C C OM9 OM10 OM11 OM12 OM13 OM14 OM15 OM16 OM21 OM22 OM23 OM24 OMI2 COMI1 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM17 COM18 COM19 COM20
..................... ..................... ....... ........
SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG76 SEG77 SEG78 SEG79 SEG80 C C C C C C C C C C C C C O O O O O O O O O O O O O M20 M19 M18 M17 M8 M7 M6 M5 M4 M3 M2 M1 M I1
................................................
B O T T O M V IE W
C O M I2 COM24 COM23 COM22 COM21 COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9
.... ........... ........... .... ....... .....................
.... ............ ............
B O T T O M V IE W
SEG80
SEG79
SEG78
SEG77
SEG76
SEG75
SEG74
SEG73
SEG72
SEG71
SEG5
SEG4
SEG3
SEG2
SEG1
....
................................................
........ .....................
41
S6A0092
26 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
Chip Top & Lower View (S bit = "0", DIRS = "1")
.....................
Chip Top & Upper View (S bit = "1", DIRS = "0")
C O M I1 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM17 COM18 COM19 COM20 C C C C C C C C C C C C C O O O O O O O O O O O O O M I2 M24 M23 M22 M21 M16 M15 M14 M13 M12 M11 M10 M9
..................... ....... ........
SEG80 SEG79 SEG78 SEG77 SEG76 SEG75 SEG74 SEG73 SEG72 SEG71 SEG5 SEG4 SEG3 SEG2 SEG1 C C C C C C C C C C C C C O O O O O O O O O O O O O M I2 M24 M23 M22 M21 M16 M15 M14 M13 M12 M11 M10 M9
................................................
C C C C
TOP
V IE W
OM20 OM19 OM18 OM17 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 C O M I1
....
.... ............ ........... .... ....... .....................
........... ............
TOP
V IE W
....
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG76
SEG77
SEG78
SEG79
SEG80
................................................
........ .....................
42
80 COM / 26 COM DRIVER & CONTROLLER FOR STN LCD
S6A0092
FRAME FREQUENCY
1/17 DUTY (2-LINE MODE)
1-line selection period 12 V0 V1 . . . . . . 16 17 1 2 . . . . . . 16 17 1 2 . . . . . . 16 17 1 2 . . . . . . 16 17
COM1
V4 VSS 1 Frame 1 Frame
1-line Selection Period = 16 Clocks One Frame = 16 x 17 x 36.8s = 10.0ms (1 Clock = 36.8s at fOSC =27.2kHz) Frame Frequency = 1 / 10.0ms = 100Hz
1/25 DUTY (3-LINE MODE)
1-line selection period 12 V0 V1 ............. 24 25 1 2 ............. 24 25 1 2 . . . . . . . . . .
COM1
V4 VSS 1 Frame 1 Frame
1-line Selection Period = 16 Clocks One Frame = 16 x 25 x 25s = 10.0ms (1 Clock = 25s at fOSC =40kHz) Frame Frequency = 1 / 10.0ms = 100Hz
43
S6A0092
26 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
MAXIMUM ABSOLUTE RATE
Table 16. Maximum Absolute Ratings Characteristic Power supply voltage (1) Power supply voltage (2) Power supply voltage (3) Input voltage Operating temperature Storage temperature Symbol VDD VOUT, V0 V1, V2, V3, V4 VIN TOPR TSTG Value -0.3 to + 7.0 -0.3 to + 8.0 -0.3 to V0 -0.3 to VDD+0.3 -30 to +85 -55 to +125 Unit V V V V
o
C C
o
NOTES: 1. All the voltage levels are based on VSS = 0V. 2. Voltage greater than above may damage the circuit. Voltage level: VOUT V0 VDD VSS 3. Voltage level: V0 V1 V2 V3 V4 VSS
44
80 COM / 26 COM DRIVER & CONTROLLER FOR STN LCD
S6A0092
ELECTRICAL CHARACTERISTICS
DC CHARACTERISTICS
Table 17. DC Characteristics (VDD = 2.4V to 3.6V, Ta = -30 to +85 oC) Item Operating voltage Symbol VDD IDD1 Supply current (VDD = 3V, Ta = 25 C)
o
Condition Display operation VLCD = 6V without load No access from MPU Access operation from MPU (fcyc = 200kHz) Sleep operation without load oscillator OFF, power save ON IOH = -1mA, VDD = 2.4V IOL = 1mA, VDD = 2.4V VIN = 0V to VDD VIN = 0V to VDD Io = 50A Io = 50A VDD = 3V, Ta = 25 oC RL = Ta = 25 oC, C = 1F Ta = 25 oC VLCD = V0 - VSS
Min. 2.4 -
Typ. -
Max. 3.6 80
Unit V
IDD2 IDDS1 VIH
0.7VDD VSS VDD0.4
-
500 5 VDD
A
Input voltage (1) VIL VOH Output voltage VOL Input leakage current Output leakage current RON resistance RSEG Frame frequency (internal OSC) Voltage converter Conversion efficiency Output voltage fFR VEF VOUT VREF VLCD IIZ IOZ RCOM 0.3VDD
V
V 0.4 1 3 100 99 7.2 2.0 5 k 10 130 7.5 2.06 V 6.0 Hz % V A A
-1 -3 70 95 6.9 1.94 4.0
Voltage regulator reference voltage LCD driving voltage NOTE:
1. RESETB pin is schmitt input (0.8VDD VIH VDD, VSS VIL 0.2VDD).
45
S6A0092
26 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
AC CHARACTERISTICS
Parallel Write Interface (68 Mode)
(VDD = 2.4V to 3.6V, Ta = -30 to +85 oC) Characteristic E_RD cycle time Pulse rise / fall time E_RD pulse width high E_RD pulse width low RS and CSB setup time RS and CSB hold time DB setup time DB hold time Symbol tC tR,tF tWH tWL tSU1 tH1 tSU2 tH2 Min. 650 450 150 60 30 100 50 Typ. Max. 25 ns Unit
RS,CSB
tS U 1 tH 1
RW_WR
tW H tF tW L
E_RD
tR tS U 2 t
H2
DB0~DB7
Valid
Data tC
Figure 26. Write Timing Diagram (68-series)
46
80 COM / 26 COM DRIVER & CONTROLLER FOR STN LCD
S6A0092
Parallel Read Interface (68 Mode)
(VDD = 2.4V to 3.6V, Ta = -30 to +85 oC) Characteristic E_RD cycle time Pulse rise / fall time E_RD pulse width high E_RD pulse width low RS and CSB setup time RS and CSB hold time DB output delay time DB output hold time Symbol tC tR,tF tWH tWL tSU tH tD tDH Min. 650 450 150 60 30 100 50 Typ. Max. 25 ns Unit
RS,CSB
tSU tH
RW_WR
tW H tF tW L
E_RD
tR tD tDH
DB0~DB7
Valid
Data tC
Figure 27. Read Timing Diagram (68-series)
47
S6A0092
26 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
Parallel Write Interface (80 Mode)
(VDD = 2.4V to 3.6V, Ta = -30 to +85 oC) Characteristic RW_WR cycle time Pulse rise / fall time RW_WR pulse width high RW_WR pulse width low RS and CSB setup time RS and CSB hold time DB setup time DB hold time Symbol tC tR,tF tWH tWL tSU1 tH1 tSU2 tH2 Min. 650 150 450 60 30 100 50 Typ. Max. 25 ns Unit
R S ,CSB
tSU1 tH1
E_RD
tW L tR tW H
RW_WR
tF tSU2 t
H2
DB0~DB7
Valid
Data tC
Figure 28. Write Timing Diagram (80-series)
48
80 COM / 26 COM DRIVER & CONTROLLER FOR STN LCD
S6A0092
Parallel Read Interface (80 Mode)
(VDD = 2.4V to 3.6V, Ta = -30 to +85 oC) Characteristic E_RD cycle time Pulse rise / fall time E_RD pulse width high E_RD pulse width low RS and CSB setup time RS and CSB hold time DB output delay time DB output hold time Symbol tC tR,tF tWH tWL tSU tH tD tDH Min. 650 150 450 60 30 100 50 Typ. Max. 25 ns Unit
R S ,CSB
tSU tH
RW_WR
tW L tR tW H
E_RD
tF tD tDH
DB0~DB7
Valid
Data tC
Figure 29. Read Timing Diagram (80-series)
49
S6A0092
26 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
Clock Synchronized Serial Mode
(VDD = 2.4V to 3.6V, Ta = -30 to +85 oC) Characteristic SCL clock cycle time Pulse rise / fall time SCL clock width (high, low) CSB setup time CSB hold time RS data setup time RS data hold time SI data setup time SI data hold time Symbol tC tR,tF tW tSU1 tH1 tSU2 tH2 tSU3 tH3 Min 1000 300 150 700 50 300 50 50 Typ Max 25 ns Unit
tSU1
tC
tH 1
CSB
tR tW tF tW
SCL
tS U 2
tH 2
RS
tSU3 tH3
SI
Figure 30. Clock Synchronized Serial Interface Mode Timing Diagram
50

▲Up To Search▲

Price & Availability of S6A0092

	To Download S6A0092 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .