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Integrated Circuit Systems, Inc.
ICS97ULP844A
1.8V Low-Power Wide-Range Frequency Clock Driver
Recommended Application: * DDR2 Memory Modules / Zero Delay Board Fan Out * Provides complete DDR DIMM logic solution with ICSSSTU32864/SSTUF32864/SSTUF32866
A
Pin Configuration
1 2 3 4 5
Product Description/Features: * Low skew, low jitter PLL clock driver * 1 to 4 differential clock distribution (SSTL_18) * Feedback pins for input to output synchronization * Spread Spectrum tolerant inputs * Auto PD when input signal is at a certain logic state Switching Characteristics: * Period jitter: 40ps * Half-period jitter: 60ps * CYCLE - CYCLE jitter 40ps * OUTPUT - OUTPUT skew: 40ps
B C D E F
28-Ball BGA
Top View
Block Diagram
CLKT0 OE OS AVDD Powerdown Control and Test Logic PLL bypass LD* or OE CLKC0 CLKT1 CLKC1 CLKT2 LD* CLKC2 CLKT3 CLKC3
Ball Assignments
1 A B C D E F CLKT0 CK_INT CK_INC AGND AVDD CLKC3 2 CLKC0 VDD OE GND GND CLKT3 3 CLKC1 NB VDD VDD NB CLKC2 4 CLKT1 VDD OS GND GND CLKT2 5 FB_INT FB_INC FB_OUTC FB_OUTT GND GND
CLK_INT CLK_INC 10K-100k PLL GND FB_INT FB_INC * The Logic Detect (LD) powers down the device when a logic low is applied to both CLK_INT and CLK_INC.
FB_OUTT FB_OUTC
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ICS97ULP844A
Pin Descriptions
Te r m i n a l Name AGND AVDD CLK_INT CLK_INC FB_INT FB_INC FB_OUTT FB_OUTC OE OS GND VDDQ CLKT[0:3] CLKC[0:3] NB Analog Ground A n a l o g p ow e r Clock input with a (10K-100K Ohm) pulldown resistor Complentar y clock input with a (10K-100K Ohm) pulldown resistor Feedback clock input Complementary feedback clock input Feedback clock output Complementary feedback clock output Output Enable (Asynchronous) Output Select (tied to GND or VDDQ) Ground Logic and output power Clock outputs Complementary clock outputs No ball Description Electrical Characteristics Ground 1.8 V nominal Differential input Differential input Differential input Differential input Differential output Differential output LVCMOS input LVCMOS input Ground 1.8V nominal Differential outputs Differential outputs
The PLL clock buffer, ICS97ULP844A, is designed for a VDDQ of 1.8 V, a AVDD of 1.8 V and differential data input and output levels. Package options include a plastic 28-ball VFBGA. ICS97ULP844A is a zero delay buffer that distributes a differential clock input pair (CLK_INT, CLK_INC) to four differential pair of clock outputs (CLKT[0:3], CLKC[0:3]) and one differential pair feedback clock outputs (FB_OUTT, FBOUTC). The clock outputs are controlled by the input clocks (CLK_INT, CLK_INC), the feedback clocks (FB_INT, FB_INC), the LVCMOS program pins (OE, OS) and the Analog Power input (AVDD). When OE is low, the outputs (except FB_OUTT/FB_OUTC) are disabled while the internal PLL continues to maintain its locked-in frequency. OS (Output Select) is a program pin that must be tied to GND or VDDQ. When OS is high, OE will function as described above. When OS is low, OE has no effect on CLKT2/CLKC2 (they are free running in addition to FB_OUTT/FB_OUTC). When AVDD is grounded, the PLL is turned off and bypassed for test purposes. When both clock signals (CLK_INT, CLK_INC) are logic low, the device will enter a low power mode. An input logic detection circuit on the differential inputs, independent from the input buffers, will detect the logic low level and perform a low power state where all outputs, the feedback and the PLL are OFF. When the inputs transition from both being logic low to being differential signals, the PLL will be turned back on, the inputs and outputs will be enabled and the PLL will obtain phase lock between the feedback clock pair (FB_INT, FB_INC) and the input clock pair (CLK_INT, CLK_INC) within the specified stabilization time tSTAB. The PLL in ICS97ULP844A clock driver uses the input clocks (CLK_INT, CLK_INC) and the feedback clocks (FB_INT, FB_INC) to provide high-performance, low-skew, low-jitter output differential clocks (CLKT[0:4], CLKC[0:4]). ICS97ULP844A is also able to track Spread Spectrum Clocking (SSC) for reduced EMI. ICS97ULP844A is characterized for operation from 0C to 70C.
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ICS97ULP844A
Function Table
Inputs AVDD GND GND GND GND 1.8V(nom) 1.8V(nom) 1.8V(nom) 1.8V(nom) 1.8V(nom) 1.8V(nom) OE H H L L L L H H X X OS X X H L H L X X X X CLK_INT L H L H L H L H L H CLK_INT H L H L H L H L L H CLKT L H *L(Z) *L(Z), CLKT2 active *L(Z) *L(Z), CLKT2 active L H *L(Z) CLKC H L *L(Z) *L(Z), CLKC2 active *L(Z) *L(Z), CLKC2 active H L *L(Z) Outputs PLL FB_OUTT L H L H L H FB_OUTC H L H L Bypassed/Off Bypassed/Off Bypassed/Off Bypassed/Off
H L
On On
L H *L(Z) Reser ved
H L *L(Z)
On On Off
*L(Z) means the outputs are disabled to a low stated meeting the IODL limit.
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ICS97ULP844A
Absolute Maximum Ratings
Supply Voltage (VDDQ & AVDD) . . . . . . . . . Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . Ambient Operating Temperature . . . . . . . . . . Storage Temperature . . . . . . . . . . . . . . . . . . . -0.5V to 2.5V GND - 0.5V to VDDQ + 0.5V 0C to +70C -65C to +150C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage AVDDQ, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated) SYMBOL MIN TYP PARAMETER CONDITIONS Input High Current IIH VI = VDDQ or GND (CLK_INT, CLK_INC) Input Low Current (OE, IIL VI = VDDQ or GND OS, FB_INT, FB_INC) Output Disabled Low OE = L, VODL = 100mV IODL 100 Current IDD1.8 CL = 0pf @ 270MHz Operating Supply Current CL = 0pf IDDLD VDDQ = 1.7V Iin = -18mA VIK Input Clamp Voltage VDDQ - 0.2 IOH = -100 A VOH High-level output voltage IOH = -9 mA 1.1 1.45 IOL=100 A 0.25 VOL Low-level output voltage IOL=9 mA 1 CIN VI = GND or VDDQ 2 Input Capacitance 1 COUT 2 VOUT = GND or VDDQ Output Capacitance
1
MAX 250 10
UNITS A A A
TBD 500 -1.2
0.10 0.6 3 3
mA A V V V V V pF pF
Guaranteed by design, not 100% tested in production.
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ICS97ULP844A
Recommended Operating Condition (see note1)
TA = 0 - 70C; Supply Voltage AVDD, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated) PARAMETER Supply Voltage Low level input voltage SYMBOL V DDQ, AVDD V IL CONDITIONS MIN 1.7 TYP 1.8 MAX 1.9 0.35 x V DDQ 0.35 x V DDQ UNITS V V V V V V DDQ + 0.3 V DDQ + 0.4 V DDQ + 0.4 V DDQ/2 + 0.10 V V V V V mA mA C
High level input voltage DC input signal voltage (note 2) Differential input signal voltage (note 3) Output differential crossvoltage (note 4) Input differential crossvoltage (note 4) High level output current Low level output current Operating free-air temperature
VIH VIN
CLK_INT, CLK_INC, FB_INC, FB_INT OE, OS CLK_INT, CLK_INC, FB_INC, 0.65 x VDDQ FB_INT OE, OS 0.65 x VDDQ -0.3 DC - CLK_INT, CLK_INC, FB_INC, FB_INT AC - CLK_INT, CLK_INC, FB_INC, FB_INT 0.3 0.6 VDDQ/2 - 0.10
VID
VOX VIX IOH IOL TA
VDDQ/2 - 0.15 VDD/2 V DDQ2 + 0.15 -9 9 0 70
Notes: 1. Unused inputs must be held high or low to prevent them from floating. 2. DC input signal voltage specifies the allowable DC execution of differential input. 3. Differential inputs signal voltages specifies the differential voltage [VTR-VCP] required for switching, where VTR is the true input level and VCP is the complementary input level. 4. Differential cross-point voltage is expected to track variations of VDDQ and is the voltage at which the differential signal must be crossing.
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ICS97ULP844A
Timing Requirements
TA = 0 - 70C Supply Voltage AVDD, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated) CONDITIONS PARAMETER SYMBOL MIN TYP Max clock frequency Application Frequency Range Input clock duty cycle CLK stabilization freqop freqApp dtin TSTAB 1.8V+0.1V @ 25C 1.8V+0.1V @ 25C 95 160 40 2.4 MAX 370 350 60 2.95
Switching Characteristics
1
TA = 0 - 70C Supply Voltage AVDD, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated) PARAMETER CONDITION SYMBOL MIN ten Output enable time OE to any output tdis Output disable time OE to any output tjit (per) Period jitter -30 tjit(hper) Half-period jitter -60 1 Input Clock Input slew rate SLr1(i) Output Enable (OE), (OS) 0.5 1.5 Output clock slew rate SLr1(o) tjit(cc+) 0 Cycle-to-cycle period jitter tjit(cc-) 0 t( )dyn Dynamic Phase Offset -20 2 Static Phase Offset -50 tSPO tskew Output to Output Skew SSC modulation frequency 30.00 SSC clock input frequency 0.00 deviation PLL Loop bandwidth (-3 dB 2.0 from unity gain)
TYP 4.73 5.82
2.5 2.5
MAX 8 8 30 60 4 3 40 -40 20 50 50 33 -0.50
0
UNITS ns ns ps ps v/ns v/ns v/ns ps ps ps ps ps kHz % MHz
Notes: 1. Switching characteristics guaranteed for application frequency range. 2. Static phase offset shifted by design.
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ICS97ULP844A
Parameter Measurement Information VDD V(CLKC)
V(CLKC) ICS97ULP844 GND Figure 1. IBIS Model Output Load VDD/2 ICS97ULP844A Z = 60 Z = 2.97" Z = 120 Z = 60 Z = 2.97" C = 10 pF GND -VDD/2 Figure 2. Output Load Test Circuit
R = 1M V(TT) C = 1 pF R = 1M V(TT) C = 1 pF
C = 10 pF - GND R = 10 Z = 50
SCOPE
R = 10
Z = 50
Note: VTT = GND
YX, FB_OUTC YX, FB_OUTT tc(n) tc(n+1) tjit(cc) = tc(n) tc(n+1) Figure 3. Cycle-to-Cycle Jitter
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ICS97ULP844A
Parameter Measurement Information CLK_INC CLK_INT
FB_INC FB_INT
t( ) n
n=N t( ) n 1 t( )= N (N is a large number of samples) Figure 4. Static Phase Offset
t ( ) n+1
YX# YX
YX, FB_OUTC YX, FB_OUTT t(skew) Figure 5. Output Skew
YX, FB_OUTC YX, FB_OUTT YX, FB_OUTC YX, FB_OUTT
tC(n)
1 fO t(jit_per) = tc(n) - 1 fO Figure 6. Period Jitter
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ICS97ULP844A
Parameter Measurement Information YX, FB_OUTC YX, FB_OUTT
t jit(hper_n) 1 fo t jit(hper_n+1)
tjit(hper) = t jit(hper_n)
-
1 2xfO
Figure 7. Half-Period Jitter
80%
80% VID, VOD
Clock Inputs and Outputs
20% tslr tslf
20%
Figure 8. Input and Output Slew Rates
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ICS97ULP844A
CK CK FBIN FBIN
t(
SSC OFF SSC ON
)
SSC ON
t(
SSC OFF
)
t(
)dyn
t(
)dyn
t(
)dyn
t(
)dyn
Figure 9. Dynamic Phase Offset
50% VDDQ OE t en 50% VDDQ Y/ Y Y Y
OE
50% VDDQ t dis 50 % VDDQ Y
Figure 10. Time delay between OE and Clock Output (Y, Y)
Y
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ICS97ULP844A
Figure 11. AVDD Filtering
- Place the 2200pF capacitor close to the PLL. - Use a wide trace for the PLL analog power & ground. Connect PLL & caps to AGND trace & connect trace to one GND via (farthest from PLL). - Recommended bead: Fair-Rite P/N 2506036017Y0 or equivalent (0.8 Ohm DC max, 600 Ohms @ 100 MHz).
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ICS97ULP844A
SYMBOL A A1 A2 A3 b D D1 E E1 e
MIN 0.80 0.165 0.16 0.475 0.35 3.90 4.40
Millimeter NOM 0.90 0.20 0.20 0.50 0.40 4.00 2.60 BSC 4.50 3.25 BSC 0.65 BSC
MAX 1.00 0.235 0.24 0.525 0.45 4.10 4.60
MIN 0.031 0.006 0.006 0.019 0.014 0.154 0.173
Inch NOM 0.035 0.008 0.008 0.020 0.016 0.157 0.102 BSC 0.177 0.128 BSC 0.026 BSC
MAX 0.039 0.009 0.009 0.021 0.018 0.161 0.181
Ordering Information
ICS97ULP844AH(LF)-T
Example:
ICS XXXX y H (LF)- T
Designation for tape and reel packaging RoHS Compliant (Optional) Package Type H = BGA Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device
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