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| (R) ISL6729 Data Sheet July 2004 FN9152.1 Low-Cost Single-Ended Current-Mode PWM for Microcontroller Based Power Converters The ISL6729 pulse width modulating (PWM) current mode controller is designed for power conversion applications that are based on a microcontroller or other device which can generate a digital clock signal at the desired switching frequency. Similar to the ISL684x family of products, the ISL6729 provides the basic current mode PWM control features, but eliminates the error amplifier, the oscillator, and the reference. An external clock signal applied to the oscillator input provides the time base and sets the maximum duty cycle. The reduced feature set is ideal for those applications where a microcontroller is available to provide the monitor and control functions. The analog PWM provides the cycle by cycle peak current mode control, leaving the monitor and control overhead to the microcontroller. Features * 5V Operation * 1A MOSFET gate driver * 400A startup current * 30ns propagation delay current sense to output * Fast transient response with peak current mode control * Switching frequency to 2MHz * 20ns rise and fall times with 1nF output load * Maximum Duty Cycle Determined by Clock Input Duty Cycle * Tight tolerance current limit threshold * Pb-free available Applications * Telecom and Datacom Power * Wireless Base Station Power Ordering Information PART NUMBER ISL6729IB ISL6729IBZ (See Note) ISL6729IU ISL6729IUZ (See Note) TEMP. RANGE (C) -40 to 105 -40 to 105 -40 to 105 -40 to 105 PACKAGE 8 Ld SOIC 8 Ld SOIC (Pb-free) 8 Ld MSOP 8 Ld MSOP (Pb-free) PKG. DWG. # M8.15 M8.15 M8.118 M8.118 * File Server Power * Industrial Power Systems * PC Power Supplies * Isolated Buck and Flyback Regulators * Boost Regulators Pinout ISL6729 (8-PIN SOIC, MSOP) TOP VIEW COMP N/C CS CLKS 1 2 3 4 8 7 6 5 N/C VDD OUT GND Add -T to part number for Tape and Reel packaging. NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which is compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J Std-020B. PART NUMBER ISL6729 RISING UVLO 4.75V MAX. DUTY CYCLE 100% 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2004 All Rights Reserved. All other trademarks mentioned are the property of their respective owners. Functional Block Diagram VDD START/STOP UV COMPARATOR VDDOK + - 2 BG GND CS COMP CLK + - 100mV + - PWM COMPARATOR + 2R R OUT ISL6729 1.1V CLAMP SQ RQ Typical Application - Interleaved Multi-Phase Isolated Converter VOLTAGE FEEDBACK 5V 1 COMP 2 8 POWER STAGE ISOLATION ERROR AMPLIFIER VDD 7 OUT 6 3 CLOCK 1 CLOCK 2 MICROCONTROLLER CLOCK 3 3 CS VOUT 4 CLK GND 5 ISL6729 CURRENT FEEDBACK 1 COMP 2 3 CS 8 POWER STAGE VDD 7 OUT 6 ISL6729 4 CLK GND 5 ISL6729 CURRENT FEEDBACK 1 COMP 2 8 POWER STAGE VDD 7 3 CS OUT 6 4 CLK GND 5 ISL6729 CURRENT FEEDBACK ISL6729 Absolute Maximum Ratings Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +6.5V OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to VDD + 0.3V Signal Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 6.5V Peak GATE Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1A ESD Classification Human Body Model (Per MIL-STD-883 Method 3015.7) . . .2000V Charged Device Model (Per EOS/ESD DS5.3, 4/14/93) . . .1000V Thermal Information Thermal Resistance (Typical, Note 1) JA (C/W) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 MSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Maximum Junction Temperature . . . . . . . . . . . . . . . . -55C to 150C Maximum Storage Temperature Range . . . . . . . . . . . -65C to 150C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300C (SOIC- Lead Tips Only) Operating Conditions Temperature Range ISL6729Ix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40C to 105C Supply Voltage Range (Typical) ISL6729 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.75V-5.25V CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 2. All voltages are with respect to GND. Electrical Specifications PARAMETER UNDERVOLTAGE LOCKOUT START Threshold STOP Threshold Hysteresis Start-Up Current, IDD Operating Current, IDD Operating Supply Current, ID CURRENT SENSE Input Bias Current CS Offset Voltage Recommended operating conditions unless otherwise noted. Refer to Block Diagram and Typical Application schematic. VDD = 5V, CLK = 50kHz, TA = -40 to 105C (Note 3), Typical values are at TA = 25C TEST CONDITIONS MIN TYP MAX UNITS 4.15 4.00 VDD < START Threshold (Note 4) Includes 1nF GATE loading - 4.50 4.30 0.2 420 3.3 4.1 4.75 4.60 800 5.5 6.0 V V A mA mA VCS = 1V VCS = 0V (Note 5) VCS = 0V (Note 5) -1.0 95 0.80 0.91 100 1.15 0.97 3.0 25 1.0 105 1.30 1.03 3.5 40 A mV V V V/V ns COMP to PWM Comparator Offset Voltage CS Input Signal, Maximum Gain, ACS = VCOMP/VCS CS to OUT Delay CLOCK Input High Voltage Level, VIH Input Low Voltage Level, VIL Maximum Clock Rate OUTPUT Gate VOH Gate VOL Peak Output Current Rise Time Fall Time 0 < VCS < 910mV, VFB = 0V. (Note 5) (Note 5) 2.5 - (Note 5) 2 2.8 2.7 - - V V MHz VDD - OUT, IOUT = -200mA OUT - GND, IOUT = 200mA COUT = 1nF (Note 5) COUT = 1nF (Note 5) COUT = 1nF (Note 5) 1.0 - 1.0 1.0 20 20 2.0 2.0 40 40 V V A ns ns 4 ISL6729 Electrical Specifications PARAMETER PWM Maximum Duty Cycle Minimum Duty Cycle NOTES: 3. Specifications at -40C are guaranteed by design, not production tested. 4. This is the VDD current consumed when the device is active but not switching. Does not include gate drive current. 5. Guaranteed by design, not 100% tested in production. 99 0 % % Recommended operating conditions unless otherwise noted. Refer to Block Diagram and Typical Application schematic. VDD = 5V, CLK = 50kHz, TA = -40 to 105C (Note 3), Typical values are at TA = 25C (Continued) TEST CONDITIONS MIN TYP MAX UNITS Pin Descriptions CLK - This is the oscillator timing control pin. The operational frequency and maximum duty cycle are set by applying a 5V amplitude clock signal to CLK. The logic high duration defines the maximum ON time for the output. A maximum clock rate up to 2.0MHz is possible. COMP - COMP is the input to the PWM comparator and is typically controlled through an external error amplifier. CS - This is the current sense input to the PWM comparator. The range of the input signal is nominally 0 to 1.0V and has an internal offset of 100mV. GND - GND is the power and small signal reference ground for all functions. OUT - This is the drive output to the power switching device. It is a high current output capable of driving the gate of a power MOSFET with peak currents of 1.0A. This GATE output is actively held low when VDD is below the UVLO threshold. VDD - VDD is the 5V power connection for the IC. The IC will operate from 4.75V to 5.25V. However, the accuracy of the voltage clamp on the COMP signal, which determines the over current threshold, is dependent on the accuracy of VDD. A tight tolerance on VDD will result in a tight over current threshold. The total supply current will depend on the load applied to OUT. Total IDD current is the sum of the operating current and the average output current. Knowing the operating frequency, f, and the MOSFET gate charge, Qg, the average output current can be calculated from: I OUT = Qg x f (EQ. 1) Ground Plane Requirements Careful layout is essential for satisfactory operation of the device. A good ground plane must be employed. A unique section of the ground plane must be designated for high di/dt currents associated with the output stage. VDD should be bypassed directly to GND with good high frequency capacitors. Applications Information Microcontrollers are becoming more popular for monitoring and supervisory functions in power converters due to their flexibility, capability, and declining prices. Many applications would like to take advantage of this flexibility and use them to perform the control loop function as well. There are many examples of voltage mode control using digital signal processing techniques. However, microcontrollers available today do not have the execution speed required for peak current mode control at the operational frequencies of modern switch-mode power supplies. As such, they are unable to detect the peak current and terminate the switching cycle within the few nanosecond window required. The ISL6729 provides the analog circuitry required to perform peak current control, but delegates the oscillator function to the microcontroller. This arrangement allows the microcontroller to control soft-start, maximum duty cycle, and operational frequency of the power converter, as well as performing the traditional overhead functions such as fault monitoring and system interface. Application of the ISL6729 is similar to the ISL684x family of PWM converters except that the input bias voltage has been changed to 5V and the oscillator, reference, and error amplifier functions have been removed. An external digital clock signal, such as the PWM output of a microcontroller, must be supplied to control the frequency and maximum duty cycle. The frequency of the applied clock signal and the frequency of operation of the PWM are identical. The duty cycle of the clock is the maximum duty cycle of the PWM. Soft-start may be accomplished by incrementing the duty cycle of the applied clock signal from zero to the maximum desired value in a time frame appropriate for the application. To optimize noise immunity, bypass VDD to GND with a ceramic capacitor as close to the VDD and GND pins as possible. 5 ISL6729 The Typical Application block diagram illustrates how the ISL6729 may be used for an interleaved power converter. In this example, three clock signals of equal duty cycle, but phased 120 apart, are applied to separate power stages. Each phase shares a common voltage feedback signal, but uses separate current feed back signals from each power stage for regulation. Excellent current sharing behavior is assured since each phase must produce the same peak current. Accuracy is determined by the variation of the output inductor value and the feedback components. Multiple output power supplies can be created in a similar fashion. Only one clock signal is required if in-phase operation is desired. Each stage may be independently controlled using separate voltage and current feedback loops. 6 ISL6729 Small Outline Plastic Packages (SOIC) N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45o H 0.25(0.010) M BM M8.15 (JEDEC MS-012-AA ISSUE C) 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A L MILLIMETERS MIN 1.35 0.10 0.33 0.19 4.80 3.80 MAX 1.75 0.25 0.51 0.25 5.00 4.00 NOTES 9 3 4 5 6 7 8o Rev. 0 12/93 MIN 0.0532 0.0040 0.013 0.0075 0.1890 0.1497 MAX 0.0688 0.0098 0.020 0.0098 0.1968 0.1574 A1 B C D E A1 0.10(0.004) C e H h L N 0.050 BSC 0.2284 0.0099 0.016 8 0o 8o 0.2440 0.0196 0.050 1.27 BSC 5.80 0.25 0.40 8 0o 6.20 0.50 1.27 e B 0.25(0.010) M C AM BS NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 7 ISL6729 Mini Small Outline Plastic Packages (MSOP) N M8.118 (JEDEC MO-187AA) 8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE E1 E INCHES SYMBOL MIN 0.037 0.002 0.030 0.010 0.004 0.116 0.116 MAX 0.043 0.006 0.037 0.014 0.008 0.120 0.120 MILLIMETERS MIN 0.94 0.05 0.75 0.25 0.09 2.95 2.95 MAX 1.10 0.15 0.95 0.36 0.20 3.05 3.05 NOTES 9 3 4 6 7 15o 6o Rev. 2 01/03 INDEX AREA -B12 TOP VIEW 0.25 (0.010) GAUGE PLANE SEATING PLANE -C4X R1 R 0.20 (0.008) ABC A A1 A2 b c D E1 4X L L1 e E L 0.026 BSC 0.187 0.016 0.199 0.028 0.65 BSC 4.75 0.40 5.05 0.70 A A2 A1 -He D b 0.10 (0.004) -A0.20 (0.008) C SEATING PLANE L1 N R 0.037 REF 8 0.003 0.003 5o 0o 15o 6o 0.95 REF 8 0.07 0.07 5o 0o C a C L E1 C R1 0 SIDE VIEW -B- 0.20 (0.008) CD END VIEW NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-187BA. 2. Dimensioning and tolerancing per ANSI Y14.5M-1994. 3. Dimension "D" does not include mold flash, protrusions or gate burrs and are measured at Datum Plane. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E1" does not include interlead flash or protrusions and are measured at Datum Plane. - H - Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. Formed leads shall be planar with respect to one another within 0.10mm (0.004) at seating Plane. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension "b" does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of "b" dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Datums -A -H- . and - B - to be determined at Datum plane 11. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 8 |
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