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TE CH
T15L256A
SRAM
FEATURES
* Access time: 35ns/70ns * Low power consumption : Active 200 mW(typ.) * Low operating current : 50mA * Single + 3.3V power supply * Fully static operation - No clock or refreshing required * All inputs and outputs directly LVTTL compatible * Common I/O capability * Available packages : 28-pin 300 mil SOJ, 28-pin SOP, TSOP-I (forward type ). * Output enable (OE ) available for very fast access
32K X 8 LOW POWER CMOS STATIC RAM
GENERAL DESCRIPTION
The T15L256A is a high speed, low power CMOS static RAM organized as 32,768 x 8 bits that operates on a single 3.3-volt power supply. This device is packaged in standard 28-pin 300 mil SOJ , 28-pin SOP, TSOP-I forward.
BLOCK DIAGRAM
Vcc
Vss
A0 A14 CS OE CONTROL WE I / O1
. .
. . .
DECODER
CORE ARRAY
PIN CONFIGURATION
A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O3 Vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 Vcc WE A13 A8 A9 A11 OE A10 CS I/O8 I/O7 I/O6 I/O5 I/O4
DATA I/O
I / O8
SOJ & SOP
23 22 21 20 19 18 17 16 15
PIN DESCRIPTION
SYMBOL A0 - A14 I/O1 - I/O8
CS
WE OE
28 27 26 25 24 23 22 21 20 19 18 17 16 15 A10 CS I/O8 I/O7 I/O6 I/O5 I/O4 VSS I/O3 I/O2 I/O1 A0 A1 A2
OE A11 A9 A8 A13 WE VCC A14 A12 A7 A6 A5 A4 A3
1 2 3 4 5 6 7 8 9 10 11 12 13 14
Vcc Vss
DESCRIPTION Address Inputs Data Inputs/Outputs Chip Select Inputs Write Enable Output Enable Power Supply Ground
PART NUMBER EXAMPLES
T15L256A-35J T15L256A-70P T15L256A-70D PACKAGE SOJ TSOP-I SOP SPEED 35ns 70ns 70ns
TSOP-I
Taiwan Memory Technology, Inc. reserves the right to change products or specifications without notice.
P. 1
Publication Date: APR. 2001 Revision:C
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TE CH
T15L256A
DC CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS
PARAMETER Supply Voltage to Vss Potential Inputs to Vss Potential Power Dissipation Storage Temperature RATING -0.5 to + 4.6 -0.5 to Vcc +0.5 0.5 -60 to +150 UNIT V V W C
RECOMMENDED OPERATING CONDITIONS
PARAMETER Supply Voltage Input Voltage, low Input Voltage, high Ambient Temperature SYM Vcc MIN Typ-5% -0.3 2.1 0 TYP 3.3 MAX Typ+5% 0.8 Vcc+0.3 70 UNIT V V V C
VIL VIH TA
TRUTH TABLE
CS H L L L OE X H L X WE X H H L MODE Not Selected Output Disable Read Write I/O1- I/O8 High-Z High-Z Data Out Data In Vcc ISB, I SB1 Icc Icc Icc
OPERATING CHARACTERISTICS
(Vcc = 3.3V 5%, Vss = 0V, Ta = 0 to 70 C)
PARAMETER Input Leakage Current Output Leakage Current Output Low Voltage Output High Voltage Operating Power Supply Current Standby Power Supply Current SYM. TEST CONDITIONS Vin=Vss to Vcc VI/O=Vss to Vcc , MIN. -10 -10 2.4 -35 -70 TYP. MAX. UNIT +10 uA +10 uA 0.4 40 35 8 0.8 V V mA mA mA mA
I LI I LO VOL VOH
Icc
CS = VIH
or OE = VIH or WE = VIL I OL = + 8.0mA I OH = - 4.0mA CS = VIL, I/O=0mA Cycle = MIN. Duty = 100%
ISB I SB1
CS = VIH , Cycle=MIN, Duty=100%
CS Vcc -0.2V,f=0MHz
Note: Typical characteristics are at Vcc = 3.3V, Ta = 25C
Taiwan Memory Technology, Inc. reserves the right to change products or specifications without notice.
P. 2
Publication Date: APR. 2001 Revision:C
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TE CH
T15L256A
CAPACITANCE
(Vcc = 3.3V, Ta = 25 C, f = 1 MHz)
PARAMETER Input Capacitance Input/ Output Capacitance SYMBOL CONDITION VIN = 0V VOUT= 0V MAX. 6 8 UNIT pF pF
CIN CI /O
Note: These parameters are sampled but not 100% tested.
AC TEST CONDITIONS
PARAMETER Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Level Output Load CONDITIONS 0V to 3V 3 ns 1.5V C L =30pF,I OH / I OL = -4mA/8mA
AC TEST LOADS AND WAVEFORM
DQ Z0 = 50 ohm Fig.1 R1 320 ohm 3.3V OUTPUT 30pF Including Jig and Scope Fig.2 3.0V 90% 0V 3ns Fig.5 10% 10% 3ns R2 350 ohm 5pF Including Jig and Scope R2 350 ohm 50 ohm Vt =1.5V 30 pF DQ Z0 = 50 ohm Fig.3 R1 320 ohm 50 ohm Vt =1.5V 5 pF
3.3V OUTPUT
Fig.4 (For TCLZ, TOLZ, TCHZ , TOHZ, TWHZ, TOW )
90%
Taiwan Memory Technology, Inc. reserves the right to change products or specifications without notice.
P. 3
Publication Date: APR. 2001 Revision:C
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TE CH
T15L256A
AC CHARACTERISTICS
(Vcc =3.3V 5%, Vss = 0V, Ta = 0 to 70 C)
(1) READ CYCLE
PARAMETER Read Cycle Time Address Access Time Chip Select Access Time Output Enable to Output Valid Chip Selection to Output in Low Z Output Enable to Output in Low Z Chip Deselection to Output in High Z Output Disable to Output in High Z Output Hold from Address Change SYM.
T RC TAA
TACS
T15M256A-35 MIN. MAX. 35 3 0 3 35 35 25 25 25 -
T15M256A-70 MIN. MAX. 70 3 0 3 70 70 35 35 35 -
UNIT ns ns ns ns ns ns ns ns ns
TAOE
T
CLZ *
T OLZ
T
CHZ *
TOHZ
TOH
* These parameters are sampled but not 100% tested.
(2)WRITE CYCLE
PARAMETER Write Cycle Time Chip Selection to End of Write Address Valid to End of Write Address Setup Time Write Pulse Width Write Recovery Time Data Valid to End of Write Data Hold from End of Write Write to Output in High Z Output Disable to Output in High Z Output Active from End of Write SYM.
TWC
TCW
T15M256A-35 MIN. MAX. 35 30 30 0 25 0 20 0 0 10 10 -
T15M256A-70 MIN. MAX. 70 60 60 0 50 0 30 0 0 25 25 -
UNIT ns ns ns ns ns ns ns ns ns ns ns
TAW TAS
TWP TWR
TDW TDH TWHZ TOHZ TOW

* These parameters are sampled but not 100% tested.
Taiwan Memory Technology, Inc. reserves the right to change products or specifications without notice.
P. 4
Publication Date: APR. 2001 Revision:C
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(Address
TE CH
T15L256A
TIMING WAVEFORMS READ CYCLE 1
Controlled)
tR C
A ddre ss
t tO H AA t OH
DOUT
READ CYCLE 2
(Chip Select
CS
tA C S t CLZ tC H Z
Controlled)
DOUT
READ CYCLE 3
(Output Enable Controlled)
t RC
A dd re ss
t AA
OE
t A OE t OL Z t OH
CS
t ACS t OH Z
t CLZ
tC H Z
DOUT
DON 'T CAR E UN DEF IN ED
Taiwan Memory Technology, Inc. reserves the right to change products or specifications without notice.
P. 5
Publication Date: APR. 2001 Revision:C
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Addres s
TE CH
T15L256A
WRITE CYCLE 1 ( OE CLOCK)
t WC
t
WR
OE t CW
CS t AW
tW P
WE t t AS O HZ (1, 4) D OU T t DW t DH
DI N
WRITE CYCLE 2
( OE = V
IL
Fixed)
t WC
Ad dres s
t CW t WR
CS
t AW
t WP
WE
t
AS
t t WH Z ( 1,4 ) t OW
OH
( 2)
(3 )
DOU T
t DW t DH
DIN
D ON 'T CAR E U N DE F INE D
Taiwan Memory Technology, Inc. reserves the right to change products or specifications without notice.
P. 6
Publication Date: APR. 2001 Revision: C
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TE CH
T15L256A
Notes: 1. During this period, I/O pins are in the output state, so input signals of opposite phase to the outputs should not be applied. 2. The data output from D OUT are the same as the data written to D IN during the write cycle. 3. D OUT provides the read data for the next address. 4. Transition is measured 500 mV from steady state with CL = 5pF. guaranteed but not 100% tested. This parameter is
5. If OE is low during a WE controlled write cycle, the write pulse width must be the larger of tWP or (t WHZ + t DW) to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW . If OE is high during a WE controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t WP .
Taiwan Memory Technology, Inc. reserves the right to change products or specifications without notice.
P. 7
Publication Date: APR. 2001 Revision: C
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TE CH
T15L256A
PACKAGE DIMENSIONS 28-LEAD SOJ SRAM (300 mil)
SYMBOL A B C D E F G H I J K L M N O P Q y
DIMENSIONS IN INCHES 0.7100.002 0.3000.005 0.0600.002 0.0500.001 0.0630.001 0.0150.002 0.0300.002 0.0500.002 0.0180.002 0.0280.002 0.3370.002 0.0100.001 0.0260.002 0.2680.003 0.3000.002 0.0530.001 0.1400.004 0.004(MAX)
DIMENSIONS IN MM 18.030.05 7.620.13 1.520.05 1.270.03 1.630.03 0.380.05 0.760.05 1.270.05 0.460.05 0.710.05 8.560.05 0.250.03 0.660.05 6.810.08 7.620.05 1.350.03 3.560.10 0.10(MAX)
Taiwan Memory Technology, Inc. reserves the right to change products or specifications without notice.
P. 8
Publication Date: APR. 2001 Revision: C
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T15L256A
PACKAGE DIMENSIONS 28-LEAD TSOP-I SRAM (8X13.4mm)
D C 1 28 b E e 14 15 A2 "A" A A1 Seating plane y
Db Gauge plane Seating plane L
0.010
Detail "A"
L1
SYMBOL A A1 A2 b c Db E e D L L1 y
DIMENSIONS IN INCHES 0.047(max.) 0.0040.002 0.039 0.002 0.008(typ.) 0.006(typ.) 0.465 0.004 0.315 0.004 0.022(typ.) 0.528 0.008 0.020 0.004 0.03150.004 0.004(max.) 0 ~5
P. 9
DIMENSIONS IN MM 1.20(max.) 0.100.05 1.000.05 0.20(typ.) 0.15(typ.) 11.80 0.10 8.000.10 0.55(typ.) 13.40 0.20 0.500.10 0.800.10 0.10(max.) 0 ~5
Publication Date: APR. 2001 Revision: C
Taiwan Memory Technology, Inc. reserves the right to change products or specifications without notice.
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TE CH
T15L256A
PACKAGE DIMENSIONS 28-LEAD SOP
e1 28 15
E HE
Detail F 1 D A2 S y Seating Plane Symbol A A1 A2 b C D E e HE L LE S y Dimension in inches min. 0.01 0.083 0.014 0.004 724 0.342 0.044 0.453 0.026 0.047 0 typ. max 0.098 Dimension in mm min. 0.25 2.13 0.39 0.1 18.4 8.7 1.12 11.5 0.65 1.2 0 typ. 2.15 0.4 0.15 18.5 8.8 1.27 11.8 0.85 1.5 1.0 max. 2.5 2.17 0.41 0.2 18.6 8.9 1.42 12.1 1.05 1.8 0.12 10 e A1 See Detail F Notes : 1. Dimensions D max. & S include mold flash or tie bar burrs. 2. Dimension b does not include dambar protrusion / intrusion. 3. Dimensions D & E include mold mismatch and determined at the mold parting line. 4. controlling dimension : inches 5. general appearance spec should be based on final visual inspection spec. A LE b 14 L e1 C
0.085 0.087 0.016 0.018 0.006 0.008 0.728 0.732 0.346 0.350 0.050 0.056 0.465 0.476 0.033 0.041 0.059 0.071 39 0.005 10
Taiwan Memory Technology, Inc. reserves the right to change products or specifications without notice.
P. 10
Publication Date: APR. 2001 Revision: C

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