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SY89200U
Ultra-Precision 1:8 LVDS Fanout Buffer with Three /1//2//4 Clock Divider Output Banks
General Description
The SY89200U is a 2.5V precision, high-speed, integrated clock divider and LVDS fanout buffer capable of handling clocks up to 1.5GHz. Optimized for communications applications, the three independently controlled output banks are phase matched and can be configured for pass through (/1), /2 or /4 divider ratios. The differential input includes Micrel's unique, 3-pin input termination architecture that allows the user to interface to any differential signal path. The low-skew, low-jitter outputs are LVDS-compatible with extremely fast rise/fall times guaranteed to be less than 150ps. The EN (enable) input guarantees that the /1, /2 and /4 outputs will start from the same state without any runt pulse after an asynchronous master rest (MR) is asserted. This is accomplished by enabling the outputs after a fourclock delay to allow the counters to synchronize. The SY89200U is part of Micrel's Precision Edge(R) product family. Datasheets and support documentation can be found on Micrel's web site at: www.micrel.com.
Precision Edge(R)
Features
* Three low-skew LVDS output banks with programmable /1, /2 and /4 divider options * Three independently programmable output banks * Guaranteed AC performance over temperature and voltage: - Accepts a clock frequency up to 1.5GHz - <900ps IN-to-OUT propagation delay - <150ps rise/fall time - <50ps bank-to-bank phase offset * Ultra-low jitter design: - <1psRMS random jitter - <10psPP total jitter (clock) * Patent-pending input termination and VT pin accepts DC- and AC-coupled inputs (CML, PECL, LVDS) * LVDS-compatible outputs * CMOS/TTL-compatible output enable (EN) and divider select control * 2.5V 5% power supply * -40C to +85C temperature range * Available in 32-pin (5mm x 5mm) MLF(R) package
Functional Block Diagram
Applications
* All SONET/SD applications * All Fibre Channel applications * All Gigabit Ethernet applications
Precision Edge is a registered trademark of Micrel, Inc MLF and MicroLeadFrame are registered trademark of Amkor Technology. Micrel Inc. * 2180 Fortune Drive * San Jose, CA 95131 * USA * tel +1 (408) 944-0800 * fax + 1 (408) 474-1000 * http://www.micrel.com
March 2007
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SY89200U
Ordering Information(1)
Part Number SY89200UMI SY89200UMITR SY89200UMG SY89200UMGTR(2)
Note: 1. 2. Contact factory for die availability. Dice are guaranteed at TA = 25C, DC Electricals only. Tape and Reel.
(2)
Package Type MLF-32 MLF-32 MLF-32 MLF-32
Temperature Range Industrial Industrial Industrial Industrial
Package Marking SY89200U SY89200U SY89200U with Pb-Free bar-line indicator SY89200U with Pb-Free bar-line indicator
Lead Finish Sn-Pb Sn-Pb Pb-Free NiPdAu Pb-Free NiPdAu
Pin Configuration
32-Pin MLF(R) (MLF-32)
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SY89200U
Pin Description
Pin Number 3, 6 Pin Name IN, /IN Pin Function Differential Input: This input pair is the differential signal input to the device. This input accepts AC- or DC-coupled signals as small as 100mV. The input pair internally terminates to a VT pin through 50. Note that these inputs will default to an indeterminate state if left open. Please refer to the "Input Interface Applications" section for more details. Single-Ended Inputs: These TTL/CMOS inputs select the device ratio for each of the three banks of outputs. Note that each of these inputs is internally connected to a 25k pull-up resistor and will default to logic HIGH state if left open. The input-switching threshold is VCC/2. Input Termination Center-Tap: Each side of the differential input pair terminates to the VT pin. The VT pin provides a center-tap to a termination network for maximum interface flexibility. See "Input Interface Applications" section for more details. Reference Voltage: This output biases to VCC-1.2V. It is used for AC-coupling inputs IN and /IN. For AC-coupled applications, connect VREF-AC directly to the VT pin. Bypass with 0.01F low ESR capacitor to VCC. Maximum sink/source capability is 0.5mA. Single-Ended Input: This TTL/CMOS input disable and enable the Q0 - Q7 outputs. This input is internally connected to a 25k pull-up resistor and will default to logic HIGH state if left open. The input-switching threshold is VCC/2. For the input enable and disable functional description, refer to Figures 2a through 2c. Bank 1 LVDS differential output pairs controlled by DIVSEL1: LOW Q0 - Q3 = /1 HIGH, Q0 - Q3 = /2. Unused output pairs should be terminated with 100 across the differential pair. Bank 2 LVDS differential output pairs controlled by DIVSEL2: LOW Q4 - Q6 = /2 HIGH, Q4 - Q6 = /2. Unused output pairs should be terminated with 100 across the differential pair. Bank 3 LVDS differential output pairs controlled by DIVSEL3: LOW Q7 = /2 HIGH. Q7 = /2. Unused output pairs should be terminated with 100 across the differential pair. Single-Ended Input: This TTL/CMOS-compatible master reset function asynchronously sets Q0 - Q7 outputs LOW, /Q0 - /Q7 outputs HIGH, and holds them in that state as long as /MR remains LOW. This input is internally connected to a 25k pull-up resistor and will default to a logic HIGH state if left open. The input-switching threshold is VCC/2. Positive power supply. Bypass with 0.1F||0.01F low ESR capacitors. Ground and exposed pad must be connected to the same GND plane on the board.
2 7 8 4
DIVSEL1 DIVSEL2 DIVSEL3 VT
5
VREF-AC
9
EN
30, 29, 28, 27, 26, 25, 24, 23 16, 15, 14, 13, 12, 11 18, 17 32
Q0, /Q0, /Q1, /Q1, Q2, /Q2 Q3, /Q3 Q4, /Q4, Q5, /Q5, Q6, /Q6 Q7, /Q7 /MR
10, 19, 22, 31 1, 20, 21
VCC GND Exposed
Truth Table
/MR(1) 0 1 1 1
Notes: 1. /MR asynchronously forces Q0 - Q7 LOW (/Q0 - /Q7 HIGH). 2. EN forces Q0 - Q7 LOW between 2 and 6 input clock cycles after the falling edge of EN. Refer to "Timing Diagram" section. 3. EN synchronously enables the outputs between two and six input clock cycles after the rising edge of EN. Refer to "Timing Diagram" section.
EN(2,3) X 0 1 1
DIVSEL1 X X 0 1
DIVSEL2 X X 0 1
DIVSEL3 X X 0 1
Q0 - Q3 0 0 /1 /2
Q4 - Q6 0 0 /2 /4
Q7 0 0 /2 /4
March 2007
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SY89200U
Absolute Maximum Ratings(1)
Supply Voltage (VCC).................................... -0.5V to +4.0V Input Voltage (VIN) ............................................ -0.5V to VCC Termination Current(3) Source or sink current on VT .............................100mA Output Current(3) Source or sink current on IN, /IN ........................50mA VREF-AC Current(3) Source or sink current on VREF-AC .........................2mA Lead Temperature (soldering, 20 sec.).................... +260C Storage Temperature (Ts) .........................-65C to +150C
Operating Ratings(2)
Supply Voltage (VCC)............................ +2.375V to +2.625V Ambient Temperature (TA) .......................... -40C to +85C Package Thermal Resistance(4) MLF(R) (JA) Still-Air.........................................................35C/W MLF(R) (JB) Junction -to-Board ......................................20C/W
DC Electrical Characteristics
TA = -40C to +85C, unless otherwise stated.
Symbol VCC ICC RDIFF_IN RIN VIH VIL VIN VDIFF_IN VREF-AC IN-to-VT Parameter Power Supply Power Supply Current Differential Input Resistance (IN-to-/IN) Input Resistance (IN-to-VT, /IN-to-VT) Input High Voltage; (IN, /IN) Input Low Voltage; (IN, /IN) Input Voltage Swing; (IN, /IN) Differential Input Voltage Swing |IN - /IN| Reference Voltage Voltage from Input to VT See Figure 1a. See Figure 1b. No load, max. VCC, Note 6 80 40 1.2 0 100 200 VCC-1.3 VCC-1.2 100 50 Condition Min 2.375 Typ 2.5 Max 2.625 350 120 60 VCC VIH-0.1 VCC 2xVCC VCC-1.1 1.8 Units V mA V V mV mV V V
LVTTL/CMOS DC Electrical Characteristics(5)
VCC = 2.5V 5%; TA = -40C to +85C, unless otherwise stated.
Symbol VIH VIL IIH IIL
Notes: 1. Permanent device damage may occur if ratings in the "Absolute Maximum Ratings" section are exceeded. This is a stress rating only and functional operation is not implied for conditions other than those detailed in the operational sections of this datasheet. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. 2. The datasheet limits are not guaranteed if the device is operated beyond the operating ratings. 3. Due to the limited drive capability use for input of the same package only. 4. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the device's most negative potential on the PCB. JB uses 4-layer JA in still-air, unless otherwise stated. 5. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. 6. Includes current through internal 50 pull-up.
Parameter Input HIGH Voltage Input LOW Voltage Input HIGH Current Input Low Current
Condition
Min 2.0
Typ
Max 0.8
Units V V A A
-125
30 -300
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SY89200U
LVDS OUTPUT DC Electrical Characteristics(7)
VCC = 2.5V 5%; TA = -40C to +85C; RL = 100 across Q and /Q, unless otherwise stated.
Symbol VOH VOL VOUT VDIFF_OUT VOCM VOCM Parameter Output HIGH Voltage; (Q, /Q) Output LOW Voltage; (Q, /Q) Output Voltage Swing; (Q, /Q) Differential Output Voltage Swing |Q - /Q| Output Common Mode Voltage (Q, /Q) Change in Common Mode Voltage (Q, /Q) 0.925 250 500 1.125 -50 350 700 1.275 +50 Condition Min Typ Max 1.475 Units V V mV mV V mV
AC Electrical Characteristics(8)
VCC = 2.5V 5%; TA = -40C to +85C; RL = 100 across all outputs (Q and /Q), unless otherwise stated.
Symbol fMAX tPD tRR tPD Tempco tSKEW Parameter Maximum Operating Frequency Differential Propagation Delay Reset Recovery Time Differential Propagation Delay Temperature Coefficient Within-Bank Skew Bank-to-Bank Skew Bank-to-Bank Skew Part-to-Park Skew tJITTER Random Jitter (RJ) Total Jitter (TJ) Cycle-to-Cycle Jitter tf, tf
Notes: 7. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. 8. Measured with 100mV input swing. See "Timing Diagram" section for definition of parameters. High-frequency AC-parameters are guaranteed by design and characterization. 9. Within-bank is the difference in propagation delays among the outputs within the same bank. 10. Bank-to-bank skew is the difference in propagation delays between outputs from difference banks. Bank-to-bank skew is also the phase offset between each bank after MR is applied. 11. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at the respective inputs. 12. RJ is measured with a K28.7 comma detect character pattern. 13. Total jitter definition: with an ideal clock input of frequency fMAX, no more than one output edge in 10 output edges will deviate by more than the specified peak-to-peak jitter value. 14. Cycle-to-cycle jitter definition: the variation of periods between adjacent cycles, Tn - Tn-1 where T is the time between rising edges of the output signal.
12
Condition VOUT >200mV IN-to-Q /MR-to-Q /MR(L-H)-to-(L-H) Clock
Min 1.5 500
Typ 700
Max 900 900 900
Units GHz ps ps ps fs/C
115 Within same fanout bank, Note 9 Same divide setting, Note 10 Differential divide setting, Note 10 Note 11 Note 12 Note 13 Note 14 20% to 80% at full output swing 40 80 10 15 25 25 35 50 200 1 10 1 150
ps ps ps ps psRMS psPP psRMS ps
Rise/Fall Time
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SY89200U
Single-Ended Differential Swings
Figure 1a. Single-Ended Voltage Swing
Figure 1b. Differential Voltage Swing
Timing Diagram
Figure 2a. Reset with Output Enabled
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SY89200U
Figure 2b. Enable Timing
Figure 2c. Disable Timing
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SY89200U
Typical Operating Characteristics
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SY89200U
Input Stage Internal Termination
Figure 3. Simplified Differential Input Stage
Input Interface Applications
Figure 4a. CML Interface (DC-Coupled)
Figure 4b. CML Interface (AC-Coupled)
Figure 4c. LVPECL Interface (DC-Coupled)
Figure 4d. LVPECL Interface (AC-Coupled)
Figure 4e. LVDS Interface
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SY89200U
Output Interface Applications
LVDS specifies a small swing of 350mV typical, on a nominal 1.25V common mode above ground. The common mode voltage has tight limits to permit large variations in ground between an LVDS driver and receiver. Also, change in common mode voltage, as a function of data input, is kept to a minimum to keep EMI low.
Figure 5b. LVDS Common Mode Measurement
Figure 5a. LVDS Differential Measurement
Related Product and Support Documentation
Part Number HBW Solutions Function MLF Application Note New Products and Applications
(R)
Datasheet Link www.amkor.com/products/notes_papers/MLF_AppNote_0902.pdf www.micrel.com/product-info/products/solutions.shtml
March 2007
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M9999-030707-D hbwhelp@micrel.com or (408) 955-1690
Micrel, Inc.
SY89200U
Package Information
32-Pin MicroLeadFrame(R) (MLF-32)
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http://www.micrel.com
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. (c) 2006 Micrel, Incorporated.
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