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19-3530; Rev 0; 1/05
KIT ATION EVALU LE B AVAILA
Low-Jitter, 8kHz Reference Clock Synthesizer Outputs 35.328MHz
General Description Features
o 8kHz Input-Reference CLK o 4psRMS (typ) Output Jitter o High-Jitter Rejection on the Reference CLK o Synthesizer Locks to the 8kHz Reference with a 100ppm Range o Output Frequency: 35.328MHz o Six Buffered LVTTL Low-Jitter Outputs o One 8kHz Reference CLK Relay Output o +3.3V Supply Operation o 24-Pin TSSOP Package
MAX9476
The MAX9476 low-cost, high-performance clock synthesizer with an 8kHz input reference clock provides six buffered LVTTL clock outputs at 35.328MHz. The clock synthesizer can be used to generate the clocks for systems using T1, E1, T3, E3, and xDSL. The MAX9476 features a phase-lock loop (PLL) that uses a voltage-controlled crystal oscillator (VCXO). The internal PLL phase locks the external crystal (35.328MHz) to the 8kHz input reference clock. In addition, this device generates a jitter-suppressed output that provides a better source for the reference clock relay. The MAX9476 is available in a 24-pin TSSOP package and operates over the extended operating temperature range of -40C to +85C and a single +3V to +3.6V power-supply range. For using lower value external crystals, refer to the MAX9486 data sheet.
Applications
Telecom Equipment Using T1, E1, T3, E3, and ISDN Protocols xDSL Equipment in CO with Interface to the Telecom Protocols
PART MAX9476EUG
Ordering Information
TEMP RANGE -40C to +85C PINPACKAGE 24 TSSOP PKG CODE U24-1
Pin Configuration
TOP VIEW
SHDN 1 REO 2 REIN 3 VDDP 4 GNDP 5 X1 6 VDD 7 X2 8 GND 9 LP2 10 LP1 11 SETI 12 24 CLK1 23 GND 22 CLK2 21 VDD
Typical Application Circuit
R1 C1
C2 LP1 VDDP SETI RSET GNDP VDD SHDN REIN GND LP2 X1 X2 VDD CLK1 CLK2
MAX9476
20 CLK3 19 VDD 18 GND 17 CLK4 16 VDD 15 CLK5 14 GND 13 CLK6
MAX9476
CLK3 CLK4 CLK5 CLK6 REO
TSSOP
________________________________________________________________ Maxim Integrated Products
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Low-Jitter, 8kHz Reference Clock Synthesizer Outputs 35.328MHz MAX9476
ABSOLUTE MAXIMUM RATINGS
VDD to GND ...........................................................-0.3V to +4.0V VDDP to GNDP.......................................................-0.3V to +4.0V SHDN, REO, REIN, X1, X2, CLK_ to GND ...-0.3V to (VDD + 0.3V) LP1, SETI to GNDP.....................................-0.3V to (VDD + 0.3V) LP2 Internally Connected to GNDP Short-Circuit Duration of Outputs ...............................Continuous Continuous Power Dissipation (TA = +70C) 24-Pin TSSOP (derate 12.2mW/C above +70C) .......976mW Operating Temperature Range ...........................-40C to +85C Maximum Junction Temperature .....................................+150C Storage Temperature Range .............................-60C to +150C ESD Rating (Human Body Model) .......................................2kV Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VDD = VDDP = +3.0V to +3.6V, TA = -40C to +85C, unless otherwise noted. Typical values are at VDD = VDDP = +3.3V, TA = +25C.) (Note 1)
PARAMETER DIGITAL INPUTS (REIN, SHDN) Input-High Logic Level Input-Low Logic Level Input-Current High Level Input-Current Low Level VIH VIL IIH IIL VIN = VDD VIN = 0 -20 VDD 0.6V 0.4 3.0 3.0 (Note 2) 9 7.5 3.6 3.6 16 30 2.0 0.8 20 V V A A SYMBOL CONDITIONS MIN TYP MAX UNITS
DIGITAL OUTPUT CLOCKS (CLK1-CLK6, REO) Output-High Logic Level Output-Low Logic Level POWER SUPPLY (VDD, VDDP) Power-Supply Range PLL Power-Supply Range Power-Supply Current Shutdown Supply Current VDD VDDP IDD + IDDP ISHDN V V mA A VOH VOL IOH = -4mA IOL = 4mA V V
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Low-Jitter, 8kHz Reference Clock Synthesizer Outputs 35.328MHz
AC ELECTRICAL CHARACTERISTICS
(VDD = VDDP = +3.0V to +3.6V, CL = 20pF, TA = -40C to +85C, unless otherwise noted. Typical values are at VDD = VDDP = +3.3V, TA = +25C.) (Note 3)
PARAMETER Frequency Range Clock Rise Time Clock Fall Time Duty Cycle Period Jitter Output Skew REFERENCE CLOCK OUTPUT (REO) Frequency Clock Rise Time Clock Fall Time Duty Cycle VCXO Crystal Frequency Crystal Accuracy VCXO Pulling Range Input Reference CLK Pulse Width tW fXTL Including frequency accuracy and temperature range (Note 4) Measured at high or low states -100 10 35.328 25 +100 MHz ppm ppm ns fREF tR2 tF2 40 8 1.8 1.8 50 60 kHz ns ns % JP1 JP2 tS Peak-to-peak RMS Peak-to-peak SYMBOL fOUT tR1 tF1 20% to 80% VDD 80% to 20% VDD 40 CONDITIONS MIN TYP 35.328 1.8 1.8 50 83 4 185 60 MAX UNITS MHz ns ns % ps psRMS ps
MAX9476
DIGITAL OUTPUT CLOCKS (CLK1-CLK6)
Note 1: Note 2: Note 3: Note 4:
Specifications are 100% tested at TA = +25C. Specifications over temperature are guaranteed by design and characterization. No load on clock outputs. Guaranteed by design. Crystal loading capacitance is 14pF.
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Low-Jitter, 8kHz Reference Clock Synthesizer Outputs 35.328MHz MAX9476
Typical Operating Characteristics
(VDD = VDDP = +3.3V, TA = +25C, unless otherwise noted.)
OUTPUT CLOCK JITTER (P-P) vs. TEMPERATURE
MAX9476 toc01 MAX9476 toc02
OUTPUT WAVEFORM
150 140 130 120 110 100 90 80 70 60 50 40 30 10ns/div -40
OUTPUT CLOCK JITTER (RMS) vs. TEMPERATURE
MAX9476 toc03
7 6 OUTPUT CLOCK JITTER (ps) 5 4 3 2 1 0
OUTPUT CLOCK JITTER (ps)
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE (C)
TEMPERATURE (C)
OUTPUT CLOCK JITTER (P-P) vs. SUPPLY VOLTAGE
MAX9476 toc04
OUTPUT CLOCK JITTER (RMS) vs. SUPPLY VOLTAGE
MAX9476 toc05
OUTPUT FREQUENCY VARIATION vs. INPUT REFERENCE FREQUENCY
OUTPUT FREQUENCY VARIATION (ppm) 100 75 50 25 0 -25 -50 -75 -100 -125 7.9990 7.9994 7.9998 8.0002 8.0006 8.0010 INPUT REFERENCE FREQUENCY (kHz) CENTERED AT 35.328MHz
MAX9476 toc06
100 90 OUTPUT CLOCK JITTER (ps) 80 70 60 50 40 30 3.0 3.1 3.2 3.3 3.4 3.5
7 6 OUTPUT CLOCK JITTER (ps) 5 4 3 2 1 0
125
3.6
3.0
3.1
3.2
3.3
3.4
3.5
3.6
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (IDD + IDDP) vs. SUPPLY VOLTAGE
MAX9476 toc07
SHUTDOWN SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX9476 toc08
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12 11 SUPPLY CURRENT (A) 10 9 8 7 TA = -40C 6 TA = +25C TA = +85C
12 SUPPLY CURRENT (mA) TA = +25C 10
TA = +85C
8 TA = -40C 6
4 3.0 3.1 3.2 3.3 3.4 3.5 3.6 SUPPLY VOLTAGE (V)
5 3.0 3.1 3.2 3.3 3.4 3.5 3.6 SUPPLY VOLTAGE (V)
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Low-Jitter, 8kHz Reference Clock Synthesizer Outputs 35.328MHz MAX9476
Pin Description
PIN 1 2 3 4 5 6 7, 16, 19, 21 8 9, 14, 18, 23 10 11 12 13 15 17 20 22 24 NAME SHDN REO REIN VDDP GNDP X1 VDD X2 GND LP2 LP1 SETI CLK6 CLK5 CLK4 CLK3 CLK2 CLK1 Active-Low Shutdown Input Reference Clock Output. REO is an 8kHz reference clock output with jitter suppression. Reference Input Phase-Lock Loop (PLL) Power Supply. Bypass VDDP with 0.1F and 0.001F capacitors to GNDP. PLL Ground Crystal Input 1. Connect X1 to a fundamental mode crystal for the VCXO. Digital Power Supply. Bypass VDD with 0.1F and 0.001F capacitors to GND. Crystal Input 2. Connect X2 to a fundamental mode crystal for the VCXO. Ground External Filter 2. Connect the loop filter capacitors and a resistor between LP1 and LP2 (see the Typical Application Circuit). LP2 is internally connected to GNDP. External Filter 1. Connect the loop filter capacitors and a resistor between LP1 and LP2 (see the Typical Application Circuit). Charge-Pump Current-Setting Input. Connect a resistor from SETI to GNDP to set PLL charge-pump current (see the Detailed Description section). Clock Output 6 at 35.328MHz Clock Output 5 at 35.328MHz Clock Output 4 at 35.328MHz Clock Output 3 at 35.328MHz Clock Output 2 at 35.328MHz Clock Output 1 at 35.328MHz FUNCTION
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Low-Jitter, 8kHz Reference Clock Synthesizer Outputs 35.328MHz MAX9476
Functional Diagram
LP1 LP2 X1 X2 VDDP GNDP
CLK1 SETI REIN PHASE DETECTOR AND CHARGE PUMP CLK2 VCXO PLL CLK3
of the reference CLK. However, if in a three-cycle time window the monitor counts two or three transitions, it considers the input reference clock as present. When the monitor detects the absence of the 8kHz reference clock, the outputs are operating at the center frequency of the crystal oscillator. However, when the monitor detects the return of the reference clock, the PLL locks to the reference clock. The ratio between the external crystal and the input reference clock is 4416.
Clock Outputs (CLK1 to CLK6) and REO
The MAX9476 uses a 35.328MHz crystal and a reference clock (REIN) to generate six identical outputs, CLK1 to CLK6, at 35.328MHz. All CLK_ outputs are LVTTL with a typical skew of 185ps. The MAX9476 also regenerates the 8kHz reference CLK at REO output.
CLK4 /4416 CLK5
SHDN REFERENCE CLK MONITOR
CLK6
MAX9476
REO
Voltage-Controlled Crystal Oscillator (VCXO)
The MAX9476's internal VCXO takes an external 35.328MHz crystal as the base frequency and has a pulling range of approximately 100ppm. This configuration also makes the VCXO PLL become a narrowband filter to reject high-frequency jitter on the input reference and eliminate it from the REO and CLK_ outputs.
VDD
GND
Detailed Description
The MAX9476 is a high-performance clock synthesizer with an 8kHz input reference clock. This device generates six identical buffered LVTTL clock outputs at 35.328MHz. The internal PLL phase locks the external crystal (35.328MHz) to the 8kHz input reference clock. This device features a low-jitter output that provides a better source for the reference clock relay (see the Functional Diagram).
SHDN Mode
The MAX9476 features a shutdown mode with a supply current of 7.5A (typ). Drive SHDN low to get the device into shutdown mode. In this mode, all the outputs go low and the PLL is powered down. After SHDN goes high, the outputs still stay low for an additional 256ms to allow the PLL to be stabilized before the outputs are enabled again.
Power-Up
At power-up, all the outputs are disabled and pulled low (to GND) for at least 256ms. After 256ms, the crystal oscillator starts oscillation. If the reference clock is not present at power-up, the outputs are forced to the center frequency of the crystal oscillator.
Applications Information
Crystal Selection
The MAX9476 uses a 35.328MHz crystal as the base frequency for the VCXO. It is important to use a correct type of quartz crystal to avoid reducing frequency pulling range, or excessive output phase jitter. Choose an AT-cut crystal that oscillates at 35.328MHz on its fundamental mode with a variation of 25ppm including frequency accuracy and operating temperature range. The crystal's load capacitance should be 14pF. Pulling range may vary depending on the crystal used. Refer to the MAX9476 evaluation kit for details.
Reference CLK Monitor
The MAX9476 features internal clock (CLK) monitor circuitry to detect the presence of the external 8kHz reference clock. The internal CLK monitor continuously monitors the number of low-to-high transitions within a three-cycle (at 8kHz) time window. If the transition number is less than two, the internal CLK monitor states loss
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Low-Jitter, 8kHz Reference Clock Synthesizer Outputs 35.328MHz
PLL Loop Filter
The PLL contains an integrated VCXO that uses an external crystal to track the input reference signal and attenuate input jitter. Figure 1 shows the external loop filter of the PLL containing resistor R1 and two capacitors, C1 and C2. This loop filter is connected between LP1 and LP2 as shown in the Typical Operating Circuit. The loop-filter bandwidth is determined by C1, C2, R1, and RSET where RSET is used to set the value of the charge-pump current. The typical values of C1, C2, R1, and RSET are 22nF, 560pF, 1000k, and 13k, respectively. Use the following equation to calculate a PLL loop bandwidth in Hz: BW = (R1 x ISETI x 1405) / N where R1 () is the resistor in the PLL loop filter (Figure 1), ISETI (A) is the charge-pump current calculated from the equation in the Charge-Pump Current Setting section, and N is the crystal PLL frequency divider equal to 4416. The loop-damping factor is calculated by: R DampingFactor = 1 x 2 8832 x ISETI x C1 N
LP1 R1 C2 C1 LP2
MAX9476
Figure 1. Typical Loop Filter
where RSET is in k and the value of the charge-pump current is in A. The loop response can be adjusted to meet individual application requirements since the charge-pump current and all the filter components for the VCXO loop can be set externally.
Board Layout and Bypassing
The MAX9476's high oscillator frequency makes proper layout important to ensure stability. For best performance, place components as close as possible to the device. Digital or AC transient signals on GND can create noise at the clock outputs. Return GND to the highest quality ground available. Bypass V DD and VDDP with 0.1F and 0.001F capacitors, placed as close to the device as possible. Careful PC board ground layout minimizes crosstalk between the outputs and digital inputs. Traces must be as short as possible on LP1 and LP2 and connect the capacitors and the resistor as close as possible to the device.
where C1 (F) and R1 () are the values of the capacitor and the resistor in the PLL loop filter shown in Figure 1; ISETI is calculated as shown in the ChargePump Current Setting section and N = 4416. The following equation shows the relationship between components C1 and C2 in the loop filter: C2 C1 / 20
Chip Information
TRANSISTOR COUNT: 7512 PROCESS: CMOS
Charge-Pump Current Setting
The MAX9476 also allows external setting of the chargepump current in the PLL. Connect a resistor from SETI to GNDP to set the PLL charge-pump current: Charge-Pump Current = 2.4 x 1000 / (RSET(k) + 1)
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Low-Jitter, 8kHz Reference Clock Synthesizer Outputs 35.328MHz MAX9476
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
8 _____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.
TSSOP4.40mm.EPS

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