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| SPICE Device Model SI1304BDL Vishay Siliconix N-Channel 30-V (D-S) MOSFET CHARACTERISTICS * N-Channel Vertical DMOS * Macro Model (Subcircuit Model) * Level 3 MOS * Apply for both Linear and Switching Application * Accurate over the -55 to 125C Temperature Range * Model the Gate Charge, Transient, and Diode Reverse Recovery Characteristics DESCRIPTION The attached spice model describes the typical electrical characteristics of the n-channel vertical DMOS. The subcircuit model is extracted and optimized over the -55 to 125C temperature ranges under the pulsed 0-V to 4.5-V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage. A novel gate-to-drain feedback capacitance network is used to model the gate charge characteristics while avoiding convergence difficulties of the switched Cgd model. All model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device. SUBCIRCUIT MODEL SCHEMATIC This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate data sheet of the same number for guaranteed specification limits. Document Number: 74133 S-52210Rev. A, 24-Oct-05 www.vishay.com 1 SPICE Device Model SI1304BDL Vishay Siliconix SPECIFICATIONS (TJ = 25C UNLESS OTHERWISE NOTED) Parameter Static Gate Threshold Voltage On-State Drain Current a Symbol Test Condition Simulated Data 1.1 12 0.21 0.30 3 0.78 Measured Data Unit VGS(th) ID(on) rDS(on) gfs VSD VDS = VGS, ID = 250 A VDS 5 V, VGS = 4.5 V VGS = 4.5 V, ID = 0.9 A VGS = 2.5 V, ID = 0.75 A VDS = 15 V, ID = 0.9 A IS = 0.28 A V A 0.216 0.308 2 0.80 S V Drain-Source On-State Resistancea Forward Transconductancea Diode Forward Voltagea Dynamicb Input Capacitance Output Capacitance Reverse Transfer Capacitance Total Gate Charge Gate-Source Charge Gate-Drain Charge Ciss Coss Crss Qg Qgs Qgd VDS = 15 V, VGS = 4.5 V, ID = 0.9 A VDS = 15 V, VGS = 0 V, f = 1 MHz 132 28 14 1.2 0.8 VDS = 15 V, VGS = 2.5 V, ID = 0.9 A 0.4 0.6 100 30 20 1.8 1.1 0.4 0.6 nC pF Notes a. Pulse test; pulse width 300 s, duty cycle 2%. b. Guaranteed by design, not subject to production testing. www.vishay.com 2 Document Number: 74133 S-52210Rev. A, 24-Oct-05 SPICE Device Model SI1304BDL Vishay Siliconix COMPARISON OF MODEL WITH MEASURED DATA (TJ=25C UNLESS OTHERWISE NOTED) Document Number: 74133 S-52210Rev. A, 24-Oct-05 www.vishay.com 3 |
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