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NTHD5903 Power MOSFET -20 V, -3.0 A, Dual P-Channel ChipFETE Features * * * * Low RDS(on) for Higher Efficiency Logic Level Gate Drive Miniature ChipFET Surface Mount Package Saves Board Space Pb-Free Package is Available http://onsemi.com V(BR)DSS -20 V RDS(on) TYP 130 mW @ -4.5 V 215 mW @ -2.5 V S1 S2 ID MAX -3.0 A Applications * Power Management in Portable and Battery-Powered Products; i.e., Cellular and Cordless Telephones and PCMCIA Cards G1 G2 MAXIMUM RATINGS (TA = 25C unless otherwise noted) Rating Drain-Source Voltage Gate-Source Voltage Continuous Drain Current (TJ = 150C) (Note 1) TA = 25C TA = 85C Pulsed Drain Current Continuous Source Current (Diode Conduction) (Note 1) Maximum Power Dissipation (Note 1) TA = 25C TA = 85C Operating Junction and Storage Temperature Range Symbol VDS VGS ID "3.0 "2.2 IDM IS PD 2.1 1.1 TJ, Tstg 1.1 0.6 C -3.0 "10 -2.2 "2.2 "1.6 A A W 5 secs Steady State -20 "12 Unit V V A ChipFET CASE 1206A STYLE 2 D1 P-Channel MOSFET D2 P-Channel MOSFET PIN CONNECTIONS D1 8 D1 7 D2 6 D2 5 1 S1 2 G1 3 S2 4 G2 1 MARKING DIAGRAM 8 A7 M G 7 6 5 2 3 4 -55 to +150 Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. Surface Mounted on FR4 Board using 1 in sq pad size (Cu area = 1.27 in sq [1 oz] including traces). A7 = Specific Device Code M = Month Code G = Pb-Free Package ORDERING INFORMATION Device NTHD5903T1 NTHD5903T1G Package ChipFET ChipFET (Pb-Free) Shipping 3000/Tape & Reel 3000/Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. (c) Semiconductor Components Industries, LLC, 2005 1 November, 2005 - Rev. 4 Publication Order Number: NTHD5903/D NTHD5903 THERMAL CHARACTERISTICS Characteristic Maximum Junction-to-Ambient (Note 2) tv5s Steady State Maximum Junction-to-Foot (Drain) Steady State Symbol RqJA Typ 50 90 30 Max 60 110 40 C/W Unit C/W RqJF 2. Surface Mounted on FR4 Board using 1 in sq pad size (Cu area = 1.27 in sq [1 oz] including traces). ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Characteristic Static Gate Threshold Voltage Gate-Body Leakage Zero Gate Voltage Drain Current VGS(th) IGSS IDSS VDS = VGS, ID = -250 mA VDS = 0 V, VGS = "12 V VDS = -16 V, VGS = 0 V VDS = -16 V, VGS = 0 V, TJ = 85C On-State Drain Current (Note 3) Drain-Source On-State Resistance (Note 3) ID(on) rDS(on) VDS v -5.0 V, VGS = -4.5 V VGS = -4.5 V, ID = -2.2 A VGS = -3.6 V, ID = -2.0 A VGS = -2.5 V, ID = -1.7 A Forward Transconductance (Note 3) Diode Forward Voltage (Note 3) Dynamic (Note 4) Total Gate Charge Gate-Source Charge Gate-Drain Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Source-Drain Reverse Recovery Time Qg Qgs Qgd td(on) tr td(off) tf trr IF = -2.2 A, di/dt = 100 A/ms VDD = -10 V, RL = 10 W ID ^ -1.0 A, VGEN = -4.5 V, RG = 6 W VDS = -10 V, VGS = -4.5 V, ID = -2.2 A 3.7 0.8 1.3 13 35 25 25 40 20 55 40 40 80 ns 7.4 nC gfs VSD VDS = -10 V, ID = -2.2 A IS = -2.2 A, VGS = 0 V -10 0.130 0.150 0.215 5.0 -0.8 -1.2 0.155 0.180 0.260 S V -0.6 "100 -1.0 -5.0 A W V nA mA Symbol Test Condition Min Typ Max Unit 3. Pulse Test: Pulse Width v 300 ms, Duty Cycle v 2%. 4. Guaranteed by design, not subject to production testing. http://onsemi.com 2 NTHD5903 TYPICAL ELECTRICAL CHARACTERISTICS 10 VGS = -4 V - 10 V ID, DRAIN CURRENT (AMPS) 8 TJ = 25C 6 -3.6 V ID, DRAIN CURRENT (AMPS) -3.4 V -3 V -2.8 V 4 VGS = -1.4 V 2 0 0 1 2 3 4 5 6 -VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) -2.6 V -2.4 V -2.2 V -1.8 V 8 25C 6 TC = -55C 10 125C 4 2 0 0 1 2 3 4 -VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 5 Figure 1. On-Region Characteristics RDS(on), DRAIN-TO-SOURCE RESISTANCE (W) RDS(on), DRAIN-TO-SOURCE RESISTANCE (W) 4 ID = -2.2 A TJ = 25C 3 0.4 Figure 2. Transfer Characteristics TJ = 25C 0.35 0.3 VGS = -2.5 V 0.25 0.2 VGS = -3.6 V 0.15 0.1 0.05 1 2 3 4 5 6 7 8 9 10 -ID, DRAIN CURRENT (AMPS) VGS = -4.5 V 2 1 0 0 1 2 3 4 5 -VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) Figure 3. On-Resistance vs. Gate-to-Source Voltage 1.6 RDS(on), DRAIN-TO-SOURCE RESISTANCE (NORMALIZED) ID = -2.2 A VGS = -4.5 V 1.4 1.0E-7 IDSS, LEAKAGE (A) 1.0E-6 Figure 4. On-Resistance vs. Drain Current and Gate Voltage VGS = 0 V TJ = 150C TJ = 100C 1.2 1.0E-8 1.0E-9 TJ = 25C 1 0.8 0.6 -50 1.0E-10 1.0E-11 -25 0 25 50 75 100 125 150 0 4 8 12 16 20 TJ, JUNCTION TEMPERATURE (C) -VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) Figure 5. On-Resistance Variation with Temperature Figure 6. Drain-to-Source Leakage Current vs. Voltage http://onsemi.com 3 NTHD5903 TYPICAL ELECTRICAL CHARACTERISTICS Ciss 500 C, CAPACITANCE (pF) 400 Crss 300 200 Coss 100 0 -12 TJ = 25C -VGS, GATE-TO-SOURCE VOLTAGE (V) VDS = 0 V VGS = 0 V 10 9 8 3 Qgs Qgd 7 6 2 5 4 ID = -2.2 A TJ = 25C 3 2 1 0 0 1 2 3 Qg, TOTAL GATE CHARGE (nC) 4 0 -VDS, DRAIN-TO-SOURCE VOLTAGE (V) 600 5 Qg 4 11 1 -8 -4 -VGS -VDS 0 4 8 12 16 20 GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS) Figure 7. Capacitance Variation 100 tf tr t, TIME (ns) td(on) IS, SOURCE CURRENT (AMPS) VDD = -10 V ID = -1.0 A VGS = -4.5 V td(off) 5 Figure 8. Gate-to-Source and Drain-to-Source Voltage vs. Total Charge VGS = 0 V TJ = 25C 4 3 10 2 1 0 1 1 10 RG, GATE RESISTANCE (OHMS) 100 0 0.2 0.4 0.6 0.8 1 1.2 -VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS) Figure 9. Resistive Switching Time Variation vs. Gate Resistance 2 Normalized Effective Transient Thermal Impedance 1 Duty Cycle = 0.5 Figure 10. Diode Forward Voltage vs. Current Notes: 0.2 0.1 0.1 0.05 0.02 Single Pulse 10-3 10-2 10 -1 1 Square Wave Pulse Duration (sec) PDM t1 t2 t1 1. Duty Cycle, D = t 2 2. Per Unit Base = RthJA = 90C/W 3. TJM - TA = PDMZthJA(t) 4. Surface Mounted 10 100 600 0.01 10-4 Figure 11. Normalized Thermal Transient Impedance, Junction-to-Ambient http://onsemi.com 4 NTHD5903 SOLDERING FOOTPRINT* 2.032 0.08 0.457 0.018 0.635 0.025 0.635 0.025 2.032 0.08 1.092 0.043 0.178 0.007 0.457 0.018 0.711 0.028 0.66 0.026 0.66 0.026 0.254 0.010 SCALE 20:1 mm inches Figure 12. Basic Figure 13. Style 2 *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. BASIC PAD PATTERNS The basic pad layout with dimensions is shown in Figure 12. This is sufficient for low power dissipation MOSFET applications, but power semiconductor performance requires a greater copper pad area, particularly for the drain leads. The minimum recommended pad pattern shown in Figure 13 improves the thermal area of the drain connections (pins 5, 6, 7, 8) while remaining within the confines of the basic footprint. The drain copper area is 0.0019 sq. in. (or 1.22 sq. mm). This will assist the power dissipation path away from the device (through the copper leadframe) and into the board and exterior chassis (if applicable) for the single device. The addition of a further copper area and/or the addition of vias to other board layers will enhance the performance still further. http://onsemi.com 5 NTHD5903 PACKAGE DIMENSIONS ChipFET] CASE 1206A-03 ISSUE G D 8 7 6 5 q L 5 6 3 7 2 8 1 HE 1 2 3 4 E 4 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. MOLD GATE BURRS SHALL NOT EXCEED 0.13 MM PER SIDE. 4. LEADFRAME TO MOLDED BODY OFFSET IN HORIZONTAL AND VERTICAL SHALL NOT EXCEED 0.08 MM. 5. DIMENSIONS A AND B EXCLUSIVE OF MOLD GATE BURRS. 6. NO MOLD FLASH ALLOWED ON THE TOP AND BOTTOM LEAD SURFACE. DIM A b c D E e e1 L HE q STYLE 2: PIN 1. 2. 3. 4. 5. 6. 7. 8. MILLIMETERS NOM MAX 1.05 1.10 0.30 0.35 0.15 0.20 3.05 3.10 1.65 1.70 0.65 BSC 0.55 BSC 0.28 0.35 0.42 1.80 1.90 2.00 5 NOM MIN 1.00 0.25 0.10 2.95 1.55 SOURCE 1 GATE 1 SOURCE 2 GATE 2 DRAIN 2 DRAIN 2 DRAIN 1 DRAIN 1 INCHES NOM 0.041 0.012 0.006 0.120 0.065 0.025 BSC 0.022 BSC 0.011 0.014 0.071 0.075 5 NOM MIN 0.039 0.010 0.004 0.116 0.061 MAX 0.043 0.014 0.008 0.122 0.067 e1 e b c A 0.05 (0.002) 0.017 0.079 ChipFET is a trademark of Vishay Siliconix. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: N. American Technical Support: 800-282-9855 Toll Free Literature Distribution Center for ON Semiconductor USA/Canada P.O. Box 61312, Phoenix, Arizona 85082-1312 USA Phone: 480-829-7710 or 800-344-3860 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2-9-1 Kamimeguro, Meguro-ku, Tokyo, Japan 153-0051 Fax: 480-829-7709 or 800-344-3867 Toll Free USA/Canada Phone: 81-3-5773-3850 Email: orderlit@onsemi.com ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative. http://onsemi.com 6 NTHD5903/D |
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