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TEL Original Products TE6138 DATA SHEET TE6138 IEEE1284 Peripheral Controller TE6138 TE6138 IEEE Std 1284-1994 TE6138 CPU DMA 64 QFP 1. Compatibility, Nibble, Byte, ECP 2. ECP RLE 3. Compatibility, ECP DMA ECP Forward, Reverse 4. CPU,DMA 5. 6. CMOS,5V (DMA 86 68 ) Rev.1.02 TOKYO ELECTRON DEVICE LIMITED 1 TEL Original Products TE6138 1 1 2 ................................................................................................................................ 4 ................................................................................................................................ 5 6 CPU 1. 2. ................................................................................................................. 8 ................................................................................................. 9 ................................................................................................................... 9 .................................................................................................................................. 10 ...................................................................................................................................................................... 10 ........................................................................................................................................................................... 11 3. ........................................................................................................................ 19 ..................................................................................................................................................................... 19 ..................................................................................................................................................................... 20 4. Compatibility Compatibility Compatibility Compatibility Nibble Byte DMA DMA DMA DMA Peripheral Peripheral DMA DMA DMA DMA DMA DMA DMA RLE RLE ................................................................................................................. 21 ............................................................................................................................ 21 ............................................................................................................................... 21 ............................................................................................................................ 22 ............................................................................................................................... 22 Host Host RLE RLE ON HostClk OFF HostClk HostClk Negotiation, Transfer Start.............................................................................................. 23 Negotiation, Transfer Start................................................................................................. 24 ON HostClk ON HostClk ............................................................. 25 ............................................................. 26 ..................................................................................... 27 ................................................................................... 28 ................................................................................ 29 ................................................................................................................................................ 30 .................................................................................................................................................... 31 ....................................................................................................................................................................... 32 DMA DMA TE6137 ECP Valid termination HostClk HostClk ................................................................................................ 33 .................................................................................................... 34 ........................................................................................................................................... 35 Compatibility ......................................................................................... 36 5. 1.CPU 2. DMA DMA .............................................................................................................. 37 ........................................................................................................................... 39 ........................................................................................................................... 39 39 ....................................................................................................................... 39 40 ................................................................................................................ 40 ................................................................................................ 42 ..................................................................................................................................................................... 42 ..................................................................................................................................................................... 44 .................................................................................................................... 46 .................................................................................................................... 46 Rev.1.02 TOKYO ELECTRON DEVICE LIMITED 2 TEL Original Products TE6138 .............................................................................................................................. 47 1. VDD VSS 2. #CS, 3. #RD 1 0 H L "#" Rev.1.02 TOKYO ELECTRON DEVICE LIMITED 3 TEL Original Products TE6138 RAM TE6138 ROM CPU I/F Register CPU Interrupt Control Protcol Control HOST I/F DMAC DMA Control Rev.1.02 TOKYO ELECTRON DEVICE LIMITED 4 TEL Original Products TE6138 NO. 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 I/O I I O O I O B B B B B B B B I I I I O O O O O SYMBOL VSS #DEND1 #DAK0 #DRQ0 #DEND0 CLS RT VDD VSS BPD7 BPD6 BPD5 VSS BPD4 BPD3 BPD2 VSS BPD1 BPD0 VDD #SEI #AF #INI #STB PE VSS VSS #ACK BY #FT SE VDD NOTES 6 6 1 4 3 1 NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 I: O: B: I/O O O O I I I I B B B B B B B B I I I I I I I O SYMBOL VSS #INT2 #INT1 #INT0 A3 A2 A1 A0 VSS VDD D7 D6 D5 VSS D4 D3 VSS D2 D1 D0 VDD VSS #RD #WR VSS CLK VSS #RST CIS #CS #DAK1 #DRQ1 NOTES 4 4 4 6 6 6 6 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 6 6 6 6 1 6 6 6 5 6 6 6 1 1 1 1 1 NOTES 1 2 3 4 5 6 Output Buffer(I OL=6mA) I/O Buffer(I OL=6mA) Input Buffer with Pull-up Resistor 40K Output Buffer(Open Drain) Input Buffer(CMOS Schmit) Input Buffer(TTL) (Typ) Rev.1.02 TOKYO ELECTRON DEVICE LIMITED 5 TEL Original Products Symbol VDD VSS No. 10,21,40 52,64 1,9,14, 17,22,25 27,33, 41,45,49 58,59 28 29 I #RD 23 I #WR 24 I CLK #CS D7-0 26 30 11,12,13 15,16, 18,19,20 5,6,7,8 4 I I B I O #INT1 #INT2 3 2 O #SEI #AF #STB PE #ACK BY #FT SE #INI 53 54 56 57 60 61 62 63 55 I I I O O O O O I O ADDRESS INTERRUPT REQUEST0 INTERRUPT REQUEST1 INTERRUPT REQUEST2 nSelectln nAutoFd nStrobe PError nAck Busy nFault Select nInit CLOCK CHIP SELECT DATA BUS I/O Name POWER SUPPLY GROUND - TE6138 Description #RST CIS I RESET CPU INTERFACE SELECT CPU "0" "1" CIS 86 68 "0" CPU CPU "1" READ/READ WRITE SELECT WRITE/ENABLE CIS "0" "1" A3-0 #INT0 Compatibility Nibble Byte ECP ECP " " Compatibility Compatibility Compatibility Compatibility Compatibility Compatibility Compatibility Compatibility Compatibility nSelectln nAutoFd nStrobe PError nAck Busy nFault Select nInit Rev.1.02 TOKYO ELECTRON DEVICE LIMITED 6 TEL Original Products symbol BPD7-0 No. 42,43,44, 46,47,48, 50,51 39 I/O B INDICATE REVERSE TRANSFER DMA REQUEST0 DMA END0 DMA ACKNOWLEDGE0 DMA REQUEST1 DMAEND1 DMA ACKNOWLEDGE1 Compatibility Mode LEVEL SELECT I BPD7-0 Name Data8-1 TE6138 Description Compatibility,Byte,ECP Data8-1 RT O #DRQ0 #DEND0 #DAK0 36 37 35 I #DRQ1 #DEND1 #DAK1 CLS 32 34 31 38 O I I O O Compatibility,ECP DMAC Compatibility,ECP DMA Compatibility,ECP DMAC ECP ECP (#DRQ1) ECP "0" Byte,ECP BY,#FT,SE "1" DMAC DMA DMAC Compatibility,Nibble, #INI,#SEI,#AF,#STB,PE,#ACK, Rev.1.02 TOKYO ELECTRON DEVICE LIMITED 7 TEL Original Products CPU TE6138 CIS CPU TE6138 CPU CIS="0" #RD #WR CIS="1" R#W #EN CIS="0" (#RD,#WR) CIS="1" Rev.1.02 TOKYO ELECTRON DEVICE LIMITED 8 TEL Original Products TE6138 Compatibility,Nibble, TE6138 Byte,ECP IEEE Std 1284-1994 DMA ECP Compatibility IC DMA 1. TE6138 I/O Compatibility nInit nSelectIn nAutoFd nStrobe PError nAck Busy Fault Select Data8 Data7 Data6 Data5 Data4 Data3 Data2 Data1 Data8-1 Nibble "1" 1284Active HostBusy HostClk AckDataReq PtrClk PtrBusy nDataAvail XFlag Byte "1" 1284Active HostBusy HostClk AckDataReq PtrClk PtrBusy nDataAvail XFlag Data8 Data7 Data6 Data5 Data4 Data3 Data2 Data1 ECP nReverseRequest 1284Active HostAck HostClk nAckReverse PeriphClk PeriphAck nPeriphRequest XFlag Data8 Data7 Data6 Data5 Data4 Data3 Data2 Data1 ( 55 #INI I 53 #SEI I 54 #AF I 56 #STB I 57 PE O 60 #ACK O 61 BY O 62 #FT O 57 SE O 42 BPD7 B 43 BPD6 B 44 BPD5 B 46 BPD4 B 47 BPD3 B 48 BPD2 B 50 BPD1 B 51 BPD0 B 1) BPD7-0 IEEE1284 Rev.1.02 TOKYO ELECTRON DEVICE LIMITED 9 TEL Original Products 2. TE6138 A3 A2 0 0 A1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 (ECP ) (ECP 1 ) 0 1 0 0 1 1 1 1 0 0 0 0 1 1 1 1 ECP RLE ECP ECP - ACK ACK Nibble/Byte Nibble/Byte ECP DMA ECP 2 ECP 1 2 Rev.1.02 TOKYO ELECTRON DEVICE LIMITED 10 TEL Original Products TE6138 [ 1 ] D6 1 D5 1 D4 1 D3 1 1 ID 0: 1: 1: 1 ACK(#ACK) 1: 0: 0: "1": "0": Immediate Termination D2 0 D1 0 D0 0 Address"0"(write only) D7 Initial Value 1 D7: D6: D5: D4: D3: D2:Byte D1: Compatibility D0: Compatibility 0 Nibble Byte Nibble Byte 1: Nibble Byte Compatibility 0: 0: STB(#STB) 1: BUSY(BY) 1 [ ](ECP D6 0 D5 0 ) D4 0 D3 0 D2 0 D1 0 D0 0 Address"1"(Read only) D7 Initial Value 0 [ ](ECP D6 0 D5 0 ) D4 0 D3 0 D2 0 D1 0 D0 0 Address"1"(Write only) D7 Initial Value 0 Rev.1.02 TOKYO ELECTRON DEVICE LIMITED 11 TEL Original Products [ ] D6 0 D5 0 D4 0 D3 0 D2 1 D1 1 TE6138 Address"2"(Read only) D7 Initial Value 1 1 D7: D6: D5: D4: D3: D2,D1,D0: D0 1 Compatibility Nibble Byte Negotiation Termination Nibble 000:Host Busy Data Avail 001:Host Busy Data Not Avail 010:Idle 011:Data Transfer 100:Interrupt 111: (Compatibility [D=7] ) Negotiation [D=4] Termination [D=3] ECP (D6=1) Byte (D5=1) [ Address"2"(Write only) D7 Initial Value 1 D7: 1: 0: ) Nibble ID Byte ID ] D6 Nibble D5 D4 Byte D3 D2 D1 (event1: D0 ) 1 Rev.1.02 TOKYO ELECTRON DEVICE LIMITED 12 TEL Original Products [ Address"3"(Read only) D7 Initial Value 1 D7:Compatibility 0: D6:Compatibility 0: D5:Compatibility 0: 0: D3:Nibble Byte 0: D2:Nibble Byte 0: ) D1:Nibble Byte 0: D0:Compatibility 0: 1: 1: ( 1: #SEI(nSelectin) 1: #AF(nAutofd) 1: 1: ID 1: Termination Compatibility ) 1: 0 (event1) #INI(`nInit) "0" ] D6 1 D5 1 D4 1 D3 1 D2 1 D1 1 "H" TE6138 D0 1 ) (Termination phase) (BUSY D4:Device ID Reverse Transfer Nibble 1284Active (INT#0) D5 D2 N T Compatibility N Nibble ID T D5 D3 D4 D2 N: Negotiation T: Termination ) [ Address"3"(Write only) D7 Initial Value 1 D7-4 D7: 1: D6: 1: D5: 1: D4: 1: D7 0: D6 0: D5 0: D4 0: ] D6 1 D5 1 D4 1 D3 D2 D1 D0 - Rev.1.02 TOKYO ELECTRON DEVICE LIMITED 13 TEL Original Products [ Address"4"(Read only) D7 Initial Value D1,D0: [ACK Address"4"(Write only) D7 Initial Value 0 CLK [ACK Address"5"(Write only) D7 Initial Value 0 CLK 2 255 1 ] D6 0 D5 0 ( " 'Nibble D4 0 32 ' 'Byte D3 0 (00h D2 0 ) ' 31 D1 0 2 255 ] D6 0 D5 0 D4 0 D3 0 (02h D2 0 2 D1 0 D6 0 ] D5 0 D4 0 D3 0 (02h D2 0 2 D1 0 ] D6 D5 D4 D3 D2 D1 0 TE6138 D0 0 ) D0 0 DMA ) D0 0 [Nibble/Byte Address"6"(Write only) D7 Initial Value 0 CLK 31 8191 "4. DataAvail 20MHZ TE6138 400s 2 ) D0 0 32+18 400s IEEE1284 35ms [Nibble/Byte ] D6 0 D5 0 D4 0 D3 0 (02h D2 0 2 D1 0 ) D0 0 Address"7"(Write only) D7 Initial Value 0 CLK 2 255 "4. IEEE1284 " 500ns 'Nibble ' 'Byte ' [ECP Address"8"(Read only) D7 Initial Value 0 ECP ] D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 0 Rev.1.02 TOKYO ELECTRON DEVICE LIMITED 14 TEL Original Products [ECP Address"8"(Write only) D7 Initial Value 0 ECP [RLE Address"9"(Read only) D7 Initial Value D6 1 ] D5 1 D4 1 D3 1 D2 1 D1 1 ] D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 TE6138 D0 0 D0 1 [ECP Address"10"(Read only) D7 Initial Value 0 1 D7: Negotiation Phase D6: Termination Phase D5: Forward Idle Phase D4: Reverse Idle Phase D3: D2: D1: ECP RLE D0: ECP RLE ECP ] D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 0 D0 0 (ID (ID ) ) '0' Rev.1.02 TOKYO ELECTRON DEVICE LIMITED 15 TEL Original Products [ECP Address"11"(Read only) D7 Initial Value 0 ECP D7: ECP D6: [#INT2: ] D5: Channel Address Command D4: RLE D3: D2: Host Transfer Recovery D1: O O O O D0: ECP ) [ DMA D6 DMA 1 2 2 Byte ECP ECP RLE D4=0 ] D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 TE6138 D0 0 D6=0 RLE ECP Immediate Termination Compatibility 1 ] D5 D4 D3 D2 D1 D0 - Address"11"(Write only) D7 Initial Value ECP #DRQ1 [ECP Address"12"(Write only) D7 Initial Value 1 D7: D6: ] D6 1 D5 1 0: D4 1 1: #INT1,#INT2 D3 1 D2 1 D1 1 D0 1 D5: Channel Address Command D4: RLE D3: D2: Host Transfer Recovery D1: D0: ECP Immediate Termination Rev.1.02 TOKYO ELECTRON DEVICE LIMITED 16 TEL Original Products [ 2 ] D6 0 0: D7: ECP RLE (1 D6: ECP RLE (1 D5: (Negotiation 0:HostClk 1:HostClk D4: (DMA D3: RLE ( D2: ECP D1: Nibble ID ) D0: ECP ECP 0 0 1 [ECP Address"14"(Write only) D7 Initial Value CLK 1 16 event 5~6 event 23~24 event 26~27 event 48~49 ] D6 D5 D4 "0000" 1 D3 0 23 (00h 1 D2 D1 0 0 22 21 ECP Reverse ( D6 ECP 0 1 )DMA 2 D4 #INT1 #INT2 ECP ECP Forward ( 0= RLE )DMA 1= (#INT2) ) HostClk ) 0 0 D5 0 D4 0 1: D3 0 D2 0 D1 0 Address"13"(Write only) D7 Initial Value 0 TE6138 D0 0 ) ) ) D6 D6 ) D0 0 20 Rev.1.02 TOKYO ELECTRON DEVICE LIMITED 17 TEL Original Products [ ] D6 1 "H" ECP ECP "H" D5:Compatibility 0: D4:DMA 0 D3: 0 1 0 0 0 : : : : : : 86 IC Forward Forward PE="L" #FT="L" SE="L" "H" "L" Reverse Reverse 1 1 1 : : : "L" "H" 1 : 68 DMA : Reverse D5 0 D4 0 D3 0 D2 0 D1 1 Address"15"(Write only) D7 Initial Value 1 D7:1 0 ( D6:0 BY BY TE6138 D0 1 #FT "1" "L" Reverse 1 D2: Compatibility D1: Compatibility D0: Compatibility PE(PError) PE="H" #FT ="H" SE="H" #FT(nFault) SE(Select) Rev.1.02 TOKYO ELECTRON DEVICE LIMITED 18 TEL Original Products 3. CLK 16MHz DMA DMA ECP #INT1 ECP Compatibility TE6138 ECP D1 TE6138 DMAC TE6138 20MHz Compatibility ECP ECP (="L") Nibble Byte DMA DMA Nibble ) ECP 1 1 2 2 Byte Nibble ID Byte ID (#INT0 D3,D4 ) #DEND1 (#INT0 D2 ECP TE6138 CPU Nibble Rev.1.02 TOKYO ELECTRON DEVICE LIMITED 19 TEL Original Products TE6138 TE6138 TE6137 < TE6137 TE6138 > TE6138 TE6137 ID ID ID ID (BPo#INT0) "0" (#INT0) (D2 ) [ Address2 1 "1": ] D7 D6 (event1: D0 Nibble Byte ) "0": ) "1" Nibble ID Byte ID TE6137 [ Adress4 - ] D7 D6 - D0 D1,D0: P14 ECP HOSTCLK PeriphACK (event35 37 ) nStrobe Busy (event35 36) nStrobe Busy (event36 32) nInit event74 #DRQ0 event75 nStrobe event75 #DRQ0 D7 D7=0 ,event35 ,event32 D7=1 nInit Event35 nStrobe nInit PEerror event75 (CLK) #DRQ0 ( ) ECP nStrobe event74 75 #DRQ0 #DRQ0 ECP ECP ECP D7 nSelectln Rev.1.02 TOKYO ELECTRON DEVICE LIMITED 20 TEL Original Products 4. Compatibility #RD #WR #SEI PE # AF #ST B #ACK BY # FT SE # INT0 ( ( ( ( 1) 2) 3) 4) TE6138 DMA "0" "L" "" "H" "L" 1 ACK STB 2 STB STB 3 STB 2 BUSY ( ( ( ( 5) 6) 7) 8) ACK 1 D1 Compatibility #R D #WR #SEI PE #AF #ST B #ACK BY #FT SE #INT0 # DRQ 0 "0" "L" "X" DMA "H" "L" "H" ( ( ( ( ( 1) 2) 3) 4) 5) 1 ACK ACK STB 2 STB STB DMA (#CS ACK 1 STB 3 ) CLK D1 1CLK 2 BUSY ( ( ( 6) 7) 8) Rev.1.02 TOKYO ELECTRON DEVICE LIMITED 21 TEL Original Products Compatibility < #RD #W R TE6138 DMA > STB #SEI #ST B #AC K BY #INT0 "" < #RD #W R STB+ STB > #SEI #S TB #ACK "0" BY #INT0 STB+ STB D7 D0 1 Compatibility DMA RD DA K DRQ SEI ST B AC K BY INT0 Compatibility DMA 1 BUSY H D7 BUSY STB "0" Rev.1.02 TOKYO ELECTRON DEVICE LIMITED 22 TEL Original Products TE6138 Nibble 1 2 2 1 Peripheral Host Negotiation, Transfer Start 2 #RD 86 # W R 68 3 3 #WR #WR 4 86 68 1284Active Data bit 2 Data bit 6 AckDataReq BP D7 0000 0000 HostBusy Hostclk Ptrclk ( 1) Nibble/Byte 1 Ptrbusy Data Avail Data bit 0 Data bit 4 Data bit 3 Data bit 7 nDataAvail Data Not Avail Busy Data Not Avail 35ms CLK Host 1284 8191(20MHz 409 s) Xflag Data bit 1 Z Data bit 5 ( 6 ( 6 Z or ( 2) Nibble/Byte 1284 2 500ns #INT0 Device ID Z Device ID ( ( ( ( H.B. D.N.A Data Transfer 3) 4) 5) Hosy Busy Data Not Avail 6) Data bit Compatibility Mode Negotiation Host Busy Data Avail Reverse Idle 5 Rev.1.02 TOKYO ELECTRON DEVICE LIMITED 23 TEL Original Products 1) 2) 1 2 1 TE6138 Byte Peripheral Host Negotiation, Transfer Start #RD(8 6 ) # W R(68 ) 3) 3 3 # W R(86 # W R(68 4 4 4 ) ) 1284Active AckDataReq Z Data byte 0 Data byte 1 BPD 7-0 0000 0001 HostBusy Hostclk Ptrclk Ptrbusy "L" nDataAvail Xflag Z or Device ID Host Busy Data Avail Data Transfer or Device ID Host Busy Data Not Avail Reverse Idle Z Z or #INT0 Z Device ID Host Busy Data Avail Data Transfer Compatibility Mode Negotiation ( 1) Nibble/Byte 1284 ( 2) Nibble/Byte 1284 ( 3) ( 4) 1 35ms 2 500ns CLK Host Busy Data Not Avail 8191(20MHz 409 s) Rev.1.02 TOKYO ELECTRON DEVICE LIMITED 24 TEL Original Products TE6138 DMA RLE ON HostClk CLK 1284Active Perror E ) E E H nAckReverse 0000 0001 ( 1010 1010( ) 0101 0101( ) E P E Data(8 1) H/P E 0011 0000(ECP,RLE ) HostAck H HostClk H PeriphClk P E Busy nFau lt Select PeriphAck P E nPeriphRequest P E XFlag P E nReverseRequest H 0000 0001( 1010 1010 0101 0101 ) E 0011 000 0(ECP,RLE ) E ECP E 1000 0000 0000 0000 #INT1 #RD &9 &9 &8 &7 &6 &5 &4 &3 &2 &1 &0 &F 0000 0001 0000 0001 0000 0000 1111 1111 0000 0001 1111 1111 &9 &8 &7 &6 &5 &4 &3 &2 &1 &0 &F E ( &9 ) &9 &8 &7 &6 &5 &4 &3 &2 &1 &0 &F E E #INT2 event 32 #RD IEEE1284 ECP 35mS #RD Rev.1.02 TOKYO ELECTRON DEVICE LIMITED TOKYO ELECTRON DEVICE LIMITED 25 TEL Original Products TE6138 DMA RLE ON HostClk CLK 1284Active Perror E ) E E H nAckReverse 0000 0001 ( 1010 1010( ) 0101 0101( ) E P E Data(8 1) H/P E 0011 0000(ECP,RLE ) HostAck H HostClk H PeriphClk P E Busy nFault Select PeriphAck P E nPeriphRequest P E XFlag P E nReverseRequest 0000 0001( 1010 1010 0101 0101 ) H E 0011 0000(ECP,RLE ) E ECP E 1000 0000 0000 0000 #INT1 #RD &9 &9 &8 &7 &6 &5 &4 &3 &2 &1 &0 &F 0000 0001 0000 0001 0000 0000 1111 1111 0000 0000 1111 1111 &9 &8 &7 &6 &5 &4 &3 &2 &1 &0 &F E ( &9 ) &9 &8 &7 &6 &5 &4 &3 &2 &1 &0 &F E E #INT2 Rev.1.02 TOKYO ELECTRON DEVICE LIMITED TOKYO ELECTRON DEVICE LIMITED 26 TEL Original Products TE6138 DMA RLE ON HostClk CLK 1284Active Perror E ) E E H nAckReverse 0000 0001 ( 1010 1010( ) 0101 0101( ) E P E Data(8 1) H/P E 0011 0000(ECP,RLE ) HostAck H HostClk H PeriphClk P E Busy nFault Select PeriphAck P E nPeriphRequest P E XFlag P E nReverseRequest H 0000 0001( 1010 1010 0101 0101 ) E 0011 0000(ECP,RLE ) E ECP E 1000 00000000 0000 #INT1 #RD I/O Read I/O Read &9 &8 &7 &6 &5 &4 &3 &2 &1 &0 &F 0000 0001 0000 0000 1111 1111 I/O Read &9 &8 &7 &6 &5 &4 &3 &2 &1 &0 &F &9 &8 &7 &6 &5 &4 &3 &2 &1 &0 &F E ( &9 ) E E 0000 0001 1111 1111 0000 0000 #INT2 #DRQ0 #DAK0 Z Z #DEND0 Z Rev.1.02 TOKYO ELECTRON DEVICE LIMITED TOKYO ELECTRON DEVICE LIMITED 27 TEL Original Products TE6138 DMA RLE OFF HostClk CLK 1284Active nAckReverse Data(8 1) HostAck HostClk PeriphClk PeriphAck nPeriphRequest XFlag nReverseRequest R R ECP #INT1 #RD #INT2 #DRQ0 #DAK0 #DEND0 Rev.1.02 TOKYO ELECTRON DEVICE LIMITED TOKYO ELECTRON DEVICE LIMITED 28 TEL Original Products TE6138 DMA HostClk CLK 1284Active H nAckReverse E E 1000 0001( ) 1010 1010( ) 0101 0101( ) P E Data(8 1) H/P E 0011 0000(ECP,RLE ) HostAck H HostClk H PeriphClk P E PeriphAck P E nPeriphRequest P E XFlag P E nReverseRequest 1000 0001( 1010 1010 0010 0000 0000 0000 0101 0101 ) H E 0011 0000(ECP,RLE ) E ECP E 1000 0000 0000 0000 #INT1 #RD &9 &8 &7 &6 &5 &4 &3 &2 &1 &0 &F E ( &9 ) E E #INT2 #DRQ0 #DAK0 #DEND0 Z Rev.1.02 TOKYO ELECTRON DEVICE LIMITED TOKYO ELECTRON DEVICE LIMITED 29 TEL Original Products TE6138 DMA CLK 1284Active H nAckReverse E E Z E 0000 0001( ) 1010 1010( ) Z P E Data(8 1) H/P E 0011 0100(ID ) HostAck H HostClk H PeriphClk E P E PeriphAck P E nPeriphRequest P E XFlag P E nReverseRequest H R E 0011 0100(ID ) R 0000 0000 0000 1000 0000 1000 0000 1000 0000 0000 0000 0000 E ECP E 1000 0000 0000 0000 #INT1 #RD #WR &9 &8 &7 &6 &5 &4 &3 &2 &1 &0 &F E ( &9 ) &9 &8 &7 &6 &5 &4 &3 &2 &1 &0 &F E E #INT2 #DRQ0 #DAK0 #DEND0 0000 0001( )) Z S E S E 1010 1010( ) Rev.1.02 TOKYO ELECTRON DEVICE LIMITED TOKYO ELECTRON DEVICE LIMITED 30 TEL Original Products TE6138 DMA CLK 1284Active H nAckReverse E E Z 1010 1010( ) Z P E Data(8 1) H/P E 0001 0000(ECP,RLE ) HostAck H HostClk H PeriphClk P E PeriphAck P E nPeriphRequest P E XFlag P E nReverseRequest H R E 0001 0000 R E ECP E 1000 0000 0000 0000 #INT1 #RD #WR DMA &9 &8 &7 &6 &5 &4 &3 &2 &1 &0 &F E ( &9 ) &9 &8 &7 &6 &5 &4 &3 &2 &1 &0 &F E E #INT2 #DRQ1 #DAK1 1010 1010( ) S E Rev.1.02 TOKYO ELECTRON DEVICE LIMITED TOKYO ELECTRON DEVICE LIMITED 31 TEL Original Products TE6138 CLK 1284Active H nAckReverse E 00 11 000 0(ECP RL E ) 000 1 0000 (ECP RLE ) 0100 0000(EPP ) E P E Data(8 1) H/P E 1000 000 0( ) HostAck H HostClk H PeriphClk P E PeriphAck P Perip hera l Busy Status nPeriphRequest P E XFlag P E nReverseRequest H E 1000 000 0( ) E ECP E 1000 0000 000 0 0000 #INT1 #RD &9 &8 &7 &6 &5 &4 &3 &2 &1 &0 &F &9 &8 &7 &6 &5 &4 &3 &2 &1 &0 &F &9 &8 &7 &6 &5 &4 &3 &2 &1 &0 &F E ( &9 ) &9 &8 &7 &6 &5 &4 &3 &2 &1 &0 &F E E #INT2 #DRQ0 #DAK0 #DEND0 Z 2 11XX XXXX Rev.1.02 TOKYO ELECTRON DEVICE LIMITED TOKYO ELECTRON DEVICE LIMITED 32 TEL Original Products TE6138 DMA HostClk CLK 1284Active H nAckReverse ) E E 0101 0101( ) P Data(8 1) H/P E 1010 1010( ) 0101 0101( HostAck H E HostClk H PeriphClk P PeriphAck P nPeriphRequest P XFlag 35ms P nReverseRequest H 1010 1010 0000 0000 0000 0100 0101 0101 0101 0101( ) ECP #INT1 #RD &1 &0 &F #INT2 Rev.1.02 TOKYO ELECTRON DEVICE LIMITED TOKYO ELECTRON DEVICE LIMITED 33 TEL Original Products TE6138 DMA HostClk BPiCLK 1284Active H nAckReverse ) E E 0101 0101( ) P Data(8 1) H/P E 1010 1010( ) 0101 0101( HostAck H E HostClk H PeriphClk P PeriphAck P nPeriphRequest P XFlag 35ms P nReverseRequest H 1010 1010 0000 0000 0000 0100 0101 0101 0101 0101( ) ECP BPoINT1 RD &F INT2 #DRQ0 #DAK0 Z Z #DEND0 Z Z Rev.1.02 TOKYO ELECTRON DEVICE LIMITED TOKYO ELECTRON DEVICE LIMITED 34 TEL Original Products TE6138 TE6137 CLK 1284Active nAckReverse Data(8 1) HostAck HostClk PeriphClk PeriphAck nPeriphRequest XFlag nReverseRequest ECP #INT1 #RD #WR INT2 Rev.1.02 TOKYO ELECTRON DEVICE LIMITED TOKYO ELECTRON DEVICE LIMITED 35 TEL Original Products TE6138 ECP Valid termination Compatibility CLK 1284Active Perror H nAckReverse P Data(8 1) H/P 0101 0101( ) E HostAck H E HostClk H PeriphClk Busy nFault Select P PeriphAck P nPeriphRequest P XFlag P nReverseRequest H 0101 0101( ) ECP #INT1 #RD #WR &9 &8 &7 &6 &5 &4 &3 &2 &1 &0 &F &9 &8 &7 &6 &5 &4 &3 &2 &1 &0 &F 0000 0000 1111 1111 #INT2 1000 0000 1000 0000 0000 0000 Rev.1.02 TOKYO ELECTRON DEVICE LIMITED TOKYO ELECTRON DEVICE LIMITED 36 TEL Original Products 5. TE6138 Compatibility DMA Byte Compatibility ,Nibble ,Byte Compatibility DMA ECP Y ECP ECP D7 0 Rev.1.02 TOKYO ELECTRON DEVICE LIMITED 37 TEL Original Products 6.ECP 1 DMA 2 RLE 3 4 < 1 2 3 4 ( ( 2 2 ( (ECP > TE6138 #INT1+ECPIR D5 ECPIR D2 D3 2 1: 1: 0: 0: D4 D6 ) ) 1: 1: TE6138 0: ) 0: ) Peripheral CPU ECPIR:ECP < 1 < [DMA 1 0 0 0 0 0 0 [DMA 1 1 1 2 0 1 0 1 0 1 ] 2 0 1 3 4 DMA TE6138 Peripheral CPU 2 0 1 > ] 3 0 0 1 1 4 0 0 1 1 0 0 TE6138 #INT1+ECPIR D6 ECPIR D6 #INT2 ECPIR ECPIR Peripheral CPU 3 4 > TE6138 #INT1+ECPIR D4 ECPIR Peripheral CPU Rev.1.02 TOKYO ELECTRON DEVICE LIMITED 38 TEL Original Products TE6138 VDD VI VO TST -0.3 +6.0 -0.3 VDD+0.3 -0.3 VDD+0.3 -55 +150 V ( VDD TA 4.5 -20 ) 5.5 70 V IDDS "1" "0" "H" "L" VIH VIL VOH VOL TTL CMOS TTL CMOS IOH=-2mA IOL=6mA 2.3 3.8 VDD-0.4 - 0.2 0.7 1.1 0.4 mA V CIN COUT CI/O 20 20 20 pF Rev.1.02 TOKYO ELECTRON DEVICE LIMITED 39 TEL Original Products TE6138 =20pF =20pF 1.CPU CIS "0" (86 ) T1 T2 T5 T4 T3 T6 T8 T7 T9 T11 T10 T12 T13 T14 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 #RD #RD #RD #RD #RD #RD #RD #WR #WR #WR #WR #WR #WR #WR S H D W #CS #CS A3-0 A3-0 #RD D7-0(Z V) D7-0(V Z) #CS #CS #WR A3-0 A3-0 D7-0 D7-0 S H S H W D D S H W S H S H 10 10 15 10 30 10 10 30 10 15 15 0 20 15 - ns Rev.1.02 TOKYO ELECTRON DEVICE LIMITED 40 TEL Original Products CIS "1" (68 ) TE6138 T1 5 T1 6 T17 T18 T1 9 T2 0 T21 T22 T24 T25 T2 3 T2 6 T2 8 T2 7 T2 9 T30 T31 T32 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 T27 T28 T29 T30 T31 T32 #WR #WR #WR #WR #WR #WR #WR #WR #WR #WR #WR #WR #WR #WR #WR #WR #WR #WR #CS #CS #RD #RD A3-0 A3-0 #WR D7-0(Z V) D7-0(V Z) #RD #RD #CS #CS #WR A3-0 A3-0 D7-0 D7-0 S H S H S H W D D S H S H W S H S H 10 10 10 10 10 10 30 10 10 10 10 30 10 10 15 0 20 15 - ns - S H D W Rev.1.02 TOKYO ELECTRON DEVICE LIMITED 41 TEL Original Products 2. DMA CPU Compatibility DMA DMA <86 > ECP Mode 0000 0010 0000 0001 0000 0000 TE6138 86 " 68 " RD WR(EN) CPU DAK 1111 1111 #DRQ0 Z #DEND0 Z #DAK0 #RD T 41 T47 T42 T48 T43 T 44 T45 T 46 D7-0 T4 T4 Z <68 > ECP Mode 0000 0010 0000 0001 0000 0000 1111 1111 #DRQ0 Z #DEND0 Z #DAK0 #W R T4 T T T T D7-0 T5 T5 Z Rev.1.02 TOKYO ELECTRON DEVICE LIMITED 42 TEL Original Products <68 > ECP Mode 0000 0000 1111 1111 TE6138 #DRQ0 #DE 0 Z Z # #W R D7-0 T5 T Z T41 T42 T43 T44 T45 T46 T47 T48 T49 T4A T4B T50 T51 T52 T53 T54 T55 T56 T57 T5A T5B #RD #RD #RD #RD #RD #RD #RD #RD #WR #RD #RD #WR #WR #WR #WR #WR #WR #DAK0 #DAK0 #WR #WR #DAK0 #RD #RD #DEND0(Z L) #DEND0(L Z) #DRQ0 #DAK0 #RD #DAK0 D7-0(Z V) D7-0(V Z) #WR #WR #DEND0(Z L) #DRQ0 #DEND0(L Z) #WR #DEND0(Z L) #DRQ0 D7-0(Z V) D7-0(V Z) S W W D D D H CT S D D W W D D D CT D D D D 0 30 30 0 2T BC 0 30 30 2T BC - 1.5T BC+20 1.5T BC+20 25 20 20 1.5T BC+20 1.5T BC+20 1.5T BC+20 20 20 20 20 ns S H D W CT TBC=CLK Rev.1.02 TOKYO ELECTRON DEVICE LIMITED 43 TEL Original Products DMA < > TE6138 # DRQ 1 T64 #DAK1 DMA #WR T6 1 T62 T63 T65 #DEND1 T6 6 D7-0 T6A T6B T67 1 D RQ 1 D MA DE ND1 < > # DRQ 1 T74 #DAK1 DMA #WR T T2 T3 T5 #DEND1 T6 D7-0 TA TB T7 1 DR Q1 D MA DEND1 Rev.1.02 TOKYO ELECTRON DEVICE LIMITED 44 TEL Original Products T61 T62 T63 T64 T65 T66 T67 T6A T6B T71 T72 T73 T74 T75 T76 T77 T7A T7B #WR #WR #WR #DAK1 #WR #DEND1 #DEND1 #WR #WR #WR #WR #WR #DAK1 #WR #DEND1 #DEND1 #WR #WR #DAK1 # WR #DAK1 #DRQ1 #DRQ1 #DEND1 #DRQ1 D7-0 D7-0 #DAK1 #WR #DAK1 #DRQ1 #DRQ1 #DEND1 #DRQ1 D7-0 D7-0 S W H D D W D S H S W H D D W D S H 0 30 0 TBC 15 0 0 30 0 TBC 15 0 TE6138 2T BC+20 3T BC+20 3T BC+20 2T BC+20 3T BC+20 3T BC+20 S H D W ns T BC=CLK Rev.1.02 TOKYO ELECTRON DEVICE LIMITED 45 TEL Original Products TE6138 TE6138 CLK TP TF TN TR "1" "0" TP TN TR TF TC 20 20 50 15 15 62.5 ns TE6138 TAW TAW 50 - ns Rev.1.02 TOKYO ELECTRON DEVICE LIMITED 46 TEL Original Products TE6138 64 0.38g TQFP mm 14.0 12.0 0.2SQ 0.2SQ 48 49 33 32 64 1 17 16 1.125 0.32 +0.06 -0.10 0.13 M 0.65TYP 1.0 0.2 0.17 0.10 +0.03 -0.07 Rev.1.02 TOKYO ELECTRON DEVICE LIMITED 47 TEL Original Products TE6138 TOP 224-0045 TEL FAX E-mail URL 045-474-7013 045-474-5617 top@teldevice.co.jp http://www.teldevice.co.jp 1 (c) 2000 Tokyo Electron Device Limited printed in JAPAN 2002 2 Rev.1.02 TOKYO ELECTRON DEVICE LIMITED 48 |
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