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 SSM9971GD
Dual N-channel Enhancement-mode Power MOSFETs
PRODUCT SUMMARY
BVDSS R DS(ON) ID
DESCRIPTION
The SSM9971GD acheives fast switching performance with low gate charge without a complex drive circuit. It is suitable for low voltage applications such as DC/DC converters and general load-switching circuits. The SSM2310GD is supplied in an RoHS-compliant PDIP-8 package, which is widely used for medium power commercial and industrial applications, where throughhole insertion into the board is required.
60V 50m 5A
Pb-free; RoHS-compliant SO-8
D2 D2 D1 D1
G2
PDIP-8
S1
S2 G1
ABSOLUTE MAXIMUM RATINGS
Symbol VDS VGS ID IDM PD TSTG TJ Parameter Drain-source voltage Gate-source voltage Continuous drain current Pulsed drain current
1,2
3
3 ,
Value 60 25 T A = 25C TA = 70C 5 3.2 20 2 0.016 -55 to 150 -55 to 150
Units V V A A A W W/C C C
Total power dissipation , TA = 25C Linear derating factor Storage temperature range Operating junction temperature range
THERMAL CHARACTERISTICS
Symbol RJA Parameter Maximum thermal resistance, junction-ambient
3
Value 62.5
Units C/W
Notes:
1.Pulse width must be limited to avoid exceeding the maximum junction temperature of 150C. 2.Pulse width <300us, duty cycle <2%. 3.Mounted on a square inch of copper pad on FR4 board; 90C/W when mounted on the minimum pad area required for soldering.
10/16/2005 Rev.3.1
www.SiliconStandard.com
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SSM9971GD
ELECTRICAL CHARACTERISTICS
Symbol BVDSS Parameter Drain-source breakdown voltage
Breakdown voltage temperature coefficient
(at Tj = 25C, unless otherwise specified)
Test Conditions VGS=0V, ID=250uA Reference to 25C, ID=1mA VGS=10V, ID=5A VGS=4.5V, ID=2.5A Min. 60 1 Typ. 0.06 7 32.5 4.9 8.8 9.6 10 30 5.5 1560 156 110 Max. Units 50 60 3 1 25 100 V V/C m m V S uA uA nA nC nC nC ns ns ns ns pF pF pF
BV DSS/Tj
RDS(ON)
Static drain-source on-resistance2
VGS(th) gfs IDSS IGSS Qg Qgs Qgd td(on) tr td(off) tf Ciss Coss Crss
Gate threshold voltage Forward transconductance
VDS=VGS, ID=250uA VDS=10V, ID=5A
Drain-source leakage current
VDS=60V, VGS=0V
VDS=48V ,VGS=0V, Tj = 70C VGS=25V ID=5A VDS=48V VGS=10V VDS=30V ID=5A RG=3.3 , VGS=10V RD=6 VGS=0V VDS=25V f=1.0MHz
Gate-source leakage current Total gate charge
2
Gate-source charge Gate-drain ("Miller") charge Turn-on delay time Rise time Turn-off delay time Fall time Input capacitance Output capacitance Reverse transfer capacitance
2
Source-Drain Diode
Symbol VSD trr Qrr Parameter Forward voltage
2
Test Conditions IS=1.6A, VGS=0V IS=5A, VGS=0V, dI/dt=100A/s
Min. -
Typ. 29.2 48
Max. Units 1.2 V ns nC
Reverse-recovery time
Reverse-recovery charge
Notes:
1.Pulse width must be limited to avoid exceeding the maximum junction temperature of 150C. 2.Pulse width <300us, duty cycle <2%.
10/16/2005 Rev.3.1
www.SiliconStandard.com
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SSM9971GD
35 35
T A =25 C
30
o
ID , Drain Current (A)
ID , Drain Current (A)
25
10V 6.0V 4.5V
T A =150 C
30
o
10V 6.0V 4.5V
25
20
20
15
15
V G =3.0V
10
10
V G =3.0V
5
5
0 0 1 2 3 4 5
0 0 1 2 3 4 5
V DS , Drain-to-Source Voltage (V)
V DS , Drain-to-Source Voltage (V)
Fig 1. Typical output characteristics
Fig 2. Typical output characteristics
52
3.0
I D =5A
48
I D =5A
2.5
T A =25 C Normalized R DS(ON)
2.0
o
V G =10V
RDS(ON) (m )
44
1.5
40
1.0
36 0.5
32 3 5 7 9 11
0.0 -50 0 50 100 150
V GS , Gate-to-Source Voltage (V)
T j , Junction Temperature ( o C)
Fig 3. On-resistance vs. gate voltage
Fig 4. Normalized on-resistance vs. junction temperature
3
100
2.5 10
2
1
VGS(th) (V)
IS (A)
T j =150 o C
T j =25 o C
1.5
1 0.1 0.5
0.01
0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5
0 -50 0 50 100 150
V SD , Source-to-Drain Voltage (V)
T j ,Junction Temperature ( C)
o
Fig 5. Forward characteristic of the reverse diode
Fig 6. Gate threshold voltage vs. junction temperature
10/16/2005 Rev.3.1
www.SiliconStandard.com
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SSM9971GD
f=1.0MHz
14 10000
I D =5A
12
VGS , Gate to Source Voltage (V)
10
V DS =48V V DS =38V V DS =30V
Ciss
1000
8
6
Coss
4 100
Crss
2
0
0 5 10 15 20 25 30 35 40
10 1 5
Q G , Total Gate Charge (nC)
V DS , Drain-to-Source Voltage (V)
9
13
17
21
25
29
Fig 7. Gate charge characteristics
Fig 8. Typical capacitance characteristics
100
1
Duty foctor=0.5
Normalized Thermal Response (R ja)
10
0.2
1ms ID (A)
0.1
0.1
0.05
1
10ms 100ms
0.02 0.01
PDM
0.01
Single Pulse
t T
Duty factor = t/T Peak T j = PDM x Rthja + Ta
R ja=90C/W
0.1
T A =25 C Single Pulse
o
1s DC
0.01
0.001
0.1
1
10
100
1000
0.0001
0.001
0.01
0.1
1
10
100
1000
V DS , Drain-to-Source Voltage (V)
t , Pulse Width (s)
Fig 9. Maximum safe operating area
Fig 10. Effective transient thermal impedance
VDS 90%
VG QG 10V QGS QGD
10% VGS td(on) tr td(off) tf Charge Q
Fig 11. Switching time waveforms
Fig 12. Gate charge diagram
10/16/2005 Rev.3.1
www.SiliconStandard.com
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SSM9971GD
PHYSICAL DIMENSIONS
D
SYMBOL A1
E1
MIN 0.38 2.90 0.35 0.20 9.00 7.62 6.09 8.3 2.92
MAX -- 5.00 0.56 0.36 10.20 8.26 7.20 11.00 --
A2 b C
E
D E
C
A2 A1
L
E1 e E2 L
2.54 (TYP)
E2 b e
All dimensions in millimeters. Dimensions do not include mold protrusions.
PART MARKING
PART NUMBER: 9971GD
XXXXXX YWWSSS
DATE/LOT CODE: (YWWSSS) Y = last digit of the year WW = week SSS = lot code sequence
PACKING: Moisture sensitivity level MSL1
50 pcs in antistatic tube, 20 tubes (1000 pieces) per box.
Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no guarantee or warranty, express or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of Silicon Standard Corporation or any third parties.
10/16/2005 Rev.3.1
www.SiliconStandard.com
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