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| CS5451A Six-channel, Delta-sigma Analog-to-digital Converter Features * Synchronous Sampling * On-chip 1.2 V Reference (25 ppm/C typ.) * Power Supply Configurations: - VA+ = +3 V; VA- = -2 V; VD+ = +3 V - Supply Tolerances: 10% Description The CS5451A is a highly integrated delta-sigma () analog-to-digital converter (ADC) developed for the power measurement industry. The CS5451A combines six ADCs, decimation filters, and a serial interface on a single chip. The CS5451A interfaces directly to a current transformer or shunt to measure current, and to a resistive divider or transformer to measure voltage. The product features a serial interface for communication with a microcontroller or DSP. The product is initialized and fully functional upon reset, and includes a voltage reference. * Power Consumption - 23 mW Typical at VD+ = +3 V * Simple Four-wire Serial Interface * Charge pump driver output generates negative power supply. * Ground-referenced Bipolar Inputs GAIN IIN1+ IIN1VIN1+ VIN1IIN2+ IIN2VIN2+ VIN2VA+ 4th Order Modulator 4th Order Modulator ORDERING INFORMATION: See page 13. RESET VD+ x1, 20 Decimation Filter x1 Decimation Filter x1, 20 4th Order Modulator Decimation Filter SE x1 4th Order Modulator 4th Order Modulator Decimation Filter Serial Interface OWRS SDO FSO SCLK IIN3+ IIN3VIN3+ VIN3VREFIN VREFOUT x1, 20 Decimation Filter x1 4th Order Modulator Decimation Filter x1 Voltage Reference Clock Pulse Output Regulator CPD AGND VA- XIN DGND http://www.cirrus.com Copyright (c) Cirrus Logic, Inc. 2005 (All Rights Reserved) AUG `05 DS635F2 CS5451A TABLE OF CONTENTS 1. PIN DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2. CHARACTERISTICS AND SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3. THEORY OF OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4. FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.1 Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.2 Digital Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.3 Performing Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.4 Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.5 System Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.6 Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.7 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5. PACKAGE DIMENSIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6. ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION . . . . . . . . . . . . . . . 13 8. REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 LIST OF FIGURES Figure 1. Serial Port Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 2. Typical Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 3. One Data Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 4. Serial Port Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 5. Generating VA- with a Charge Pump. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2 DS635F2 CS5451A 1. PIN DESCRIPTION Serial Clock Output Serial Data Output Frame Sync Serial Port Enable Current Input Gain Analog Ground Reference Input Positive Analog Supply Negative Analog Supply Differential Voltage Input 3 Differential Voltage Input 3 Differential Current Input 3 Differential Current Input 3 SCLK SDO FSO SE GAIN AGND VREFIN VA+ VA VIN3+ VIN3IIN3+ IIN31 2 3 4 6 7 8 9 10 11 12 13 14 28 27 26 25 VD+ DGND CPD XIN Digital Supply Digital Ground Charge Pump Drive Master Clock CS5451A 5 24 23 22 21 20 19 18 17 16 15 RESET Reset OWRS Output Word Rate Select VIN1+ VIN1IIN1+ IIN1VIN2+ VIN2IIN2+ IIN2Differential Voltage Input 1 Differential Voltage Input 1 Differential Current Input 1 Differential Current Input 1 Differential Voltage Input 2 Differential Voltage Input 2 Differential Current Input 2 Differential Current Input 2 Reference Output VREFOUT Clock Generator Master Clock Input Control Pins and Serial Data I/O Serial Clock Output Serial Data Output Frame Sync Serial Port Enable Current Input Gain Output Word Rate Select 23 Reset Analog Inputs/Outputs Voltage Reference Input Voltage Reference Output Differential Voltage Inputs 7 8 VREFIN - The input to this pin establishes the voltage reference for the on-chip modulator. VREFOUT - The on-chip voltage reference output. The voltage reference has a nominal magnitude of 1.2 V and is referenced to the AGND pin on the converter. 25 XIN - External clock signal or oscillator input. 1 2 3 4 5 SCLK - Serial port clock signal that determines the output data rate for SDO pin. Rate of SCLK is dependent on the XIN frequency and state of OWRS pin. SDO -Serial port data output pin. Data will be output at a rate defined by SCLK. FSO - Framing signal indicates when data samples are about to be transmitted on the SDO pin. SE - When SE is low, the output pins of the serial port are tri-stated. GAIN - A logic high sets current channel gain to 1, a logic low sets the gain to 20. If no connection is made to this pin, it will default to logic low level (through internal 200 k resistor to DGND). OWRS - A logic low sets the output word rate (OWR) to XIN/2048 (Hz). A logic high sets the OWR to XIN/1024 (Hz). If no connection is made to this pin, then OWRS will default to logic low level (through internal 200 k resistor to DGND). RESET - Low activates Reset, all internal registers are set to their default states. 24 11,12 VIN3+, VIN3- - Differential analog input pins for the voltage channel 3. 18,17 VIN2+, VIN2- - Differential analog input pins for the voltage channel 2. 22,21 VIN1+, VIN1- - Differential analog input pins for the voltage channel 1. 13,14 IIN3+, IIN3- - Differential analog input pins for the current channel 3. 16,15 IIN2+, IIN2- - Differential analog input pins for the current channel 2. 20,19 IIN1+, IIN1- - Differential analog input pins for the current channel 1. Differential Current Inputs Power Supply Connections Analog Ground Positive Analog Supply Negative Analog Supply Charge Pump Drive Digital Ground Positive Digital Supply 6 9 10 AGND - Analog ground. VA+ - The positive analog supply. Typical +3 V 10% relative to AGND. VA- - The negative analog supply. Typical -2 V 10% relative to AGND. CPD - Designed to drive external charge pump circuitry that will produce a negative analog supply (VA-)voltage. DGND - Digital Ground. VD+ - The positive digital supply. Typical +3 V 10% relative to AGND. 26 27 28 DS635F2 3 CS5451A 2. CHARACTERISTICS AND SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS Parameter DC Power Supplies Positive Digital Positive Analog Negative Analog Symbol VD+ VA+ VAVREF+ Min 2.7 2.7 -2.2 Typ 3.0 3.0 -2.0 1.2 Max 3.3 3.3 -1.8 Unit V V V V Voltage Reference Input ANALOG CHARACTERISTICS * * * * Min/Max characteristics and specifications are guaranteed over all Operating Conditions. Typical characteristics and specifications are measured at nominal supply voltages and TA = 25 C. VA+ = VD+ = 3 V 10%; VA- = -2 V 10%; AGND = DGND = 0 V; VREFIN = +1.2 V. All voltages with respect to 0 V. XIN = 4.096 MHz. Parameter Accuracy (All Channels) Total Harmonic Distortion Common Mode Rejection Common Mode + Signal on Input Input Sampling Rate Analog Inputs (Note 1) Differential Input Voltage Range [(IIN+) - (IIN-)] or [(VIN+) - (VIN-)] Bipolar Offset Crosstalk (Channel-to-channel) Input Capacitance Effective Input Impedance Noise (Referred to Input) 0-60 Hz 0-1 kHz 0-2 kHz Reference Output Output Voltage Temperature Coefficient Load Regulation Reference Input Input Voltage Range Input Capacitance Input CVF Current (Output Current 1 A Source or Sink) Gain=20 Gain=1 Gain=20 Gain=1 (50, 60 Hz) Gain = 20 Gain = 1 Gain=20 Gain=1 Gain=20 Gain=1 Gain=20 Gain=1 Gain=20 Gain=1 (DC, 50, 60 Hz) Symbol THD CMRR Min 74 80 VA- Typ XIN/4 80 1.6 11.5 0.5 -105 60 600 1.2 25 6 1.2 - Max VA+ 20 4.0 20 1 1 20 2.5 50 3.75 75 1.25 50 10 1.25 10 1 Unit dB dB V Hz mVP-P VP-P mV mV dB pF pF k k Vrms Vrms Vrms Vrms Vrms Vrms VIN VIN VOS VOS IC IC EII EII 50 500 - REFOUT VR PSRR VREF+ 1.15 60 1.15 - V ppm/C mV dB V pF A Power Supply Rejection 4 DS635F2 CS5451A ANALOG CHARACTERISTICS (continued) Parameter Power Supplies Power Supply Currents Typical VA+ = VD+ = +3 V; VA- = -2 V Symbol IA+ ID+ with CPD ID+ without CPD With CPD Without CPD Min 50 50 60 Typ 4.0 5.0 1.0 27 23 65 90 Max 5.3 6.3 1.5 35 31 - Unit mA mA mA mW mW dB dB dB PSCA PSCD PSCD PC PC PSRR PSRR PSRR Power Consumption (Note 2) Power Supply Rejection 50, 60 Hz (Note 3) 50, 60 Hz (Note 3) (DC) Voltage Channel Current Channel Notes: 1. Specifications for Gain = 20 apply only to Current Channels. Voltage Channels are fixed to Gain = 1 2. 3. All outputs unloaded. All inputs CMOS level. Definition for PSRR: VREFIN tied to VREFOUT, VA+ = VD+ = 3 V, AGND = DGND = 0 V, VA- = -2 V (using chargepump circuit with CPD). In addition, a 106.07 mV rms (60 Hz) sinewave is imposed onto the VA+ and VD+ pins. The "+" and "-" input pins of both input channels are shorted to VA-. 2048 instantaneous digital output data words are collected for the channel under test. The rms value of the digital sinusoidal output signal is calculated, and this rms value is converted into the rms value of the sinusoidal voltage (measured in mV) that would need to be applied at the channel's inputs, in order to cause the same digital sinusoidal output. This voltage is then defined as Veq. PSRR is then (in dB): 106.07 PSRR = 20 log ----------------- V eq DIGITAL CHARACTERISTICS (See Note 4) * * * * Min/Max characteristics and specifications are guaranteed over all Operating Conditions. Typical characteristics and specifications are measured at nominal supply voltages and TA = 25 C. VA+ = VD+ = 3V 10%; VA- = -2 V 10%; AGND = DGND = 0 V. All voltages with respect to 0 V. XIN = 4.096 MHz Parameter Master Clock Characteristics Master Clock Frequency Master Clock Duty Cycle Filter Characteristics High Rate Filter Output Word Rate Input/Output Characteristics High-Level Input Voltage Low-Level Input Voltage High-Level Output Voltage Low-Level Output Voltage Input Leakage Current 3-State Leakage Current Digital Output Pin Capacitance Notes: 4. All measurements performed under static conditions. 5. Symbol XIN Min 3 40 Typ 4.096 XIN/2048 XIN/1024 1 9 Max 5 60 VD+ 0.8 0.4 10 10 - Unit MHz % Hz Hz V V V V A A pF OWRS = 0 OWRS = 1 OWR OWR VIH VIL 0.6 VD+ 0.0 (VD+) - 1.0 - Iout = -5.0 mA Iout = 5.0 mA (Note 5) VOH VOL Iin IOZ Cout For OWRS and GAIN pins, input leakage current is 30 A (Max). DS635F2 5 CS5451A SWITCHING CHARACTERISTICS * * * * Min/Max characteristics and specifications are guaranteed over all Operating Conditions. Typical characteristics and specifications are measured at nominal supply voltages and TA = 25 C. VA+ = VD+ = 3 V 10%; VA- = -2 V 10%; AGND = DGND = 0 V. All voltages with respect to 0 V. Logic Levels: Logic 0 = 0 V, Logic 1 = VD+ Parameter Rise Times (Note 6) Fall Times (Note 6) Serial Port Timing Serial Clock Frequency (Note 7) Serial Clock (Note 7 and 8) SCLK falling to New Data Bit FSO Falling to SCLK Rising Delay FSO Pulse Width SE Rising to Output Enabled SE Falling to Output in Tri-state 7. 8. 9. Symbol trise Min - Typ 50 50 500 1000 0.5 0.5 0.5 1 - Max 1.0 10 1.0 10 50 50 50 Unit s ns ns s ns ns kHz kHz SCLK SCLK ns SCLK SCLK ns ns Any Digital Input (except XIN) XIN only Any Digital Output Any Digital Input (except XIN) XIN only Any Digital Output OWRS = "0" OWRS = "1" Pulse Width High Pulse Width Low (Note 7 & 8) (Note 7 & 8) (Note 9) tfall SCLK SCLK t1 t2 t3 t4 t5 t6 t7 Notes: 6. Specified using 10% and 90% points on wave-form of interest. Output loaded with 50 pF. Device parameters are specified with XIN = 4.096 MHz. Device parameters are specified with OWRS = 1. After SE is asserted, the states of SDO and SCLK are FSO is undefined. SDO MSB(V1) MSB(V1) - 1 LSB(I3) t3 t1 t2 SCLK t4 FSO t5 t7 SE t6 Figure 1. Serial Port Timing 6 DS635F2 CS5451A ABSOLUTE MAXIMUM RATINGS WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. Parameter DC Power Supplies Positive Digital Positive Analog Negative Analog (Note 10 and 11) (Note 12) All Analog Pins All Digital Pins Symbol VD+ VA+ VAIIN IOUT PDN VINA VIND TA Tstg Min -0.3 -0.3 -2.5 (VA-) - 0.3 -0.3 -40 -65 Typ Max +3.5 +3.5 -0.3 10 25 500 (VA+) + 0.3 (VD+) + 0.3 85 150 Unit V V V mA mA mW V V C C Input Current, Any Pin Except Supplies Output Current Power Dissipation Analog Input Voltage Digital Input Voltage Ambient Operating Temperature Storage Temperature Notes: 10. Applies to all pins including continuous over-voltage conditions at the analog input (AIN) pins. Transient current of up to 100 mA will not cause SCR latch-up. Maximum input current for a power supply pin is 50 mA. 12. Total power dissipation, including all input currents and output currents. 11. DS635F2 7 CS5451A 3. THEORY OF OPERATION The CS5451A is a six-channel analog-to-digital converter (ADC) followed by a serial interface that allows communication with a target device. The analog inputs are structured for 3-phase power meter applications, with three dedicated voltage and current channels. Figure 2 illustrates the CS5451A typical inputs and power supply connections. The voltage-sensing element introduces a voltage waveform on the voltage channel inputs VIN(1-3) and is subject to a fixed 1x gain amplifier. A fourth-order delta-sigma modulator samples the amplified signal for digitization. Simultaneously, the current-sensing element introduces a voltage waveform on the current channel input IIN(1-3) and is subject to two selectable gains of the programmable gain amplifier (PGA). The amplified signal is sampled by a fourth-order delta-sigma modulator for digitization. Both converters sample at a rate of XIN/8, the over-sampling provides a wide dynamic range and simplified anti-alias filter design. The decimating digital filters on all channels are Sinc3 filters. The single bit data is passed to the low-pass decimation filter and output at a fixed word rate. The decimation rate is selectable for two output word rates. The 16-bit output word is then transmitted via a master serial data port. The six-channel data is multiplexed on the serial data output and is preceded by a frame sync signal. +3 V VA+ REFIN Optional External Reference REFOUT VD+ 1.2 V V + PHASE VIN1+, VIN2+, or VIN3+ VIN1-, VIN2-, or VIN3- IIN1+, IIN2+, or IIN3+ I PHASE NOTE: Current input channels actually measure voltage. IIN1-, IIN2-, or IIN3- AGND VA- DGND -2 V Figure 2. Typical Connection Diagram 8 DS635F2 CS5451A 4. 4.1 FUNCTIONAL DESCRIPTION Analog Inputs The decimation rate is determined by the exponent DR (see Table 2). The output word rate (OWR) is selected by the OWRS pin and defined by Table 2. OWRS 0 1 DR 256 128 Output Word Rate XIN/2048 XIN/1024 The CS5451A is equipped with six fully differential input channels. The inputs VIN(1-3) and IIN(1-3) are designated as the voltage and current channel inputs, respectively. The full-scale differential input voltage for the current and voltage channel is 800 mVP (gain = 1x). Table 2. Decimation Filter OWR 4.1.1 Voltage Channel 4.3 Performing Measurements The output of the line voltage resistive divider or transformer is connected to the VIN(1-3)+ and VIN(1-3)- input pins of the CS5451A. The voltage channels are equipped with a 1x fixed gain amplifier. The full-scale signal level that can be applied to the voltage channel is 800 mV. If the input signal is a sine wave the maximum RMS voltage is: 800mV P 2 ----------------- 565.69mVRMS which is approximately 70.7% of maximum peak voltage. The ADC outputs are transferred in 16-bit, signed (two's complement) data formats. Table 3 defines the relationship between the differential voltage applied to any one of the input channels and the corresponding output code. Note that for the current channels, the state of the GAIN input pin is assumed to driven low such that the PGA gain on the current channels is 1x. If the PGA gain of the current channels is set to 20x, a +40 mV voltage is applied to any pair of IIN(1-3) pins would cause an output code of 32767. Differential Input Voltage (mV) +800 0.0122 to 0.0366 -0.0122 to 0.0122 -0.0122 to -0.0366 -800 Output Code (hexadecimal) 7FFF 0001 0000 FFFF 8000 Output Code (decimal) 32767 1 0 -1 -32768 4.1.2 Current Channel The output of the current sense resistor or transformer is connected to the IIN(1-3)+ and IIN(1-3)- input pins of the CS5451A. To accommodate different current-sensing devices the current channels incorporates a programmable gain amplifier (PGA) that can be set to one of two input ranges. Input pin GAIN (see Table 1) define the PGA's two gain selections and corresponding maximum input signal level. GAIN 0 1 Maximum Input Range 40mV 800mV 20x 1x Notes: Assume PGA gain is set to 1x. Table 3. Differential Input Voltage vs. Output Code 4.4 Serial Interface Table 1. Current Channel PGA Setting 4.2 Digital Filters The decimating digital filter samples the modulator bit stream at XIN/8 and produces a fixed output word rate. The digital filters are implemented as sinc3 filters with the following transfer function: The CS5451A communicates with a target device via a master serial data output port. Output data is provided on the SDO output synchronous with the SCLK output. A third output, FSO, is a framing signal used to signal the start of output data. These three outputs will be driven as long as the SE (serial enable) input is held high. Otherwise, these outputs will be high-impedance. Data out (SDO) changes as a result of SCLK falling, and always outputs valid data on the rising edge of SCLK. When data is being transferred the SCLK frequency is XIN/8 when OWRS is low or XIN/4 when OWRS is high. 1 - z - DR H ( z ) = --------------------- 1 - z-1 3 DS635F2 9 CS5451A 96 SCLKs SCLK ... ... 15 14 13 12 11 10 9 876 5 43 21 0 15 14 13 12 11 10 9 8 7654 3 2 1 0 15 14 ... ... ... 3 2 1 0 FSO SDO [ Low ] Channel 1 ( V ) Channel 1 ( I ) ... ... [ Low ] Ch. 2 ( V )... Ch. 2 ( I ) ... Ch. 3 ( V ) ... Ch. 3 ( I ) Figure 3. One Data Frame When data is not being transferred SCLK is held low. (see Figure 3.) The framing signal (FSO) output is normally low. FSO goes high, with a pulse width equal to one SCLK period, when the instantaneous voltage and current data samples are about to be transmitted out of the serial interface (after each A/D conversion cycle). SCLK is not active during FSO high. For 96 SCLK periods after FSO falls, SCLK is active and SDO provides valid output. Six channels of 16-bit data are output, MSB first. Figure 4 illustrates how the voltage and current measurements are output for the three phases. SCLK will then be held low until the next sample period. RESET is activated, all internal registers are set to a default state. Upon powering up, the RESET pin must be held low (active) until after the power stabilizes. 4.6 Voltage Reference The CS5451A is specified for operation with a +1.2 V reference between the VREFIN and AGND pins. The converter includes an internal 1.2 V reference that can be used by connecting the VREFOUT pin to the VREFIN pin of the device. The VREFIN can be used to connect external filtering and/or references. 4.7 Power Supply 4.5 System Initialization A hardware reset is initiated when the RESET pin is forced low with a minimum pulse width of 50 ns. When The low, stable analog power consumption and superior supply rejection of the CS5451A allow for the use of a simple charge-pump negative supply generator. The use of a negative supply alleviates the need for level SCLK 96 SCLKs FSO Each data segment is 16 bits long. SDO Channel 1 V Channel 1 I Channel 2 V Channel 3 I Channel 3 V Channel 2 I Figure 4. Serial Port Data Transfer 10 DS635F2 CS5451A shifting of the analog inputs. The CPD pin and capacitor C1 provide the necessary analog supply current as shown in Figure 5. The Schottky diodes D1 and D2 are chosen for their low forward voltages and high-speed capabilities. The capacitor C2 provides the required charge storage and bypassing of the negative supply. The CPD output signal provides the charge pump driver signal. The frequency of the charge pump driver signal is synchronous to XIN. The nominal average frequency is 1 MHz. The level on the VA- pin is fed back internally so that the CPD output will regulate the VA- level to -2/3 of VA+ level. The value of capacitor C1 (see Figure 5) is dependent on the XIN clock frequency. The 39 nF value for C1 was selected for a XIN clock frequency equal to 4.096 MHz. For more information about the operation of this type of charge pump circuit, the reader can refer to Cirrus Logic, Inc.'s application note AN152: Using the CPD AGND 39 nF C1 D2 BAT 85 D1 BAT 85 VA- C2 1 F Figure 5. Generating VA- with a Charge Pump CS5521/24/28, and CS5525/26 Charge Pump Drive for External Loads. DS635F2 11 CS5451A 5. PACKAGE DIMENSIONS 28L SSOP PACKAGE DRAWING N D E11 A2 A1 A E L e b2 SIDE VIEW END VIEW SEATING PLANE 123 TOP VIEW INCHES DIM A A1 A2 b D E E1 e L MIN -0.002 0.064 0.009 0.390 0.291 0.197 0.022 0.025 0 NOM -0.006 0.069 -0.4015 0.307 0.209 0.026 0.0354 4 MAX 0.084 0.010 0.074 0.015 0.413 0.323 0.220 0.030 0.041 8 MIN -0.05 1.62 0.22 9.90 7.40 5.00 0.55 0.63 0 MILLIMETERS NOM -0.13 1.75 -10.20 7.80 5.30 0.65 0.90 4 MAX 2.13 0.25 1.88 0.38 10.50 8.20 5.60 0.75 1.03 8 NOTE 2,3 1 1 JEDEC #: MO-150 Notes: 1. "D" and "E1" are reference datums and do not included mold flash or protrusions, but do include mold mismatch 2. and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. Dimension "b" does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be 0.13 mm total in excess of "b" dimension at maximum material condition. Dambar intrusion shall not reduce dimension "b" by more than 0.07 mm at least material condition. 3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips. 12 DS635F2 CS5451A 6. ORDERING INFORMATION Model Temperature Package CS5451A-IS CS5451A-ISZ (lead free) -40 to +85 C 28-pin SSOP 7. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION Model Number Peak Reflow Temp 240 C 260 C MSL Rating* 2 3 Max Floor Life 365 Days 7 Days CS5451A-IS CS5451A-ISZ (lead free) * MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020. 8. REVISION HISTORY Revision A1 PP1 F1 F2 Date JUL 2003 OCT 2003 FEB 2005 AUG 2005 Initial Release Initial release for Preliminary Product Information Update electrical specifications w/ most-current characterization data. Update electrical specifications w/ most-current characterization data. Added MSL data. Changes Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to you go to www.cirrus.com IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. DS635F2 13 |
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