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Features
* 16 Channel GPS Correlator
- 8192 Search Bins with GPS Acquisition Accelerator - Accuracy: 2.5m CEP (Stand-Alone, S/A off) - Time to First Fix: 34s (Cold Start) - Acquisition Sensitivity: -140 dBm - Tracking Sensitivity: -150 dBm Utilizes the ARM7TDMI(R) ARM(R) Thumb(R) Processor Core - High-performance 32-bit RISC Architecture - High-density 16-bit Instruction Set - EmbeddedICETM (In-circuit Emulator) 128 Kbyte Internal RAM 384 Kbyte Internal ROM, Firmware Version V5.0 Position Technology Provided by u-blox Fully Programmable External Bus Interface (EBI) - Maximum External Address Space of 8 Mbytes - Up to 4 Chip Selects - Software Programmable 8-bit/16-bit External Data Bus 6-channel Peripheral Data Controller (PDC) 8-level Priority, Individually Maskable, Vectored Interrupt Controller - 2 External Interrupts 32 User-programmable I/O Lines 1 USB Device Port - Universal Serial Bus (USB) V2.0 Full-speed Device - Embedded USB V2.0 Full-speed Transceiver - Suspend/Resume Logic - Ping-pong Mode for Isochronous and Bulk Endpoints 2 USARTs - 2 Dedicated Peripheral Data Controller (PDC) Channels per USART Master/Slave SPI Interface - 2 Dedicated Peripheral Data Controller (PDC) Channels - 8-bit to 16-bit Programmable Data Length - 4 External Slave Chip Selects Programmable Watchdog Timer Advanced Power Management Controller (APMC) - Peripherals Can Be Deactivated Individually - Geared Master Clock to Reduce Power Consumption - Sleep State with Disabled Master Clock - Hibernate State with 32.768 kHz Master Clock Real Time Clock (RTC) 2.3V to 3.6V or 1.8V Core Supply Voltage Includes Power Supervisor 1.8V to 3.3V User-definable I/O Voltage for Several GPIOs with 5V Tolerance 4 Kbytes Battery Backup Memory 9 mm x 9 mm 100-pin BGA Package (LFBGA100) RoHS-compliant
*
* * * *
GPS Baseband Processor ATR0621P
* * * *
* *
* *
* * * * * * *
4890H-GPS-08/08
1. Description
The GPS baseband processor ATR0621P includes a 16-channel GPS correlator and is based on the ARM7TDMI processor core. This processor has a high-performance 32-bit RISC architecture and very low power consumption. In addition, a large number of internally banked registers result in very fast exception handling, making the device ideal for real-time control applications. The ATR0621P has two USART and an USB device port. This port is compliant with the Universal Serial Bus (USB) V2.0 full-speed device specification. The ATR0621P has a direct connection to off-chip memory, including Flash, through the External Bus Interface (EBI). The ATR0621P includes full GPS firmware, licensed from u-blox AG, which performs the basic GPS operation, including tracking, acquisition, navigation and position data output. For normal PVT (Position/Velocity/Time) applications, there is no need for off-chip Flash memory or ROM. The firmware supports e.g. the NMEA(R) protocol (2.1 and 2.3), a binary protocol for PVT data, configuration and debugging, the RTCM protocol for DGPS, SBAS (WAAS, EGNOS and MSAS) and A-GPS (aiding). It is also possible to store the configuration settings in an optional external EEPROM. The ATR0621P is manufactured using the Atmel(R) high-density CMOS technology. By combining the ARM7TDMI microcontroller core with on-chip SRAM, 16-channel GPS correlator and a wide range of peripheral functions on a monolithic chip, the ATR0621P provides a highly-flexible and cost-effective solution for GPS applications.
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4890H-GPS-08/08
ATR0621P
Figure 1-1. Block Diagram
NSHDN NSLEEP XT_IN XT_OUT GPS Accelerator GPS Correlators
Advanced Power Management Controller
SRAM
RTC
RF_ON CLK23
SIGLO0 SIGHI0
SMD Generator
P0/NANTSHORT P14/NAADET1 P25/NAADET0 P20/TIMEPULSE P29/GPSMODE12 P27/GPSMODE11 P26/GPSMODE10 P24/GPSMODE8 P23/GPSMODE7 P19/GPSMODE6 P17/GPSMODE5 P13/GPSMODE3 P12/GPSMODE2 P1/GPSMODE0 P9/EXTINT0 P2/BOOT_MODE P30/AGCOUT0 P8/STATUSLED
PIO2 Controller
APB
SPI
Timer Counter
P15/ANTON
USART2
Special Function
P21/TXD2 PIO2 P22/RXD2
PIO2
Advanced Interrupt Controller
USART1
P18/TXD1 P31/RXD1
USB Transceiver
Watchdog
EM_A19 EM_A1 EM_DA15 EM_DA0
Interface to Off-Chip Memory (EBI)
ASB
ARM7TDMI
Embedded ICE
DBG_EN NTRST TDI TDO TCK TMS JTAG
SRAM 128K
ROM 384K
PDC2
P16/NEEPROM P11/EM_A21 P28/EM_A20 P10/EM_A0/NLB P7/NUB/NWR1 P6/NOE/NRD P5/NWE/NWR0 P4/nCS0 P3/nCS1
USB_DP USB_DM
B R I D G E
USB
Reset Controller
Power Supply Manager
VBAT18 VBAT LDOBAT_IN LDO_OUT LDO_IN LDO_EN
NRESET
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4890H-GPS-08/08
2. Architectural Overview
2.1 Description
The ATR0621P architecture consists of two main buses, the Advanced System Bus (ASB) and the Advanced Peripheral Bus (APB). The ASB is designed for maximum performance. It interfaces the processor with the on-chip 32-bit memories and the external memories and devices by means of the External Bus Interface (EBI). The APB is designed for accesses to on-chip peripherals and is optimized for low power consumption. The AMBATM Bridge provides an interface between the ASB and the APB. An on-chip Peripheral Data Controller (PDC2) transfers data between the on-chip USARTs/SPI and the on-chip and off-chip memories without processor intervention. Most importantly, the PDC2 removes the processor interrupt handling overhead and significantly reduces the number of clock cycles required for a data transfer. It can transfer up to 64K contiguous bytes without reprogramming the starting address. As a result, the performance of the microcontroller is increased and the power consumption reduced. The ATR0621P peripherals are designed to be easily programmable with a minimum number of instructions. Each peripheral has a 16 Kbyte address space allocated in the upper 3 Mbyte of the 4 Gbyte address space. (Except for the interrupt controller, which has 4 Kbyte address space.) The peripheral base address is the lowest address of its memory space. The peripheral register set is composed of control, mode, data, status, and interrupt registers. To maximize the efficiency of bit manipulation, frequently written registers are mapped into three memory locations. The first address is used to set the individual register bits, the second resets the bits, and the third address reads the value stored in the register. A bit can be set or reset by writing a "1" to the corresponding position at the appropriate address. Writing a "0" has no effect. Individual bits can thus be modified without having to use costly read-modify-write and complex bit-manipulation instructions. All of the external signals of the on-chip peripherals are under the control of the Parallel I/O (PIO2) Controller. The PIO2 Controller can be programmed to insert an input filter on each pin or generate an interrupt on a signal change. After reset, the user must carefully program the PIO2 Controller in order to define which peripheral signals are connected with off-chip logic. The ARM7TDMI processor operates in little-endian mode on the ATR0621P GPS Baseband. The processor's internal architecture and the ARM and Thumb instruction sets are described in the ARM7TDMI datasheet. The ARM standard In-Circuit Emulation debug interface is supported via the JTAG/ICE port of the ATR0621P. Features of the ROM firmware are described in software documentation available from u-blox AG, Switzerland.
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ATR0621P
3. Pin Configuration
3.1 Pinout
Pinout LFBGA100 (Top View)
Figure 3-1.
A B CDE F GH J K 10 9 8 7 6 5 4 3 2 1
Table 3-1.
Pin Name CLK23 DBG_EN EM_A1 EM_A2 EM_A3 EM_A4 EM_A5 EM_A6 EM_A7 EM_A8 EM_A9 EM_A10 EM_A11 EM_A12 EM_A13 EM_A14 EM_A15 Notes:
ATR0621P
ATR0621P Pinout
LFBGA100 G9 H4 A6 A5 A4 A2 A3 B5 B4 B2 D4 C2 D6 D7 C3 C1 D5 Pin Type IN IN OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT PD Pull Resistor (Reset Value)(1) Firmware Label PIO Bank A PIO Bank B
1. PD = internal pull-down resistor, PU = internal pull-up resistor, OH = switched to Output High at reset 2. VBAT18 represent the internal power supply of the backup power domain, see section "Power Supply" on page 21 3. VDDIO is the supply voltage for the following GPIO pins: P1, P2, P8, P12, P14, P16, P17, P18, P19, P20, P21, P23, P24, P25, P26, P27 and P29, see section "Power Supply" on page 21 4. VDD_USB is the supply voltage for the following USB pins: USB_DM and USB_DP, see section "Power Supply" on page 21. For operation of the USB interface, supply of 3.0V to 3.6V is required. 5. This pin is not connected
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4890H-GPS-08/08
Table 3-1.
Pin Name EM_A16 EM_A17 EM_A18 EM_A19 EM_DA0 EM_DA1 EM_DA2 EM_DA3 EM_DA4 EM_DA5 EM_DA6 EM_DA7 EM_DA8 EM_DA9 EM_DA10 EM_DA11 EM_DA12 EM_DA13 EM_DA14 EM_DA15 GND GND GND GND LDOBAT_IN LDO_EN LDO_IN LDO_OUT NRESET NSHDN NSLEEP NTRST P0 P1 Notes:
ATR0621P Pinout (Continued)
LFBGA100 C6 F8 B3 C5 B6 B10 C7 C10 D10 E7 E9 B7 B8 A9 C8 B9 D8 C9 D9 E8 A1 A10 K1 K10 K8 H7 K7 H6 C4 G7 J6 K2 K9 G3 Pin Type OUT OUT OUT OUT I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O IN IN IN IN IN IN IN OUT I/O OUT OUT IN I/O I/O PD PD Configurable (PD) NANTSHORT GPSMODE0 AGCOUT1 Open Drain PU PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD Pull Resistor (Reset Value)(1) Firmware Label PIO Bank A PIO Bank B
1. PD = internal pull-down resistor, PU = internal pull-up resistor, OH = switched to Output High at reset 2. VBAT18 represent the internal power supply of the backup power domain, see section "Power Supply" on page 21 3. VDDIO is the supply voltage for the following GPIO pins: P1, P2, P8, P12, P14, P16, P17, P18, P19, P20, P21, P23, P24, P25, P26, P27 and P29, see section "Power Supply" on page 21 4. VDD_USB is the supply voltage for the following USB pins: USB_DM and USB_DP, see section "Power Supply" on page 21. For operation of the USB interface, supply of 3.0V to 3.6V is required. 5. This pin is not connected
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4890H-GPS-08/08
ATR0621P
Table 3-1.
Pin Name P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 RF_ON SIGHI0 SIGLO0 TCK Notes:
ATR0621P Pinout (Continued)
LFBGA100 G4 H5 A7 B1 A8 D2 G2 J8 E4 H10 F3 G10 J5 K5 E1 J4 K4 F1 H2 F2 H8 H3 H1 D1 G8 E2 G1 E3 G5 H9 K6 F9 E10 J3 Pin Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O OUT IN IN IN PU Pull Resistor (Reset Value)(1) Configurable (PD) OH OH OH OH OH Configurable (PD) PU to VBAT18 OH OH Configurable (PU) PU to VBAT18 Configurable (PD) PD Configurable (PU) Configurable (PD) Configurable (PU) Configurable (PU) Configurable (PD) Configurable (PU) PU to VBAT18 Configurable (PU) Configurable (PU) Configurable (PD) Configurable (PU) Configurable (PU) OH Configurable (PU) PD PU to VBAT18 PD Firmware Label BOOT_MODE NCS1 NCS0 NWE/NWR0 NOE/NRD NUB/NWR1 STATUSLED EXTINT0 EM_A0/NLB EM_A21 GPSMODE2 GPSMODE3 NAADET1 ANTON NEEPROM GPSMODE5 TXD1 GPSMODE6 TIMEPULSE TXD2 RXD2 GPSMODE7 GPSMODE8 NAADET0 GPSMODE10 GPSMODE11 EM_A20 GPSMODE12 AGCOUT0 RXD1 RXD1 RXD2 SCK MOSI MISO NSS SCK MOSI MISO NPCS0 NPCS1 NCS3 NPCS3 AGCOUT0 "0" EM_A20 MCLK_OUT "0" "0" "0" SIGLO1 SCK2 SCK2 TXD2 SIGHI1 SCK1 SCK1 TXD1 "0" "0" TIMEPULSE "0" NWD_OVF EXTINT1 "0" EXTINT0 EM_A0/NLB NCS2 NPCS2 "0" EM_A21 PIO Bank A "0" NCS1 NCS0 NWE/NWR0 NOE/NRD NUB/NWR1 "0" "0" "0" "0" "0" "0" PIO Bank B
1. PD = internal pull-down resistor, PU = internal pull-up resistor, OH = switched to Output High at reset 2. VBAT18 represent the internal power supply of the backup power domain, see section "Power Supply" on page 21 3. VDDIO is the supply voltage for the following GPIO pins: P1, P2, P8, P12, P14, P16, P17, P18, P19, P20, P21, P23, P24, P25, P26, P27 and P29, see section "Power Supply" on page 21 4. VDD_USB is the supply voltage for the following USB pins: USB_DM and USB_DP, see section "Power Supply" on page 21. For operation of the USB interface, supply of 3.0V to 3.6V is required. 5. This pin is not connected
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4890H-GPS-08/08
Table 3-1.
Pin Name TDI TDO TMS USB_DM USB_DP VBAT VBAT18
(2)
ATR0621P Pinout (Continued)
LFBGA100 J2 K3 J1 F10 D3 J7 G6 E6 F7 F6 E5 F5 J9 J10 F4 Pin Type IN OUT IN I/O I/O IN OUT IN IN IN IN IN IN OUT PU Pull Resistor (Reset Value)(1) PU Firmware Label PIO Bank A PIO Bank B
VDD18 VDD18 VDD18 VDDIO
(3) (4)
VDD_USB XT_IN
XT_OUT NC Notes:
(5)
1. PD = internal pull-down resistor, PU = internal pull-up resistor, OH = switched to Output High at reset 2. VBAT18 represent the internal power supply of the backup power domain, see section "Power Supply" on page 21 3. VDDIO is the supply voltage for the following GPIO pins: P1, P2, P8, P12, P14, P16, P17, P18, P19, P20, P21, P23, P24, P25, P26, P27 and P29, see section "Power Supply" on page 21 4. VDD_USB is the supply voltage for the following USB pins: USB_DM and USB_DP, see section "Power Supply" on page 21. For operation of the USB interface, supply of 3.0V to 3.6V is required. 5. This pin is not connected
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4890H-GPS-08/08
ATR0621P
3.2 Signal Description
ATR0621P Signal Description
Name EM_A0 to EM_A21 NCS0 to NCS1 NCS2 to NCS3 NWR0 NWR1 EBI NRD NWE NOE NUB NLB BOOT_MODE TXD1-2 USART RXD1-2 SCK1-2 USB APMC AIC USB_DP USB_DM RF_ON EXTINT0-1 External interrupt request Function External memory address bus Chip select Chip select Lower byte write signal Upper byte write signal Read signal Write enable Output enable Upper byte select (16-bit SRAM) Lower byte select (16-bit SRAM) Boot mode input Transmit data output Receive data input External synchronous serial clock USB data (D+) USB data (D-) Type Output I/O Output Output Output Output Output Output Output Output Output Input Output Input I/O I/O I/O Output Input Active Level Comment - - Low Low Low Low Low Low Low Low Low - - - - - - - High/ Low/ Edge - Low Low - - - - - Low Low - - Interface to ATR0601 PIO-controlled after reset Interface to ATR0601 PIO-controlled after reset Interface to ATR0601 Connect to pin LDO_EN RTC oscillator RTC oscillator PIO-controlled after reset PIO-controlled after reset PIO-controlled after reset PIO-controlled after reset PIO-controlled after reset PIO-controlled after reset Input after reset (except P3 to P7, P10, P11, P28) All valid after reset Internal pull-down resistor Output high in RESET state Output high in RESET state Output high in RESET state Output high in RESET state Output high in RESET state Output high in RESET state Output high in RESET state Output high in RESET state Output high in RESET state PIO-controlled after reset, internal pull-down resistor PIO-controlled after reset PIO-controlled after reset PIO-controlled after reset
Table 3-2.
Module
EM_DA0 to EM_DA15 External memory data bus
AGC
AGCOUT0-1 NSLEEP
Automatic gain control Sleep output Shutdown output Oscillator input Oscillator output SPI clock Master out slave in Master in slave out Slave select Slave select Watchdog timer overflow Programmable I/O port
Output Output Output Input Output I/O I/O I/O I/O Output Output I/O
RTC
NSHDN XT_IN XT_OUT SCK MOSI
SPI
MISO NSS/NPCS0 NPCS1-3
WD PIO Note:
NWD_OVF P0-31
1. The USB transceiver is disabled if VDD_USB < 2.0V. In this case the pins USB_DM and USB_DP are connected to GND (internal pull-down resistors). The USB transceiver is enabled if VDD_USB is within 3.0V and 3.6V.
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Table 3-2.
Module
ATR0621P Signal Description (Continued)
Name SIGHI0 SIGLO0 Function Digital IF Digital IF Digital IF Digital IF GPS synchronized time pulse GPS mode Status LED Enable EEPROM support Active antenna power on output Active antenna short circuit detection Input Active antenna detection input Test mode select Test data in Test data out Test clock Test reset input Debug enable Clock input Master clock output Reset input Type Input Input Input Input Output Input Output Input Output Input Input Input Input Output Input Input Input Input Output I/O Power Power Power Power Power Power Out LDO in LDO out LDO enable Power Power Input Active Level Comment - - - - - - - Low - Low Low - - - - Low High - - Low - - - - - - - - - - Interface to ATR0601 Interface to ATR0601 PIO-controlled after reset PIO-controlled after reset PIO-controlled after reset PIO-controlled after reset PIO-controlled after reset PIO-controlled after reset PIO-controlled after reset PIO-controlled after reset PIO-controlled after reset Internal pull-up resistor Internal pull-up resistor Output high in RESET state Internal pull-up resistor Internal pull-down resistor Internal pull-down resistor Interface to ATR0601, Schmitt trigger input PIO-controlled after reset Open drain with internal pull-up resistor Core voltage 1.8V Variable I/O voltage 1.65V to 3.6V USB voltage 0 to 2.0V or 3.0Vto 3.6V(1) Ground 2.3V to 3.6V 1.5V to 3.6V 1.8V backup voltage 2.3V to 3.6V 1.8V core voltage, maximum 80 mA
GPS
SIGHI1 SIGLO1 TIMEPULSE GPSMODE0-12 STATUSLED NEEPROM
CONFIG
ANTON NANTSHORT NAADET0-1 TMS TDI TDO TCK NTRST DBG_EN
JTAG/ICE
CLOCK
CLK23 MCLK_OUT
RESET
NRESET VDD18 VDDIO
POWER
VDD_USB GND LDOBAT_IN
LDOBAT
VBAT VBAT18 LDO_IN
LDO18
LDO_OUT LDO_EN
Note:
1. The USB transceiver is disabled if VDD_USB < 2.0V. In this case the pins USB_DM and USB_DP are connected to GND (internal pull-down resistors). The USB transceiver is enabled if VDD_USB is within 3.0V and 3.6V.
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ATR0621P
3.3 Setting GPSMODE0 to GPSMODE12
The start-up configuration of a ROM-based system without external non-volatile memory is defined by the status of the GPSMODE pins after system reset. Alternatively, the system can be configured through message commands passed through the serial interface after start-up. This configuration of the ATR0621P can be stored in an external non-volatile memory like FLASH memory or EEPROM. Default designates settings used by ROM firmware if GPSMODE configuration is disabled (GPSMODE0 =0).
Table 3-3.
Pin
GPSMODE Functions
Function Enable configuration with GPSMODE pins This pin (EXTINT0) is used for FixNowTM functionality and not used for GPSMODE configuration GPS sensitivity settings This pin (NAADET1) is used as active antenna supervisor input and not used for GPSMODE configuration. This is the default selection if GPSMODE configuration is disabled. Serial I/O configuration USB power mode General I/O configuration This pin (NAADET0) is used as active antenna supervisor input and not used for GPSMODE configuration General I/O configuration
GPSMODE0 (P1) GPSMODE1 (P9) GPSMODE2 (P12) GPSMODE3 (P13) GPSMODE4 (P14) GPSMODE5 (P17) GPSMODE6 (P19) GPSMODE7 (P23) GPSMODE8 (P24) GPSMODE9 (P25) GPSMODE10 (P26) GPSMODE11 (P27)
GPSMODE12 (P29) Serial I/O configuration
In the case that GPSMODE pins with internal pull-up or pull-down resistors are connected to GND/VDD18, additional current is drawn over these resistors. Especially GPSMODE3 can impact the back-up current. 3.3.1 Enable GPSMODE Pin Configuration Table 3-4. Enable Configuration with GPSMODE Pins
GPSMODE0 (Reset = PD) Description 0(1) 1 Note: Ignore all GPSMODE pins. The default settings as indicated below are used. Use settings as specified with GPSMODE[2, 3, 5 to 8, 10 to 12] 1. Leave open
If the GPSMODE configuration is enabled (GPSMODE0 = 1) and the other GPSMODE pins are not connected externally, the reset default values of the internal pull-down and pull-up resistors will be used.
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3.3.2
Sensitivity Settings Table 3-5.
GPSMODE3 (Fixed PU) 0(1) 0
(1)
GPS Sensitivity Settings
GPSMODE2 (Reset = PU) Description 0 1
(2)
Auto mode Fast mode Normal mode (Default ROM value) High sensitivity
1(2) 1(2) Notes:
0 1(2)
1. Increased back-up current 2. Leave open
For all GPS receivers the sensitivity depends on the integration time of the GPS signals. Therefore there is a trade-off between sensitivity and the time to detect the GPS signal (Time to first fix). The three modes, "Fast Acquisition", "Normal" and "High Sensitivity", have a fixed integration time. The "Normal" mode, recommended for the most applications, is a trade off between the sensitivity and TTFF. The "Fast Acquisition" mode is optimized for fast acquisition, at the cost of a lower sensitivity. The "High Sensitivity" mode is optimized for higher sensitivity, at the cost of longer TTFF. The "Auto" mode adjusts the integration time (sensitivity) automatically according to the measured signal levels. That means the receiver with this setting has a fast TTFF at strong signals, a high sensitivity to acquire weak signals but some times at medium signal level a higher TTFF as the "Normal" mode. These sensitivity settings affect only the startup performance not the tracking performance. 3.3.3 Serial I/O Configuration The ATR0621P features a two-stage I/O message and protocol selection procedure for the two available serial ports. At the first stage, a certain protocol can be enabled or disabled for a given USART port or the USB port. Selectable protocols are RTCM, NMEA and UBX. At the second stage, messages can be enabled or disabled for each enabled protocol on each port. In all configurations discussed below, all protocols are enabled on all ports. But output messages are enabled in a way that ports appear to communicate at only one protocol. However, each port will accept any input message in any of the three implemented protocols.
Table 3-6.
GPSMODE12 (Reset = PU) 0 0 0 0 1(2) 1 1 Notes: 1
(2) (2) (2)
Serial I/O Configuration
GPSMODE6 (Reset = PU) 0 0 1 1
(2) (2)
USART1/USB USART2 GPSMODE5 (Output Protocol/ (Output Protocol/ (Reset = PD) Baud Rate (kBaud)) Baud Rate (kBaud)) Messages(1) Information Messages 0(2) 1 0
(2)
UBX/57.6 UBX/38.4 UBX/19.2 -/Auto NMEA/19.2 NMEA/4.8 NMEA/9.6 UBX/115.2
NMEA/19.2 NMEA/9.6 NMEA/4.8 -/Auto UBX/57.6 UBX/19.2 UBX/38.4 NMEA/19.2
High Medium Low Off High Low Medium Debug
User, Notice, Warning, Error User, Notice, Warning, Error User, Notice, Warning, Error None User, Notice, Warning, Error User, Notice, Warning, Error User, Notice, Warning, Error All
1 0(2) 1 0
(2)
0 0 1 1
(2) (2)
1
1. See Table 3-7 to Table 3-10 on page 13, the messages are described in the ANTARIS4 protocol specification 2. Leave open
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ATR0621P
Both USART ports and the USB port accept input messages in all three supported protocols (NMEA, RTCM and UBX) at the configured baud rate. Input messages of all three protocols can be arbitrarily mixed. Response to a query input message will always use the same protocol as the query input message. The USB port does only accept NMEA and UBX as input protocol by default. RTCM can be enabled via protocol messages on demand. In Auto Mode, no output message is sent out by default, but all input messages are accepted at any supported baud rate. Again, USB is restricted to only NMEA and UBX protocols. Response to query input commands will be given the same protocol and baud rate as it was used for the query command. Using the respective configuration commands, periodic output messages can be enabled. The following message settings are used in the tables below:
Table 3-7.
NMEA Port UBX Port
Supported Messages at Setting Low
Standard NAV MON GGA, RMC SOL, SVINFO EXCEPT
Table 3-8.
NMEA Port UBX Port
Supported Messages at Setting Medium
Standard NAV MON GGA, RMC, GSA, GSV, GLL, VTG, ZDA SOL, SVINFO, POSECEF, POSLLH, STATUS, DOP, VELECEF, VELNED, TIMEGPS, TIMEUTC, CLOCK EXCEPT
Table 3-9.
NMEA Port
Supported Messages at Setting High
Standard Proprietary NAV MON GGA, RMC, GSA, GSV, GLL, VTG, ZDA, GRS, GST PUBX00, PUBX03, PUBX04 SOL, SVINFO, POSECEF, POSLLH, STATUS, DOP, VELECEF, VELNED, TIMEGPS, TIMEUTC, CLOCK SCHD, IO, IPC, EXCEPT
UBX Port
Table 3-10.
Supported Messages at Setting Debug (Additional Undocumented Message May be Part of Output Data)
Standard Proprietary NAV GGA, RMC, GSA, GSV, GLL, VTG, ZDA, GRS, GST PUBX00, PUBX03, PUBX04 SOL, SVINFO, POSECEF, POSLLH, STATUS, DOP, VELECEF, VELNED, TIMEGPS, TIMEUTC, CLOCK SCHD, IO, IPC, EXCEPT RAW (RAW message support requires an additional license)
NMEA Port
UBX Port
MON RXM
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The following settings apply if GPSMODE configuration is not enabled, that is, GPSMODE = 0 (ROM-Defaults):
Table 3-11.
Serial I/O Default Setting if GPSMODE Configuration is Deselected (GPSMODE0 = 0)
USB NMEA USART1 NMEA 57.6 UBX, NMEA NMEA GGA, RMC, GSA, GSV UBX, NMEA, RTCM NMEA GGA, RMC, GSA, GSV User, Notice, Warning, Error USART2 UBX 57.6 UBX, NMEA, RTCM UBX NAV: SOL, SVINFO MON: EXCEPT User, Notice, Warning, Error
Baud rate (kBaud) Input protocol Output protocol Messages
Information User Notice, Warning, messages (UBX INF Error or NMEA TXT)
3.3.4
USB Power Mode For correct response to the USB host queries, the device has to know its power mode. This is configured via GPSMODE7. If set to bus powered, an upper current limit of 100 mA is reported to the USB host; that is, the device classifies itself as a "low-power bus-powered function" with no more than one USB power unit load.
Table 3-12.
0 1 Note:
USB Power Modes
USB device is bus-powered (maximum current limit 100 mA) USB device is self-powered (default ROM value)
GPSMODE7 (Reset = PU) Description
(1)
1. Leave open
3.3.5
Active Antenna Supervisor The two pins P0/NANTSHORT and P15/ANTON plus one pin of P25/NAADET0/MISO or P14/NAADET1 are always initialized as general purpose I/Os and used as follows: * P15/ANTON is an output which can be used to switch on and off antenna power supply. * Input P0/NANTSHORT will indicate an antenna short circuit, i.e. zero DC voltage at the antenna, to the firmware. If the antenna is switched off by output P15/ANTON, it is assumed that also input P0/NANTSHORT will signal zero DC voltage, i.e. switch to its active low state. * Input P25/NAADET0/MISO or P14/NAADET1 will indicate a DC current into the antenna. In case of short circuit, both P0 and P25/P14 will be active, i.e. at low level. If the antenna is switched off by output P15/ANTON, it is assumed that also input P25/NAADET0/MISO will signal zero DC current, i.e. switch to its active low state. Which pin is used as NAADET (P14 or P25) depends on the settings of GPSMODE11 and GPSMODE10 (see Table 3-14 on page 15).
14
ATR0621P
4890H-GPS-08/08
ATR0621P
Table 3-13.
Pin P0/NANTSHORT P25/NAADET0/ MISO or P14/NAADET1 P15/ANTON
Pin Usage of Active Antenna Supervisor
Usage NANTSHORT Meaning Active antenna short circuit detection High = No antenna DC short circuit present Low = Antenna DC short circuit present Active antenna detection input High = No active antenna present Low = Active antenna is present Active antenna power on output High = Power supply to active antenna is switched on Low = Power supply to active antenna is switched off
NAADET
ANTON
Table 3-14.
Antenna Detection I/O Settings
Comment
GPSMODE11 GPSMODE10 GPSMODE8 (Reset = PU) (Reset = PU) (Reset = PU) Location of NAADET 0 0 0 0 1(1) 1(1) 1(1) 1 Note:
(1)
0 0 1(1) 1(1) 0 0 1(1) 1
(1)
0 1(1) 0 1(1) 0 1(1) 0 1
(1)
P25/NAADET0/MISO P25/NAADET0/MISO P14/NAADET1 P14/NAADET1 (Default ROM value) P14/NAADET1 P14/NAADET1 P25/NAADET0/MISO P25/NAADET0/MISO Reserved for further use. Do not use this setting. Reserved for further use. Do not use this setting. Reserved for further use. Do not use this setting.
1. Leave open
The Antenna Supervisor Software will be configured as follows: 1. Enable Control Signal 2. Enable Short Circuit Detection (power down antenna via ANTON if short is detected via NANTSHORT) 3. Enable Open Circuit Detection via NAADET The antenna supervisor function may not be disabled by GPSMODE pin selection. If the antenna supervisor function is not used, please leave open ANTON, NANTSHORT and NAADET.
15
4890H-GPS-08/08
3.4
External Connections for a Working GPS System
Example of an External Connection
SIGH SIGL SC PuRF PuXTO NC see Table 3-15 NC SIGHI SIGLO CLK23 RF_ON NSLEEP NRESET EM_DA0 - 15 EM_A1 - 19
Figure 3-2.
ATR0601
ATR0621P
P8 P20 USB_DM USB_DP P31 P18 P22 P21
STATUS LED TIMEPULSE Optional USB Optional USART 1 Optional USART 2
see Table 3-15 see Table 3-15 see Table 3-15 see Table 3-15 see Table 3-15 NC NC NC NC NC NC GND +3V (see Power Supply)
P0 - 7 P9 - 15 P16 - 17 P19 P23 - 30 TMS TCK TDI NTRST TDO DBG_EN GND NSHDN LDO_EN LDO_OUT VDD18 LDO_IN LDOBAT_IN VBAT18 VBAT
XT_IN XT_OUT 32.368 kHz (see RTC)
+3V (see Power Supply)
VDDIO
+3V (see Power Supply)
VDD_USB
+3V (see Power Supply) GND
NC: Not connected
16
ATR0621P
4890H-GPS-08/08
ATR0621P
Table 3-15.
Pin Name P0/NANTSHORT
Recommended Pin Connection
Recommended External Circuit Internal pull-down resistor, leave open if Antenna Supervision functionality is unused. Internal pull-down resistor, leave open, in order to disable the GPSMODE pin configuration feature. Connect to VDD18 to enable the GPSMODE pin configuration feature. Refer to GPSMODE definitions in section "Setting GPSMODE0 to GPSMODE12" on page 11. Can be left open if configured as output by user application. Internal pull-down resistor, leave open. Output in default ROM firmware: leave open, only needs pull-up resistor to VDD18 or pull-down resistor to GND if used as GPIO input by user application and is not always driven from external sources. Output in default ROM firmware: leave open, only needs pull-up resistor to VDD18 or pull-down resistor to GND if used as GPIO input by user application and is not always driven from external sources. Output in default ROM firmware: leave open, only needs pull-up resistor to VDD18 or pull-down resistor to GND if used as GPIO input by user application and is not always driven from external sources. Output in default ROM firmware: leave open, only needs pull-up resistor to VDD18 or pull-down resistor to GND if used as GPIO input by user application and is not always driven from external sources. Output in default ROM firmware: leave open, only needs pull-up resistor to VDD18 or pull-down resistor to GND if used as GPIO input by user application and is not always driven from external sources. Output in default ROM firmware: leave open, only needs pull-up resistor to VDD18 or pull-down resistor to GND if used as GPIO input by user application and is not always driven from external sources. Internal pull-up resistor, leave open if unused. Output in default ROM firmware: leave open, only needs pull-up resistor to VDD18 or pull-down resistor to GND if used as GPIO input by user application and is not always driven from external sources. Output in default ROM firmware: leave open, only needs pull-up resistor to VDD18 or pull-down resistor to GND if used as GPIO input by user application and is not always driven from external sources. Internal pull-up resistor, can be left open if the GPSMODE feature is not used or configured as output by user application. Refer to GPSMODE definitions in section "Setting GPSMODE0 to GPSMODE12" on page 11. Internal pull-up resistor, can be left open if the GPSMODE feature is not used or configured as output by user application. Refer to GPSMODE definitions in section "Setting GPSMODE0 to GPSMODE12" on page 11. Internal pull-down resistor, leave open if Antenna Supervision functionality is unused. Internal pull-down resistor, leave open if Antenna Supervision functionality is unused. Internal pull-up resistor, leave open if no serial EEPROM is connected. Otherwise connect to GND. Internal pull-down resistor, can be left open if the GPSMODE feature is not used or configured as output by user application. Refer to GPSMODE definitions in section "Setting GPSMODE0 to GPSMODE12" on page 11. Output in default ROM firmware: leave open if serial interface is not used. Internal pull-up resistor, can be left open if the GPSMODE feature is not used or configured as output by user application. Refer to GPSMODE definitions in section "Setting GPSMODE0 to GPSMODE12" on page 11. Output in default ROM firmware: leave open if timepulse feature is not used. Output in default ROM firmware: leave open if serial interface not used. Internal pull-up resistor, leave open if serial interface is not used. Internal pull-up resistor, can be left open if the GPSMODE feature is not used or configured as output by user application. Refer to GPSMODE definitions in section "Setting GPSMODE0 to GPSMODE12" on page 11.
P1/GPSMODE0
P2/BOOT_MODE P3/NCS1 P4/NCS0 P5/NWE/NWR0 P6/NOE/NRD P7/NUB/NWR1 P8/STATUSLED P9/EXTINT0 P10/EM_A0/NLB P11/EM_A21/NCS2
P12/GPSMODE2/NPCS2
P13/GPSMODE3/EXTINT1 P14/NAADET1 P15/ANTON P16/NEEPROM P17/GPSMODE5/SCK1 P18/TXD1 P19/GPSMODE6/SIGLO1 P20/TIMEPULSE/SCK2 P21/TXD2 P22/RXD2 P23/GPSMODE7/SCK
17
4890H-GPS-08/08
Table 3-15.
Pin Name
Recommended Pin Connection (Continued)
Recommended External Circuit Internal pull-up resistor, can be left open if the GPSMODE feature is not used or configured as output by user application. Refer to GPSMODE definitions in section "Setting GPSMODE0 to GPSMODE12" on page 11. Internal pull-down resistor, leave open if Antenna Supervision functionality is unused. Can be left open if configured as output by user application. Internal pull-up resistor, can be left open if the GPSMODE feature is not used or configured as output by user application. Refer to GPSMODE definitions in section "Setting GPSMODE0 to GPSMODE12" on page 11. Internal pull-up resistor, can be left open if the GPSMODE feature is not used or configured as output by user application. Refer to GPSMODE definitions in section "Setting GPSMODE0 to GPSMODE12" on page 11. Output in default ROM firmware: leave open, only needs pull-up resistor to VDD18 or pull-down resistor to GND if used as GPIO input by user application and is not always driven from external sources. Internal pull-up resistor, can be left open if the GPSMODE feature is not used or configured as output by user application. Refer to GPSMODE definitions in section "Setting GPSMODE0 to GPSMODE12" on page 11. Internal pull-down resistor, leave open. Internal pull-up resistor, leave open if serial interface is not used. If no external memory is used, could be leave open (internal pull-down).
P24/GPSMODE8/MOSI
P25/NAADET0/MISO P26/GPSMODE10/NSS/ NPCS0
P27/GPSMODE11/NPCS1
P28/EM_A20/NCS3
P29/GPSMODE12/NPCS3 P30/AGCOUT0 P31/RXD1 EM_DA0 - EM_DA15
18
ATR0621P
4890H-GPS-08/08
ATR0621P
3.4.1 Connecting an Optional FLASH Memory The ATR0621P offers the possibility to connect an external FLASH memory. The high performance ARM7TM 32-bit RISC processor of the ATR0621P can be used to run application specific code, that is stored in the FLASH memory. The 32-bit RISC processor of the ATR0621 accesses the external memory via the EBI (External Bus Interface). Atmel recommends to use 1.8V FLASH memory, e.g. the Atmel AT49SV802A. The LDO_OUT pin of the ATR0621P can supply the external FLASH memory. Figure 3-3 shows an example of the external FLASH memory connection. Figure 3-3. Example of an External FLASH Memory Connection
I/O0-15 A0-18 CE_N WE_N OE_N EM_DA0-15 EM_A1-19 P4/NCS0 P5/NWE P6/NOE
AT49SV802A
ATR0621P
BYTE_N READY/BUSY_N
NC
RESET_N
NRESET
NC VSS GND
NC
GND GND GND NSHDN LDO_EN LDO_OUT VDD18 LDO_IN LDOBAT_IN
+3V (see Power Supply)
NC: Not connected
19
4890H-GPS-08/08
3.4.2
Connecting an Optional Serial EEPROM The ATR0621P offers the possibility to connect an external serial EEPROM. The internal ROM firmware supports to store the configuration of the ATR0621P in serial EEPROM. The pin P16/NEEPROM signals the firmware that a serial EEPROM is connected with the ATR0621P. The 32-bit RISC processor of the ATR0621P accesses the external memory with SPI (Serial Peripheral Interface). Atmel recommends to use 32 Kbit 1.8V serial EEPROM, e.g. the Atmel AT25320AY1-1.8. Figure 3-4 shows an example of the serial EEPROM connection. Figure 3-4. Example of a Serial EEPROM Connection
SCK SI SO CS_N
AT25320AY1-1.8
ATR0621P P23/SCK P24/MOSI P25/MISO/NAADET0 P29/NPCS3
HOLD_N WP_N
GND NC
P16/NEEPROM P1/GPSMODE0
GND
+3V (see Power Supply)
GND NSHDN LDO_EN LDO_OUT VDD18 VDDIO
LDO_IN LDOBAT_IN NC: Not connected
Note:
The GPSMODE pin configuration feature can be disabled, because the configuration can be stored in the serial EEPROM. VDDIO is the supply voltage for the pins: P23, P24, P25 and P29.
20
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4890H-GPS-08/08
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4. Power Supply
The baseband IC is supplied with four distinct supply voltages: * VDD18, the nominal 1.8V supply voltage for the core, the RF-I/O pins, the memory interface and the test pins and all GPIO-pins not mentioned in next item. * VDDIO, the variable supply voltage within 1.8V to 3.6V for following GPIO-pins: P1, P2, P8, P12, P14, P16, P17, P18, P19, P20, P21, P23, P24, P25, P26, P27 and P29. In input mode, these pins are 5V input tolerant. * VDD_USB, the power supply of the USB pins: USB_DM and USB_DP. * VBAT18 to supply the backup domain: RTC, backup SRAM and the pins NSLEEP, NSHDN, LDO_EN, VBAT18, P9/EXTIN0, P13/EXTINT1, P22/RXD2 and P31/RXD1 and the 32kHz oscillator. In input mode, the four GPIO-pins are 5V input tolerant. Figure 4-1, Figure 4-2 and Figure 4-3 show examples of the wiring of ATR0621 power supply. Figure 4-1. External Wiring Example Using Internal LDOs and Backup Power Supply
ATR0621P internal
2.3V to 3.6V LDO_IN NSHDN LDO_EN LDO_OUT ldoin ldoen ldoout LDO18
VDD18
Core
1 F (X7R)
VDDIO
1.8V to 3.3V variable IO Domain
LDOBAT
ldobat_in LDOBAT_IN 1.5V to 3.6V VBAT VBAT18 vbat vbat18
1 F (X7R)
vdd
RTC Backup Memory
0V or 3V to 3.6V
VDDUSB
USB SM and Transceiver
21
4890H-GPS-08/08
The baseband IC contains a built in low dropout voltage regulator LDO18. This regulator can be used if the host system does not provide the core voltage VDD18 of 1.8V nominal. In such case, LDO18 will provide a 1.8V supply voltage from any input voltage VDD between 2.3V and 3.6V. It will also allow supplying external components such as FLASH memory with 1.8V. The LDO_EN input can be used to shut down VDD18 if the system is in standby mode. If the host system does however supply a 1.8V core voltage directly, this voltage has to be connected to the VDD18 supply pins of the baseband IC. LDO_EN must be connected to GND. LDO_IN can be connected to GND. LDO_OUT must not be connected. A second built in low dropout voltage regulator LDOBAT provides the supply voltage for the RTC and backup SRAM from any input voltage VBAT between 1.5V and 3.6V. The backup battery is only discharged if VDD - supplied via pin LDOBAT_IN - is shut down. Only after VDD18 has been supplied to ATR0621 the RTC section will be initialized properly. If only VBAT is applied first, the current consumption of the RTC and backup SRAM is undetermined. Figure 4-2. External Wiring Example Using 1.8V from Host System and Backup Power Supply
ATR0621P internal
LDO18
LDO_IN LDO_EN LDO_OUT
ldoin ldoen ldoout
1.65V to 1.95V VDD18
Core
1 F (X7R)
2.3V to 3.6V
VDDIO
1.8V to 3.3V variable IO Domain
LDOBAT
ldobat_in LDOBAT_IN 1.5V to 3.6V VBAT VBAT18 vbat vbat18
1 F (X7R)
vdd
RTC Backup Memory
0V or 3V to 3.6V
VDDUSB
USB SM and Transceiver
22
ATR0621P
4890H-GPS-08/08
ATR0621P
The USB Transceiver is disabled if VDD_USB < 2.0V. In this case the pins USB_DM and USB_DP are connected to GND (internal pull-down resistors). The USB Transceiver is enabled if VDD_USB within 3.0V and 3.6V. Figure 4-3. External Wiring Example Using Internal LDOs, USB Supply Voltage and Backup Power Supply
ATR0621P internal
LDO18
LDO_IN NSHDN LDO_EN LDO_OUT
ldoin ldoen ldoout
VDD18
Core
1 F (X7R)
VDDIO
1.8V to 3.3V variable IO Domain
LDOBAT
ldobat_in LDOBAT_IN 1.5V to 3.6V VBAT VBAT18 vbat vbat18
1 F (X7R)
vdd
RTC Backup Memory
USB-VSB 5V
External LDO 3.3V
VDDUSB
USB SM and Transceiver
23
4890H-GPS-08/08
5. RTC Oscillator
Figure 5-1. Crystal Connection
ATR0621P internal
XT_IN 32 kHz Crystal Oscillator XT_OUT
32.768 kHz 50 ppm
32.768 kHz clock
RTC
C
C
C = 2 x Cload, Cload can be derived from the crystal datasheet. Maximum value for C is 25 pF.
6. Absolute Maximum Ratings
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters Operating free air temperature range Storage temperature VDD18 VDDIO DC supply voltage VDD_USB LDO_IN LDOBAT_IN VBAT EM_DA0 to EM_DA15, P0, P3 to P7, P10, P11, P15, P28, P30, SIGHI, SIGLO, CLK23, XT_IN, TMS, TCK, TDI, NTRST, DBG_EN, LDO_EN, NRESET USB_DM, USB_DP Pin Symbol Min. -40 -60 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 Max. +85 +150 +1.95 +3.6 +3.6 +3.6 +3.6 +3.6 Unit C C V V V V V V
-0.3
+1.95
V
DC input voltage
-0.3
+3.6 +5.0
V V
Note:
P1, P2, P8, P9, P12 to P14, -0.3 P16 to P27, P29, P31 Minimum/maximum limits are at +25C ambient temperature, unless otherwise specified
7. Thermal Resistance
Parameters Junction ambient, according to JEDEC51-9 Symbol RthJA Value 36.9 Unit K/W
24
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4890H-GPS-08/08
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8. Electrical Characteristics - DC Characteristics
If no additional information is given in column Test Conditions, the values apply to a temperature range from -40C to +85C. No. Parameters 1.1 DC supply voltage core DC supply voltage VDDIO 1.2 domain(1) 1.3 DC supply voltage USB(2) 1.4 DC supply voltage backup domain(3) Test Conditions Pin VDD18 VDDIO VDD_USB VBAT18 Symbol VDD18 VDDIO VDDUSB VBAT18 VO,18 VO,IO VDD18 = 1.65V to 1.95V VDD18 = 1.65V to 1.95V VDD18 = 1.65V to 1.95V VDD18 = 1.65V to 1.95V CLK23 CLK23 CLK23 NRESET NRESET VIL,18 VIH,18 Vth+,CLK23 Vth-,CLK23 Vhyst,CLK23 Vth+,NRESET Vth-,NRESET VIL,IO VIH,IO P9, P13, P22, P31 P9, P13, P22, P31 DP, DM VIL,BAT VIH,BAT VIL,USB 0.3 x VDD18 0.2 0.8 0.46 -0.3 1.46 -0.3 1.46 -0.3 0.55 1.3 0.77 +0.41 5.0 +0.41 5.0 +0.8 Min. 1.65 1.65 3.0 1.65 0 0 -0.3 0.7 x VDD18 Typ. 1.8 1.8/3.3 3.3 1.8 Max. 1.95 3.6 3.6 1.95 VDD18 VDDIO 0.3 x VDD18 VDD18 + 0.3 0.7 x VDD18 Unit V V V V V V V V V V V V V V V V V V Type* D D D D D D C C C C C C C C C C C C
1.5 DC output voltage VDD18 1.6 DC output voltage VDDIO 1.7 1.8 1.9 1.10 Low-level input voltage VDD18 domain High-level input voltage VDD18 domain Schmitt trigger threshold rising Schmitt trigger threshold falling
1.11 Schmitt trigger hysteresis VDD18 = 1.65V to 1.95V Schmitt trigger threshold 1.12 rising 1.13 1.14 1.15 1.16 1.17 1.18 Schmitt trigger threshold falling Low-level input voltage VDDIO domain High-level input voltage VDDIO domain Low-level input voltage VBAT18 domain High-level input voltage VBAT18 domain Low-level input voltage USB VDD18 = 1.65V to 1.95V VDD18 = 1.65V to 1.95V VDDIO = 1.65V to 3.6V VDDIO = 1.65V to 3.6V VBAT18 = 1.65V to 1.95V VBAT18 = 1.65V to 1.95V VDD_USB = 3.0V to 3.6V VDD_USB = 3.0V to 3.6V, 39 source resistance + 27 external series resistor IOL = 1.5 mA, VDD18 = 1.65V IOH = -1.5 mA, VDD18 = 1.65V
High-level input voltage 1.19 USB Low-level output voltage VDD18 domain High-level output voltage VDD18 domain
DP, DM
VIH,USB
2.0
4.6
V
C
1.20 1.21
VOL,18 VOH,18 VDD18 - 0.45
0.4
V V
A A
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Notes: 1. VDDIO is the supply voltage for the following GPIO-pins: P1, P2, P8, P12, P14, P16, P17, P18, P19, P20, P21, P23, P24, P25, P26, P27 and P29 2. Values defined for operating the USB interface. Otherwise VDD_USB may be connected to ground 3. Supply voltage VBAT18 for backup domain is generated internally by the LDOBAT
25
4890H-GPS-08/08
8. Electrical Characteristics - DC Characteristics (Continued)
If no additional information is given in column Test Conditions, the values apply to a temperature range from -40C to +85C. No. Parameters 1.22 1.23 1.24 1.25 Low-level output voltage VDDIO domain High-level output voltage VDDIO domain Low-level output voltage VBAT18 domain High-level output voltage VBAT18 domain Test Conditions IOL = 1.5 mA, VDDIO = 3.0V IOH = -1.5 mA, VDDIO = 3.0V IOL = 1 mA IOH = -1 mA IOL = 2.2 mA, VDD_USB = 3.0V to 3.6V, 27 external series resistors IOH = -0.2 mA, VDD_USB = 3.0V to 3.6V, 27 external series resistors P9, P13, P22, P31 P9, P13, P22, P31 Pin Symbol VOL,IO VOH,IO VOL,BAT VOH,BAT 1.2 VDDIO - 0.5 0.4 Min. Typ. Max. 0.4 Unit V V V V Type* A A A A
Low-level output voltage 1.26 USB
DP, DM
VOL,USB
0.3
V
A
High-level output voltage 1.27 USB
DP, DM
VOH,USB
2.8
V
A
1.28
Input-leakage current VDD18 = 1.95V (standard inputs and I/Os) VIL=0 V NRESET TCK, TDI, TMS P9, P13, P22, P31 DBG_EN, NTRST, P0, P15, P30, EM_DA[0:15] P1, P2, P8, P12, P14, P[16-21], P[23-27], P29 P1, P2, P8, P12, P14, P[16-21], P[23-27], P29
ILEAK ICAP RPU RPU RPU RPD RPD
-1
1 10
A pF k k k k
C D C C C C
1.29 Input capacitance 1.30 Input pull-up resistor 1.31 Input pull-up resistor 1.32 Input pull-up resistor 1.33 Input pull-down resistor
0.7 7 100 7
1.8 18 235 18
1.34 Input pull-down resistor
100
235
k
C
1.35
Configurable input pull-up VDDIO = 3.6V resistor VPAD = 0V
RCPU
50
160
k
C
1.36
Configurable input pull-down resistor
VDDIO = 3.6V VPAD = 3.6V
RCPD
40
160
k
C
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Notes: 1. VDDIO is the supply voltage for the following GPIO-pins: P1, P2, P8, P12, P14, P16, P17, P18, P19, P20, P21, P23, P24, P25, P26, P27 and P29 2. Values defined for operating the USB interface. Otherwise VDD_USB may be connected to ground 3. Supply voltage VBAT18 for backup domain is generated internally by the LDOBAT
26
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4890H-GPS-08/08
ATR0621P
8. Electrical Characteristics - DC Characteristics (Continued)
If no additional information is given in column Test Conditions, the values apply to a temperature range from -40C to +85C. No. Parameters 1.37 1.38 Configurable input pull-up resistor (idle state) Configurable input pull-up resistor (operation state) Test Conditions Pin USB_DP USB_DP USB_DP USB_DM Symbol RCPU RCPU RPD Min. 0.9 1.425 10 Typ. Max. 1.575 3.09 500 Unit k k k Type* C C C
1.39 Input pull-down resistor
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Notes: 1. VDDIO is the supply voltage for the following GPIO-pins: P1, P2, P8, P12, P14, P16, P17, P18, P19, P20, P21, P23, P24, P25, P26, P27 and P29 2. Values defined for operating the USB interface. Otherwise VDD_USB may be connected to ground 3. Supply voltage VBAT18 for backup domain is generated internally by the LDOBAT
9. Power Consumption
Table 9-1.
Mode Sleep Shutdown
Core Power Consumption
Conditions At 1.8V, no CLK23 RTC, backup SRAM and LDOBAT Satellite acquisition Normal tracking on 6 channels with 1 fix/s; each additional active tracking channel adds 0.5 mA All channels disabled Typ. 0.065 0.007 25 14 11 mA Unit Type* C C C C C
Normal
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
10. ESD Sensitivity
The ATR0621P is an ESD sensitive device. Observe precautions for handling.
Table 10-1.
Test Model
ESD- Sensitivity
Max. TBD Unit V
Human Body Model (HBM)
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4890H-GPS-08/08
11. LDO18
The LDO18 is a built in low dropout voltage regulator which can be used if the host system does not provide the core voltage VDD18.
Table 11-1.
Parameter
Electrical Characteristics of LDO18
Conditions Min. 2.3 1.65 1.8 Typ. Max. 3.6 1.95 80 After startup, no load, at room temperature Standby mode (LDO_EN = 0), at room temperature 1 80 5 Unit V V mA A A Type* D A A A A
Supply voltage LDO_IN Output voltage (LDO_OUT) Output current (LDO_OUT) Current consumption Current consumption
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
For well-defined start up of LDO18, LDO_IN needs to be connected to LDOBAT_IN.
12. LDOBAT and Backup Domain
The LDOBAT is a built in low dropout voltage regulator which provides the supply voltage VBAT18 for the RTC, backup SRAM, P9, P13, P22, P31, NSLEEP and NSHDN. The LDOBAT voltage regulator switches in battery mode if LDOBAT_IN falls below 1.5V. Table 12-1.
Parameter Supply voltage LDOBAT_IN Supply voltage VBAT Output voltage (VBAT18) If switch connects to LDOBAT_IN. Output current (VBAT18) No external load allowed Current consumption LDOBAT_IN(1) Current consumption VBAT(1) Current consumption After startup (sleep/backup mode), at room temperature After startup (backup mode and LDOBAT_IN = 0V), at room temperature After startup (normal mode), at room temperature
Electrical Characteristics of LDOBAT
Conditions Min. 2.3 1.5 1.65 1.8 Typ. Max. 3.6 3.6 1.95 1.5 15 Unit V V V mA A Type* D D A D A
10
A
A
1.5
mA
C
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Note: 1. If no current is caused by outputs (pad output current as well as current across internal pull-up resistors)
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13. Ordering Information
Extended Type Number ATR0621P-7FQY ATR0621P-7FHW ATR0622-EK1 ATR0622-DK1 Package LFBGA100 LFBGA100 MPQ 2000 2000 1 1 Remarks 9 mm x 9 mm, 0.80 mm pitch, ROM5, Pb-free, RoHS-compliant 9 mm x 9 mm, 0.80 mm pitch, ROM5, Pb-free, RoHS-compliant, green Evaluation kit/road test kit Development kit including example design information
14. Package LFBGA100
Package: R-LFBGA 100_G Dimensions in mm 0.08 M 0.15 M A1 Corner Top View 12345 A B C D E F G H J K 6 7 8 9 10 Bottom View 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K A1 Corner C BA 0.38 ... 0.48 (100x)
90.05
7.2
0.8
0.8 A 7.2
technical drawings according to DIN specifications
0.15 (4x) C B 90.05
0.53 ref.
0.12 C
0.2 C
0.27 ... 0.37
1.4 max
Seating plane C
Drawing-No.: 6.580-5003.01-4 Issue: 2; 27.10.05
Moisture sensitivity level (MSL) = 3
(0.36)
29
4890H-GPS-08/08
15. Revision History
Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. Revision No. 4890H-GPS-08/08 4890G-GPS-01/08 4890F-GPS-09/07 4890E-GPS-06/07 History * Section 8 "Electrical Characteristics - DC Characteristics" numbers 1.11, 1.34 and 1.35 on pages 25 to 26 changed * Table 3-1 "ATR0621P Pinout" on page 5 changed * Section 13 "Ordering Information" on page 29 changed * Table 3-1 "ATR0621P Pinout" on page 5 changed * Section 8 "Electrical Characteristics" numbers 1.35 and 1.36 on page 26 changed * * * * * * * All pages: Part number changed in ATR0621P Page 24: Abs. Max. Ratings table: some changes Page 25-27: El. Characteristics table: Type column added Page 27: Power Consumption table: Type column added Page 27: ESD Sensitivity table: Type column added Page 28: LDO18 table: Type column added Page 28: LDOBAT and Backup Domain table: Type column added
4890D-GPS-12/06
4890C-GPS-10/06
* Section 7 "Thermal Resistance" on page 24 added * Section 13 "Ordering Information" on page 29 changed * Table 3-1 "ATR0621 Pinout" on pages 5-8 changed * Section 3.3 "Setting GPSMODE12" on page 11 changed * Table 3-4 "Enable Configuration with GPSMODE Pins" on page 11 changed * Section 3.3.2 "Sensitivity Settings" on page 12 changed * Table 3-5 "GPS Sensitivity Settings" on page 12 changed * Table 3-6 "Serial I/O Configuration" on page 12 changed * Table 3-12 "USB Power Modes" on page 14 changed * Table 3-14 "Antenna Detection I/O Settings" on page 15 changed * Figure 3.2 "Example of an External Connection" on page 16 changed * Table 3-15 "Recommended Pin Connection" on pages 17-18 changed * Section 7 "Electrical Characteristics - DC Characteristics" on pages 25-26 changed * Section 10 "LDO18" on page 27 changed
4890B-GPS-06/06
30
ATR0621P
4890H-GPS-08/08
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4890H-GPS-08/08

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