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| 74LVCV2G66 Overvoltage tolerant bilateral switch Rev. 3 -- 16 June 2010 Product data sheet 1. General description The 74LVCV2G66 is a low-power, low-voltage, high-speed Si-gate CMOS device. The 74LVCV2G66 provides two single pole single throw analog or digital switches. Each switch includes an overvoltage tolerant input/output terminal (pin nZ), an output/input terminal (pin nY) and low-power active HIGH enable input (pin nE). The overvoltage tolerant switch terminals allow the switching of signals in excess of VCC. The low-power enable input eliminates the necessity of using current limiting resistors in portable applications when using control logic signals much lower than VCC. These inputs are also overvoltage tolerant. 2. Features and benefits Wide supply voltage range from 2.3 V to 5.5 V Ultra low-power operation Very low ON resistance: 8.0 (typical) at VCC = 2.7 V 7.5 (typical) at VCC = 3.3 V 7.3 (typical) at VCC = 5.0 V. 5 V tolerant input for interfacing with 5 V logic High noise immunity Switch handling capability of 32 mA CMOS low-power consumption Latch-up performance exceeds 250 mA Incorporates overvoltage tolerant analog switch technology Switch accepts voltages up to 5.5 V independent of VCC Multiple package options Specified from -40 C to +85 C and -40 C to +125 C NXP Semiconductors 74LVCV2G66 Overvoltage tolerant bilateral switch 3. Ordering information Table 1. Ordering information Package Temperature range 74LVCV2G66DP -40 C to +125 C 74LVCV2G66DC -40 C to +125 C 74LVCV2G66GD -40 C to +125 C Name TSSOP8 VSSOP8 XSON8U Description plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm plastic very thin shrink small outline package; 8 leads; body width 2.3 mm plastic extremely thin small outline package; no leads; 8 terminals; UTLP based; body 3 x 2 x 0.5 mm Version SOT505-2 SOT765-1 SOT996-2 Type number 4. Marking Table 2. Marking codes Marking code[1] Y66 Y66 Y66 Type number 74LVCV2G66DP 74LVCV2G66DC 74LVCV2G66GD [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram 1Y 1Z 1 1 1 X1 2 1E 7# 2Z 2Y 5 3# 1 1 X1 001aaa531 6 2E 001aaa530 Fig 1. Logic symbol Fig 2. IEC logic symbol Z Y E VCC 001aaa532 Fig 3. Logic diagram (one switch) 74LVCV2G66 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 3 -- 16 June 2010 2 of 23 NXP Semiconductors 74LVCV2G66 Overvoltage tolerant bilateral switch 6. Pinning information 6.1 Pinning 74LVCV2G66 1Z 1 2 3 4 8 7 6 5 VCC 1E 2Y 2Z 74LVCV2G66 1Z 1Y 2E GND 1 2 3 4 001aai213 1Y 8 7 6 5 VCC 1E 2Y 2Z 2E GND 001aai214 Transparent top view Fig 4. Pin configuration SOT505-2 (TSSOP8) and SOT765-1 (VSSOP8) Fig 5. Pin configuration SOT996-2 (XSON8U) 6.2 Pin description Table 3. Symbol 1Y, 2Y 1Z, 2Z GND 1E, 2E VCC Pin description Pin 2, 6 1, 5 4 7, 3 8 Description independent input or output independent input or output (overvoltage tolerance) ground (0 V) enable input (active HIGH) supply voltage 7. Functional description Table 4: Input nE L H [1] H = HIGH voltage level; L = LOW voltage level. Function table[1] Switch OFF-state ON-state 74LVCV2G66 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 3 -- 16 June 2010 3 of 23 NXP Semiconductors 74LVCV2G66 Overvoltage tolerant bilateral switch 8. Limiting values Table 5: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC VI IIK ISK VSW ISW ICC IGND Tstg Ptot [1] [2] Parameter supply voltage input voltage input clamping current switch clamping current switch voltage switch current supply current ground current storage temperature total power dissipation Conditions [1] Min -0.5 -0.5 -50 -0.5 -100 -65 Max +6.5 +6.5 50 +6.5 50 100 +150 250 Unit V V mA mA V mA mA mA C mW VI < -0.5 V or VI > 6.5 V VI < -0.5 V or VI > 6.5 V enable and disable mode VSW > -0.5 V or VSW < 6.5 V Tamb = -40 C to +125 C [2] - The input and output voltage ratings may be exceeded if the input and output current ratings are observed. For TSSOP8 package: above 55 C the value of Ptot derates linearly with 2.5 mW/K. For VSSOP8 package: above 110 C the value of Ptot derates linearly with 8 mW/K. For XSON8U package: above 118 C the value of Ptot derates linearly with 7.8 mW/K. 9. Recommended operating conditions Table 6: Symbol VCC VI VSW Tamb t/V Recommended operating conditions Parameter supply voltage input voltage switch voltage ambient temperature input transition rise and fall rate VCC = 2.3 V to 2.7 V VCC = 2.7 V to 5.5 V [1] [2] [2] Conditions Min 2.3 0 Typ - Max 5.5 5.5 5.5 +125 20 10 Unit V V V C ns/V ns/V enable and disable mode [1] 0 -40 - To avoid sinking GND current from terminal nZ when switch current flows in terminal nY, the voltage drop across the bidirectional switch must not exceed 0.4 V. If the switch current flows into terminal nZ, no GND current will flow from terminal nY. In this case, there is no limit for the voltage drop across the switch. Applies to control signal levels. [2] 74LVCV2G66 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 3 -- 16 June 2010 4 of 23 NXP Semiconductors 74LVCV2G66 Overvoltage tolerant bilateral switch 10. Static characteristics Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter VIH Conditions -40 C to +85 C Min HIGH-level VCC = 2.3 V to 2.7 V input voltage V = 3.0 V to 3.6 V CC VCC = 4.5 V to 5.5 V VIL LOW-level VCC = 2.3 V to 2.7 V input voltage V = 3.0 V to 3.6 V CC VCC = 4.5 V to 5.5 V II IS(OFF) input leakage pin nE; VI = 5.5 V or GND; current VCC = 0 V to 5.5 V OFF-state leakage current ON-state leakage current supply current additional supply current input capacitance OFF-state capacitance ON-state capacitance VCC = 2.3 V to 5.5 V; see Figure 6 [2] -40 C to +125 C Unit Min 0.6VCC 2.0 0.55VCC Max 0.1VCC 0.5 5 10 V V V V V A A - Typ[1] 0.1 0.1 Max 0.6VCC 2.0 0.55VCC - 0.1VCC 0.5 0.15VCC 5 10 0.15VCC V [2][3] IS(ON) VCC = 2.3 V to 5.5 V; see Figure 7 [2][3] - 0.1 10 - 10 A ICC VI = 5.5 V or GND; VSW = GND or VCC; VCC = 2.3 V to 5.5 V pin nE; VI = VCC - 0.6 V; VSW = GND or VCC; VCC = 3.0 V to 5.5 V [2] - 0.1 10 - 40 A ICC [2] - 0.1 5 - 50 A CI CS(OFF) CS(ON) - 2.5 8.0 16 - - - pF pF pF [1] [2] [3] All typical values are measured at Tamb = 25 C. These typical values are measured at VCC = 3.3 V. For overvoltage signals (VSW > VCC) the condition VY < VZ must be observed. 74LVCV2G66 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 3 -- 16 June 2010 5 of 23 NXP Semiconductors 74LVCV2G66 Overvoltage tolerant bilateral switch 10.1 Test circuits VCC VIL nE nZ GND nY VIH IS VO VCC nE nZ GND nY IS VI VI VO 001aag488 001aag489 VI = GND and VO = GND or 5.5 V. VI = 5.5 V or GND and VO = open circuit. Fig 6. Test circuit for measuring OFF-state leakage current Fig 7. Test circuit for measuring ON-state leakage current 10.2 ON resistance Table 8. Resistance RON At recommended operating conditions; voltages are referenced to GND (ground 0 V); for graphs see Figure 9 and Figure 10. Symbol RON(peak) Parameter ON resistance (peak) Conditions VSW = GND to VCC; VI = VIH; see Figure 8 ISW = 8 mA; VCC = 2.3 V to 2.7 V ISW = 12 mA; VCC = 2.7 V ISW = 24 mA; VCC = 3.0 V to 3.6 V ISW = 32 mA; VCC = 4.5 V to 5.5 V RON(rail) ON resistance (rail) VSW = GND; VI = VIH; see Figure 8 ISW = 8 mA; VCC = 2.3 V to 2.7 V ISW = 12 mA; VCC = 2.7 V ISW = 24 mA; VCC = 3.0 V to 3.6 V ISW = 32 mA; VCC = 4.5 V to 5.5 V VSW = VCC; VI = VIH ISW = 8 mA; VCC = 2.3 V to 2.7 V ISW = 12 mA; VCC = 2.7 V ISW = 24 mA; VCC = 3.0 V to 3.6 V ISW = 32 mA; VCC = 4.5 V to 5.5 V RON(flat) ON resistance (flatness) VSW = GND to VCC; VI = VIH ISW = 8 mA; VCC = 2.5 V ISW = 12 mA; VCC = 2.7 V ISW = 24 mA; VCC = 3.3 V ISW = 32 mA; VCC = 5.0 V [1] [2] All typical values are measured at Tamb = 25 C and nominal VCC. Flatness is defined as the difference between the maximum and minimum value of ON resistance measured at identical VCC and temperature. [2] -40 C to +85 C Min Typ[1] Max -40 C to +125 C Unit Min Max - 13 10 8.3 7.4 8.5 8.0 7.5 7.3 8.5 7.2 6.5 5.7 17 10 5 3 30 25 20 15 20 18 15 10 20 18 15 10 - - 30 25 20 15 20 18 15 10 20 18 15 10 - 74LVCV2G66 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 3 -- 16 June 2010 6 of 23 NXP Semiconductors 74LVCV2G66 Overvoltage tolerant bilateral switch 10.3 ON resistance test circuit and graphs 001aaa536 16 RON () 12 VSW VCC VIH nE nY GND nZ 4 8 VCC = 2.5 V 2.7 V 3.3 V 5.0 V VI ISW 0 0 001aag490 2 4 VI (V) 6 VI = GND to 5.5 V; RON = VSW / ISW. VI = GND to 5.5 V; Tamb = 25 C. Fig 8. Test circuit for measuring ON resistance Fig 9. Typical ON resistance as a function of input voltage 74LVCV2G66 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 3 -- 16 June 2010 7 of 23 NXP Semiconductors 74LVCV2G66 Overvoltage tolerant bilateral switch 16 RON () 12 Tamb = +85 C +25 C -40 C +125 C 001aaa537 16 RON () 12 001aaa538 Tamb = +85 C +25 C -40 C +125 C 8 8 4 4 0 0 2 4 VI (V) 6 0 0 2 4 VI (V) 6 a. VCC = 2.5 V 16 RON () 12 Tamb = +85 C +25 C -40 C +125 C 001aaa539 b. VCC = 2.7 V 16 RON () 12 Tamb = +85 C +25 C -40 C +125 C 001aaa540 8 8 4 4 0 0 2 4 VI (V) 6 0 0 2 4 VI (V) 6 c. VCC = 3.3 V d. VCC = 5.0 V Fig 10. ON resistance as a function of input voltage at various supply voltages 74LVCV2G66 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 3 -- 16 June 2010 8 of 23 NXP Semiconductors 74LVCV2G66 Overvoltage tolerant bilateral switch 11. Dynamic characteristics Table 9. Dynamic characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for test circuit see Figure 13. Symbol Parameter tpd Conditions [2][3] -40 C to +85 C Min Typ[1] Max -40 C to +125 C Unit Min Max propagation delay nY to nZ or nZ to nY; see Figure 11 VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V [4] 0.4 0.4 0.3 0.2 1.2 1.0 0.8 0.6 - 2.0 1.5 1.5 1.0 ns ns ns ns ten enable time nE to nY or nZ; see Figure 12 VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V 1.0 1.0 1.0 1.0 [5] 4.7 4.4 3.8 2.7 12 8.5 7.5 5.0 1.0 1.0 1.0 1.0 15 11 9.5 6.5 ns ns ns ns tdis disable time nE to nY or nZ; see Figure 12 VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V 1.0 1.0 1.0 1.0 [6] 6.0 7.9 6.5 4.4 16 15 13.5 9.0 1.0 1.0 1.0 1.0 20 19 17 11.5 ns ns ns ns CPD power dissipation capacitance CL = 50 pF; fi = 10 MHz; VI = GND to 5.5 V VCC = 2.5 V VCC = 3.3 V VCC = 5.0 V - 9.7 10.3 11.3 - - - pF pF pF [1] [2] [3] [4] [5] [6] Typical values are measured at Tamb = 25 C and nominal VCC. tpd is the same as tPLH and tPHL. Propagation delay is the calculated RC time constant of the typical ON resistance of the switch and the specified capacitance when driven by an ideal voltage source (zero output impedance). ten is the same as tPZH and tPZL. tdis is the same as tPLZ and tPHZ. CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD x VCC2 x fi x N + {(CL + CS(ON)) x VCC2 x fo} where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; CS(ON) = maximum ON-state switch capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; {(CL + CS(ON)) x VCC2 x fo} = sum of the outputs. 74LVCV2G66 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 3 -- 16 June 2010 9 of 23 NXP Semiconductors 74LVCV2G66 Overvoltage tolerant bilateral switch 11.1 Waveforms and test circuit VI nY or nZ input GND t PLH VOH nZ or nY output VOL 001aaa541 VM VM t PHL VM VM Measurement points are given in Table 10. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. Fig 11. Input (nY or nZ) to output (nZ or nY) propagation delays VI nE input GND t PLZ VCC nY or nZ output LOW-to-OFF OFF-to-LOW VOL t PHZ output HIGH-to-OFF OFF-to-HIGH VOH VY VM GND switch enabled switch disabled switch enabled 001aaa542 VM t PZL VM VX t PZH nY or nZ Measurement points are given in Table 10. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. Fig 12. Enable and disable times Table 10. VCC 2.3 V to 2.7 V 2.7 V 3.0 V to 3.6 V 4.5 V to 5.5 V Measurement points Input VM 0.5VCC 1.5 V 1.5 V 0.5VCC Output VM 0.5VCC 1.5 V 1.5 V 0.5VCC VX VOL + 0.1VCC VOL + 0.3 V VOL + 0.3 V VOL + 0.3 V VY VOH - 0.1VCC VOH - 0.3 V VOH - 0.3 V VOH - 0.3 V Supply voltage 74LVCV2G66 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 3 -- 16 June 2010 10 of 23 NXP Semiconductors 74LVCV2G66 Overvoltage tolerant bilateral switch VEXT VCC VI VO DUT RT CL RL RL G mna616 Test data is given in Table 11. Definitions test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including jig and probe capacitance. RL = Load resistance. VEXT = External voltage for measuring switching times. Fig 13. Load circuit for measuring switching times Table 11. VCC 2.3 V to 2.7 V 2.7 V 3.0 V to 3.6 V 4.5 V to 5.5 V Test data Input VI VCC 2.7 V 2.7 V VCC tr, tf 2.0 ns 2.5 ns 2.5 ns 2.5 ns Load CL 30 pF 50 pF 50 pF 50 pF RL 500 500 500 500 VEXT tPLH, tPHL open open open open tPZH, tPHZ GND GND GND GND tPZL, tPLZ 2VCC 6.0 V 6.0 V 2VCC Supply voltage 11.2 Additional dynamic characteristics Table 12. Additional dynamic characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V); Tamb = 25 C. Symbol THD Parameter total harmonic distortion Conditions fi = 1 kHz; RL = 10 k; CL = 50 pF; see Figure 14 VCC = 2.3 V VCC = 3.0 V VCC = 4.5 V fi = 10 kHz; RL = 10 k; CL = 50 pF; see Figure 14 VCC = 2.3 V VCC = 3.0 V VCC = 4.5 V 0.11 0.07 0.01 % % % 0.42 0.36 0.47 % % % Min Typ Max Unit 74LVCV2G66 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 3 -- 16 June 2010 11 of 23 NXP Semiconductors 74LVCV2G66 Overvoltage tolerant bilateral switch Table 12. Additional dynamic characteristics ...continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V); Tamb = 25 C. Symbol f(-3dB) Parameter -3 dB frequency response Conditions RL = 600 ; CL = 50 pF; see Figure 15 VCC = 2.3 V VCC = 3.0 V VCC = 4.5 V RL = 50 ; CL = 5 pF; see Figure 15 VCC = 2.3 V VCC = 3.0 V VCC = 4.5 V iso isolation (OFF-state) RL = 600 ; CL = 50 pF; fi = 1 MHz; see Figure 16 VCC = 2.3 V VCC = 3.0 V VCC = 4.5 V RL = 50 ; CL = 5 pF; fi = 1 MHz; see Figure 16 VCC = 2.3 V VCC = 3.0 V VCC = 4.5 V Vct crosstalk voltage between digital inputs and switch; RL = 600 ; CL = 50 pF; fi = 1 MHz; tr = tf = 2 ns; see Figure 17 VCC = 2.3 V VCC = 3.0 V VCC = 4.5 V Xtalk crosstalk between switches; RL = 600 ; CL = 50 pF; fi = 1 MHz; see Figure 18 VCC = 2.3 V VCC = 3.0 V VCC = 4.5 V between switches; RL = 50 ; CL = 5 pF; fi = 1 MHz; see Figure 18 VCC = 2.3 V VCC = 3.0 V VCC = 4.5 V Qinj charge injection CL = 0.1 nF; Vgen = 0 V; Rgen = 0 ; fi = 1 MHz; RL = 1 M; see Figure 19 VCC = 2.5 V VCC = 3.3 V VCC = 4.5 V VCC = 5.5 V < 0.003 0.003 0.0035 0.0035 pC pC pC pC -29 -28 -28 dB dB dB -56 -55 -55 dB dB dB 91 119 205 mV mV mV -37 -36 -36 dB dB dB -65 -65 -62 dB dB dB 180 180 180 MHz MHz MHz 160 200 210 MHz MHz MHz Min Typ Max Unit 74LVCV2G66 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 3 -- 16 June 2010 12 of 23 NXP Semiconductors 74LVCV2G66 Overvoltage tolerant bilateral switch 11.3 Test circuits VCC VIH nE nY/nZ nZ/nY 0.5VCC RL 10 F VO CL fi 600 D 001aag492 Test conditions: VCC = 2.3 V: Vi = 2 V (p-p). VCC = 3 V: Vi = 2.5 V (p-p). VCC = 4.5 V: Vi = 4 V (p-p). Fig 14. Test circuit for measuring total harmonic distortion VCC VIH 0.1 F 0.5VCC RL nE nY/nZ nZ/nY VO CL fi 50 dB 001aag491 Adjust fi voltage to obtain 0 dBm level at output. Increase fi frequency until dB meter reads -3 dB. Fig 15. Test circuit for measuring the frequency response when switch is in ON-state 0.5VCC RL VIL 0.1 F VCC nE nZ/nY 0.5VCC RL nY/nZ VO CL dB fi 50 001aag493 Adjust fi voltage to obtain 0 dBm level at input. Fig 16. Test circuit for measuring isolation (OFF-state) 74LVCV2G66 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 3 -- 16 June 2010 13 of 23 NXP Semiconductors 74LVCV2G66 Overvoltage tolerant bilateral switch VCC nE nY/nZ G logic input nZ/nY VO RL CL 50 600 0.5VCC 0.5VCC 001aag494 Fig 17. Test circuit for measuring crosstalk voltage (between digital inputs and switch) 0.5VCC VIH 0.1 F Ri 600 fi 50 1E 1Y or 1Z CHANNEL ON 1Z or 1Y RL CL 50 pF VO1 0.5VCC VIL 2E 2Y or 2Z Ri 600 RL 2Z or 2Y CHANNEL OFF CL 50 pF VO2 001aag496 20 log10 (VO2 / VO1) or 20 log10 (VO1 / VO2). Fig 18. Test circuit for measuring crosstalk between switches 74LVCV2G66 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 3 -- 16 June 2010 14 of 23 NXP Semiconductors 74LVCV2G66 Overvoltage tolerant bilateral switch VCC nE Rgen nY/nZ nZ/nY RL 1 M CL 0.1 nF VO G logic input Vgen 001aag495 a. Test circuit logic input (nE) off on off VO VO mna675 b. Input and output pulse definitions Qinj = VO x CL. VO = output voltage variation. Rgen = generator resistance. Vgen = generator voltage. Fig 19. Test circuit for measuring charge injection 74LVCV2G66 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 3 -- 16 June 2010 15 of 23 NXP Semiconductors 74LVCV2G66 Overvoltage tolerant bilateral switch 12. Application information Use the 74LVCV2G66 to reduce component count and footprint in low-power portable applications. Typical `66' devices do not have low-power enable inputs causing a high ICC. To reduce power consumption in portable (battery) applications, a current limiting resistor is used. (see Figure 20a). The low-power enable inputs of the 74LVCV2G66 have much lower ICC, eliminating the necessity of the current limiting resistor (see Figure 20b). 5V 1 M VCC 3V nE 3V nZ nE 5V VCC nY nY nZ '66' device 74LVCV2G66 (a) (b) 001aaa550 Fig 20. Application example 74LVCV2G66 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 3 -- 16 June 2010 16 of 23 NXP Semiconductors 74LVCV2G66 Overvoltage tolerant bilateral switch 13. Package outline TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm SOT505-2 D E A X c y HE vMA Z 8 5 A pin 1 index A2 A1 (A3) Lp L 1 e bp 4 wM detail X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT505-2 REFERENCES IEC JEDEC --JEITA EUROPEAN PROJECTION ISSUE DATE 02-01-16 A max. 1.1 A1 0.15 0.00 A2 0.95 0.75 A3 0.25 bp 0.38 0.22 c 0.18 0.08 D(1) 3.1 2.9 E(1) 3.1 2.9 e 0.65 HE 4.1 3.9 L 0.5 Lp 0.47 0.33 v 0.2 w 0.13 y 0.1 Z(1) 0.70 0.35 8 0 Fig 21. Package outline SOT505-2 (TSSOP8) 74LVCV2G66 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 3 -- 16 June 2010 17 of 23 NXP Semiconductors 74LVCV2G66 Overvoltage tolerant bilateral switch VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm SOT765-1 D E A X c y HE vMA Z 8 5 Q A pin 1 index A2 A1 (A3) Lp L 1 e bp 4 wM detail X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1 A1 0.15 0.00 A2 0.85 0.60 A3 0.12 bp 0.27 0.17 c 0.23 0.08 D(1) 2.1 1.9 E(2) 2.4 2.2 e 0.5 HE 3.2 3.0 L 0.4 Lp 0.40 0.15 Q 0.21 0.19 v 0.2 w 0.13 y 0.1 Z(1) 0.4 0.1 8 0 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT765-1 REFERENCES IEC JEDEC MO-187 JEITA EUROPEAN PROJECTION ISSUE DATE 02-06-07 Fig 22. Package outline SOT765-1 (VSSOP8) 74LVCV2G66 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 3 -- 16 June 2010 18 of 23 NXP Semiconductors 74LVCV2G66 Overvoltage tolerant bilateral switch XSON8U: plastic extremely thin small outline package; no leads; 8 terminals; UTLP based; body 3 x 2 x 0.5 mm SOT996-2 D B A E A A1 detail X terminal 1 index area e1 L1 1 e b 4 v w M M CAB C C y1 C y L2 L 8 5 X 0 1 scale 2 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max 0.5 A1 0.05 0.00 b 0.35 0.15 D 2.1 1.9 E 3.1 2.9 e 0.5 e1 1.5 L 0.5 0.3 L1 0.15 0.05 L2 0.6 0.4 v 0.1 w 0.05 y 0.05 y1 0.1 OUTLINE VERSION SOT996-2 REFERENCES IEC --JEDEC JEITA --- EUROPEAN PROJECTION ISSUE DATE 07-12-18 07-12-21 Fig 23. Package outline SOT996-2 (XSON8U) 74LVCV2G66 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 3 -- 16 June 2010 19 of 23 NXP Semiconductors 74LVCV2G66 Overvoltage tolerant bilateral switch 14. Abbreviations Table 13. Acronym CMOS DUT Abbreviations Description Complementary Metal-Oxide Semiconductor Device Under Test 15. Revision history Table 14: Revision history Release date 20100616 Data sheet status Product data sheet Product data sheet Change notice Supersedes 74LVCV2G66_2 74LVCV2G66_1 Document ID 74LVCV2G66 v.3 Modifications: 74LVCV2G66_2 Modifications: * * * * Conditions for ICC and ICC corrected. The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Added type number 74LVCV2G66GD (XSON8U package). Product data sheet - 20080703 74LVCV2G66_1 20040402 74LVCV2G66 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 3 -- 16 June 2010 20 of 23 NXP Semiconductors 74LVCV2G66 Overvoltage tolerant bilateral switch 16. Legal information 16.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 16.2 Definitions Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification -- The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer's sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer's applications and products planned, as well as for the planned application and use of customer's third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer's applications or products, or the application or use by customer's third party customer(s). Customer is responsible for doing all necessary testing for the customer's applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer's third party customer(s). NXP does not accept any liability in this respect. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer's general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 16.3 Disclaimers Limited warranty and liability -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors' aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use in automotive applications -- This NXP Semiconductors product has been qualified for use in automotive applications. The product is not designed, authorized or warranted to be 74LVCV2G66 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 3 -- 16 June 2010 21 of 23 NXP Semiconductors 74LVCV2G66 Overvoltage tolerant bilateral switch Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com 74LVCV2G66 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 3 -- 16 June 2010 22 of 23 NXP Semiconductors 74LVCV2G66 Overvoltage tolerant bilateral switch 18. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 10.1 10.2 10.3 11 11.1 11.2 11.3 12 13 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ON resistance . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ON resistance test circuit and graphs. . . . . . . . 7 Dynamic characteristics . . . . . . . . . . . . . . . . . . 9 Waveforms and test circuit . . . . . . . . . . . . . . . 10 Additional dynamic characteristics . . . . . . . . . 11 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Application information. . . . . . . . . . . . . . . . . . 16 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 17 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 20 Legal information. . . . . . . . . . . . . . . . . . . . . . . 21 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 21 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Contact information. . . . . . . . . . . . . . . . . . . . . 22 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'. (c) NXP B.V. 2010. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 16 June 2010 Document identifier: 74LVCV2G66 |
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