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INTEGRATED CIRCUITS
DATA SHEET
SAA4955TJ 2.9-Mbit field memory
Product specification Supersedes data of 1997 Sep 25 File under Integrated Circuits, IC02 1999 Apr 29
Philips Semiconductors
Product specification
2.9-Mbit field memory
FEATURES * 2949264-bit field memory * 245772 x 12-bit organization * 3.3 V power supply * Inputs fully TTL compatible when using an extra 5 V power supply * High speed read and write operations * FIFO operations: - full word continuous read and write - independent read and write pointers (asynchronous read and write access) - resettable read and write pointers * Optional random access by block function (40 words per block) enabled during pointer reset operation * Quasi static (internal self-refresh and clocking pauses of infinite length) * Write mask function * Cascade operation possible * 16 Mbit CMOS DRAM process technology * 40-pin SOJ Package. GENERAL DESCRIPTION The SAA4955TJ is a 2949264-bit field memory designed for advanced TV applications such as 100/120 Hz TV, QUICK REFERENCE DATA SYMBOL Tcy(SWCK) Tcy(SRCK) tACC VDD(P) IDD(tot) PARAMETER WRITE cycle time (SWCK) READ cycle time (SRCK) READ access time after SRCK supply voltage (pins 20 and 21) total supply current (IDD(tot) = IDD + IDD(O) + IDD(P)) minimum read/write cycle; outputs open CONDITIONS see Fig.3 see Fig.10 see Fig.10 MIN. 26 26 - 3.0 3.0 -
SAA4955TJ
PALplus, PIP and 3D comb filter. The maximum storage depth is 245772 words x 12 bits. A FIFO operation with full word continuous read and write could be used as a data delay, for example. A FIFO operation with asynchronous read and write could be used as a data rate multiplier. Here the data is written once, then read as many times as required without being overwritten by new data. In addition to the FIFO operations, a random block access mode is accessible during the pointer reset operation. When this mode is enabled, reading and/or writing may begin at, or proceed from, the start address of any of the 6144 blocks. Each block is 40 words in length. Two or more SAA4955TJs can be cascaded to provide greater storage depth or a longer delay, without the need for additional circuitry. The SAA4955TJ contains separate 12-bit wide serial ports for reading and writing. The ports are controlled and clocked separately, so asynchronous read and write operations are supported. Independent read and write clock rates are possible. Addressing is controlled by read and write address pointers. Before a controlled write operation can begin, the write pointer must be set to zero or to the beginning of a valid address block. Likewise, the read pointer must be set to zero or to the beginning of a valid address block before a controlled read operation can begin.
TYP. - - - 3.3 3.3 22
MAX. - - 21 3.6 5.5 70
UNIT ns ns ns V V mA
VDD, VDD(O) supply voltage (pins 19 and 22)
ORDERING INFORMATION TYPE NUMBER SAA4955TJ PACKAGE NAME SOJ40 DESCRIPTION plastic small outline package; 40 leads (J-bent); body width 10.16 mm VERSION SOT449-1
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Philips Semiconductors
Product specification
2.9-Mbit field memory
BLOCK DIAGRAM
SAA4955TJ
handbook, full pagewidth
D0 to D11 12 14 to 3
IE 18
WE 17
RSTW 16
SWCK 15 3 SERIAL WRITE CONTROLLER write control write acknowledge load write block address IE internal
DATA INPUT AND WRITE MASK BUFFER (x13) IE internal D0 internal 19 20 21 22
INPUT BUFFER (x3)
mini cache write control + cache transfer 12 + 1 SERIAL WRITE REGISTER 20-WORD (x13) 20 x (12 + 1) PARALLEL WRITE REGISTER 20-WORD (x13) 20 x (12 + 1)
+3.3 V VDD VDD(P) VDD(P) VDD(O)
CLOCK OSCILLATOR refresh clock D0 internal IE internal
WRITE MINI CACHE 12-WORD (x12) 100 nF 12 cache transfer MEMORY ARRAY 245760-WORD (x12)
WRITE ADDRESS COUNTER MEMORY ARBITRATION REFRESH ADDRESS COUNTER LOGIC READ ADDRESS COUNTER
READ MINI CACHE 12-WORD (x12)
GNDP GND GNDO GNDP
1 2 39 40 12
20 x 12 PARALLEL READ REGISTER 20-WORD (x12) 20 x 12 SERIAL READ REGISTER 20-WORD (x12) mini cache read control OE internal INPUT BUFFER (x4) 23 24 25 26
MGK676
OE internal
SAA4955TJ
12 DATA MUX DATA OUTPUT BUFFER (x12) 27 to 38 12
read control 3
read acknowledge
load read block address
SERIAL READ CONTROLLER
RE Q0 to Q11 OE
SRCK RSTR
Pins 20 and 21 (VDD(P)) should be connected to the supply voltage of the driving circuit that generates the input voltages. This could be, for instance, 5.5 V instead of 3.3 V. Pins 19 and 22 (VDD and VDD(O)) require a 3.3 V supply.
Fig.1 Block diagram.
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Philips Semiconductors
Product specification
2.9-Mbit field memory
PINNING SYMBOL GNDP GND D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 SWCK RSTW WE IE VDD VDD(P) VDD(P) VDD(O) OE RE RSTR SRCK Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 GNDO GNDP 1999 Apr 29 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 I/O ground ground digital input digital input digital input digital input digital input digital input digital input digital input digital input digital input digital input digital input digital input digital input digital input digital input supply supply supply supply digital input digital input digital input digital input digital output digital output digital output digital output digital output digital output digital output digital output digital output digital output digital output digital output ground ground ground for protection circuits general purpose ground data input 11 data input 10 data input 9 data input 8 data input 7 data input 6 data input 5 data input 4 data input 3 data input 2 data input 1 data input 0 serial write clock write reset clock write enable input enable DESCRIPTION
SAA4955TJ
+3.3 V general purpose supply voltage (see figure note in Fig.1) +3.3 to 5.5 V supply voltage for protection circuits (see figure note in Fig.1) +3.3 to 5.5 V supply voltage for protection circuits +3.3 V supply voltage for output circuits output enable read enable reset read serial read clock data output 0 data output 1 data output 2 data output 3 data output 4 data output 5 data output 6 data output 7 data output 8 data output 9 data output 10 data output 11 ground for output circuits ground for protection circuits 4
Philips Semiconductors
Product specification
2.9-Mbit field memory
SAA4955TJ
handbook, halfpage
GNDP GND D11 D10 D9 D8 D7 D6 D5
1 2 3 4 5 6 7 8 9
40 GNDP 39 GNDO 38 Q11 37 Q10 36 Q9 35 Q8 34 Q7 33 Q6 32 Q5 31 Q4
D4 10
SAA4955TJ
D3 11 D2 12 D1 13 D0 14 SWCK 15 RSTW 16 WE 17 IE 18 VDD 19 VDD(P) 20
MGK675
30 Q3 29 Q2 28 Q1 27 Q0 26 SRCK 25 RSTR 24 RE 23 OE 22 VDD(O) 21 VDD(P)
Fig.2 Pin configuration.
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Philips Semiconductors
Product specification
2.9-Mbit field memory
FUNCTIONAL DESCRIPTION Write operation Write operations are controlled by the SWCK, RSTW, WE and IE signals. A write operation starts with a reset write address pointer (RSTW) operation, followed by a sequence SWCK clock cycles during which time WE and IE must be held HIGH. Write operations between two successive reset write operations must contain at least 40 SWCK write clock cycles while WE is HIGH. To transfer data temporarily stored in the serial write registers to the memory array, a reset write operation is required after the last write operation. RESET WRITE: RSTW The first positive transition of SWCK after RSTW goes from LOW to HIGH resets the write address pointer to the lowest address (-12 decimal), regardless of the state of WE (see Figs 3 and 4). RSTW set-up (tsu(RSTW)) and hold (th(RSTW)) times are referenced to the rising edge of SWCK (see Fig.3). The reset write operation may also be asynchronously related to the SWCK signal if WE is LOW. RSTW needs to stay LOW for a single SWCK cycle before another reset write operation can take place. If RSTW is HIGH for 1024 SWCK write clock cycles while WE is HIGH, the SAA4955TJ will enter a built-in test mode and will not be in regular operation. RANDOM WRITE BLOCK ACCESS MODE The SAA4955TJ will enter random write block access mode if the following signal sequence is applied to control inputs IE and WE during the first four SWCK write clock cycles after a reset write (see Figs 5 and 6): At the 1st and 2nd positive transitions of SWCK, IE must be LOW and WE must be HIGH At the 3rd and 4th positive transitions of SWCK, IE must be HIGH and WE must be LOW At the 5th positive transition of SWCK, the state of WE determines which input pin is used for the block address. If WE is LOW the Most Significant Bit (MSB) of the block address must be applied to the D0 input pin. If WE is HIGH, the Most Significant Bit (MSB) of the block address is applied to pin IE. During the first four clock cycles, control signals WE and IE will function as defined for normal operation. The remaining 12 bits of the 13-bit write block address must be applied, in turn, to the selected input pin (D0 or IE) at the following 12 positive transitions of SWCK. The Least Significant Bit (LSB) of the write block address is applied
SAA4955TJ
at the 17th positive transition of SWCK. A write latency period of 18 additional SWCK clock cycles is required before write access to the new block address is possible. During this time, data is transferred from the serial write and parallel write registers into the memory array and the write pointer is set to the new block address. Block address values between 0 and 6143 are valid. Values outside this range must be avoided because invalid block addresses can result in abnormal operation or a lock-up condition. Recovery from lock-up requires a standard reset write operation. WE must remain LOW from the 3rd positive transition of SWCK to the 17th write latency SWCK clock cycle if the block address is applied to pin D0. If the block address is applied to pin IE, WE must be HIGH on the 5th positive transition of SWCK, may be HIGH or LOW on the 6th transition, and must be LOW from the 7th transition to the 17th write latency SWCK clock cycle. At the 18th write latency SWCK clock cycle, IE and WE may be switched HIGH to prepare for writing new data at the next positive transition of SWCK. The complete write block access entry sequence is finished after the 18th write latency cycle. The LOW-to-HIGH transition on RSTW required at the beginning of the sequence should not be repeated. Additional LOW-to-HIGH transitions on RSTW would disable write block address mode and reset the write pointer. ADDRESS ORGANIZATION Two different types of memory are used in the data address area: a mini cache for the first 12 data words after a reset write or a reset read, and a DRAM cell memory array with a 245760 word capacity. Each word is 12 bits long. The mini cache is needed to store data immediately after a reset operation since a latency period is required before read or write access to the memory array is possible. Latency periods are needed for read or write operations in random read or write block access modes because data is read from, or written to, the memory array. The data in the mini cache can only be accessed directly after a standard reset operation. It cannot be accessed in random read or write block access modes. The address area reserved for the mini cache, accessible after a standard reset operation, is from decimal -12 to -1. The memory array starts at decimal 0 and ends at 245759. Decimal address 0 is identical to block address 0000H. Because a single block address is defined for every 40 words in the memory array, block address 0001H
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Philips Semiconductors
Product specification
2.9-Mbit field memory
corresponds to decimal address 40. The highest block address is 17FFH. This block has a decimal start address of 245720 and an end address 245759. If a read or write reset operation is not performed, the next read or write pointer address after 245759 will be address 0 due to pointer wraparound. Note that reset read and reset write operations should occur in a single sequence. If one pointer wraps around while the other is reset, either 12 words will be lost or 12 words of undefined data will be read. DATA INPUTS: D0 TO D11 AND WRITE CLOCK: SWCK A positive transition on the SWCK write clock latches the data on inputs D0 to D11, provided WE was HIGH at the previous positive transition of SWCK. The data input set-up (tsu(D)) and hold (th(D)) times are referenced to the positive transition of SWCK (see Fig.4). The latched data will only be written into memory if IE was HIGH at the previous positive transition of SWCK. WRITE ENABLE: WE Pin WE is used to enable or disable a data write operation. The WE signal controls data inputs D0 to D11. In addition, the internal write address pointer is incremented if WE is HIGH at the positive transition of the SWCK write clock. WE set-up (tsu(WE)) and hold (th(WE)) times are referenced to the positive edge of SWCK (see Fig.7). INPUT ENABLE: IE Pin IE is used to enable or disable a data write operation from the D0 to D11 data inputs into memory. The latched data will only be written into memory if the IE and WE signals were HIGH during the previous positive transition of SWCK. A LOW level on IE will prevent the data being written into memory and existing data will not be overwritten (write mask function; see Fig.9). The IE set-up (tsu(IE)) and hold (th(IE)) times are referenced to the positive edge of SWCK (see Fig.8). Read operation Read operations are controlled by the SRCK, RSTR, RE and OE signals. A read operation starts with a reset read address pointer (RSTR) operation, followed by a sequence of SRCK clock cycles during which time RE and OE must be held HIGH. Read operations between two successive reset read operations must contain at least 20 SRCK read clock cycles while RE is HIGH. RESET READ: RSTR
SAA4955TJ
The first positive transition of SRCK after RSTR goes from LOW to HIGH resets the read address pointer to the lowest address (-12 decimal; see Figs 10 and 11). If RE is LOW, however, the reset read operation to the lowest address will be delayed until the first positive transition of SRCK after RE goes HIGH. RSTR set-up (tsu(RSTR)) and hold (th(RSTR)) times are referenced to the rising edge of SRCK (see Fig.10). The reset read operation may also be asynchronously related to the SRCK signal if RE is LOW. RSTR needs to stay LOW for a single SRCK cycle before another reset read operation can take place. RANDOM READ BLOCK ACCESS MODE The SAA4955TJ will enter random read block access mode if the following signal sequence is applied to control inputs RE and OE during the first four SRCK read clock cycles after a reset read (see Fig.12): At the 1st and 2nd positive transitions of SRCK, OE must be LOW and RE must be HIGH At the 3rd and 4th positive transitions of SRCK, OE must be HIGH and RE must be LOW. During this time, control signals RE and OE will function as defined for normal operation. The Most Significant Bit (MSB) of the block read address is applied to the OE input pin at the 5th positive transition of SRCK. The remaining 12 bits of the 13-bit read block address must be applied, in turn, to OE at the following 12 positive transitions of SRCK. The Least Significant Bit (LSB) of the block address is applied at the 17th positive transition of SRCK. A read latency period of 20 additional SRCK clock cycles is required before read access to the new block address is possible. During this period, data is transferred from the memory array to the serial read and parallel read registers and the read pointer is set to the new block address. Block address values between 0 and 6143 are valid. Values outside this range must be avoided because invalid block addresses can result in abnormal operation or a lock-up condition. Recovery from lock-up requires a standard reset read operation. The data output pins are not controlled by the OE pin and are forced into high impedance mode from the 3rd to the 17th positive transition of SRCK. OE should be held LOW during the read latency period. RE must remain LOW from the 3rd positive transition of SRCK to the 20th read latency SRCK clock cycle. After the 20th read latency SRCK clock cycle, RE and OE may be switched HIGH to prepare for reading new data
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Philips Semiconductors
Product specification
2.9-Mbit field memory
from the new address block at the next positive transition of SRCK. The complete read block access entry sequence is finished after the 20th read latency cycle. The LOW-to-HIGH transition on RSTR required at the beginning of the sequence should not be repeated. Additional LOW-to-HIGH transitions on RSTR would disable read block address mode and reset the read pointer. DATA OUTPUTS: Q0 TO Q11 AND READ CLOCK: SRCK The new data is shifted out of the data output registers on the rising edge of the SRCK read clock provided RE and OE are HIGH. Data output pins are low impedance if OE is HIGH. If OE is LOW, the data outputs are high impedance and the data output bus may be used by other devices. Data output hold (th(Q)) and access (tACC) times are referenced to the positive transition of SRCK. The output data becomes valid after access time interval tACC (see Fig.11). Data output pins Q0 to Q11 are TTL compatible with the restriction that when the outputs are high impedance, they must not be forced higher than VDD(O) + 0.5 V or 5.0 V absolute. The output data has the same polarity as the incoming data at inputs D0 to D11. READ ENABLE: RE RE is used to increment the read pointer. Therefore, RE needs to be HIGH at the positive transition of SRCK. When RE is LOW, the read pointer is not incremented. RE set-up (tsu(RE)) and hold (th(RE)) times are referenced to the positive edge of SRCK (see Fig.13). OUTPUT ENABLE: OE OE is used to enable or disable data outputs Q0 to Q11. The data outputs are enabled (low impedance) if OE is HIGH. OE LOW disables the data output pins (high impedance). Incrementing of the read pointer does not depend on the status of OE. OE set-up (tsu(OE)) and hold (th(OE)) times are referenced to the positive edge of SRCK (see Fig.14). Power-up and initialization Reliable operation is not guaranteed until at least 100 s after power-up, the time needed to stabilize VDD within the recommended operating range. After the 100 s power-up interval has elapsed, the following initialization sequence must be performed: a minimum of 12 dummy read operations (SRCK cycles) followed by a reset read operation (RSTR), and a minimum of 12 dummy write
SAA4955TJ
operations (SWCK) followed by a reset write operation (RSTW). Read and write initialization may be performed simultaneously. If initialization starts earlier than the recommended 100 s after power-up, the initialization sequence described above must be repeated, starting with an additional reset read operation and an additional reset write operation after the 100 s start-up time. Old and new data access A minimum delay of 40 SWCK clock cycles is needed before newly written data can be read back from memory (see Fig.15). If a reset read operation (RSTR) occurs in a read cycle before a reset write operation (RSTW) in a write cycle accessing the same memory location, then old data will be read. Old data will be read provided a data read cycle begins within 20 pointer positions of the start of a write cycle. This means that if a reset read operation begins within 20 SWCK clock cycles after a reset write operation, the internal buffering of the SAA4955TJ will ensure that old data will be read out (see Fig.16). New data will be read if the read pointer is delayed by 40 pointer positions or more after the write pointer. Old data is still read out if the write pointer is less than or equal to 20 pointer positions ahead of the read pointer (internal buffering). A write pointer to read pointer delay of more than 20 but less than 40 pointer positions should be avoided. In this case, the old or the new data may be read, or a combination of both. In random read and write block access modes, the minimum write-to-read new data delay of 40 SWCK clock cycles must be inserted for each block. Memory arbitration logic and self-refresh Since the data in the memory array is stored in DRAM cells, it needs to be refreshed periodically. Refresh is performed automatically under the control of internal memory arbitration logic which is clocked by a free running clock oscillator. The memory arbitration logic controls memory access for read, write and refresh operations. It uses the contents of the write, read and refresh address counters to access the memory array to load data from the parallel write register, store data in the parallel read register, or to refresh stored data. The values in these counters correspond to block addresses.
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Philips Semiconductors
Product specification
2.9-Mbit field memory
Cascade operation If a longer delay is needed, the total storage depth can be increased beyond 2949264 bits by cascading several SAA4955TJs. For details see the interconnection and timing diagrams (Figs 17 and 18). Test mode operation The SAA4955TJ incorporates a test mode not intended for customer use. If WE and RSTW are held HIGH LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDD(P) VI VO IDD(tot) V IO Ptot Tstg Tj Tamb Ves PARAMETER supply voltage for protection circuits input voltage output voltage total supply current voltage difference between GND, GNDO and GNDP short circuit output current total power dissipation storage temperature junction temperature ambient temperature electrostatic handling note 1 note 2 Notes VDD(P) = 5 V VDD(P) = 5 V CONDITIONS MIN. -0.5 -0.5 -0.5 -0.5 - -0.5 - - -20 0 0 -150 -2000 VDD = VDD(O) = VDD(P) = 3.3 V -0.5 VDD = VDD(O) = VDD(P) = 3.3 V -0.5
SAA4955TJ
continuously for 1024 SWCK clock cycles, the SAA4955TJ will enter test mode. It will exit test mode if WE is LOW for a single SWCK cycle or if RSTW is LOW for 2 SWCK clock cycles.
MAX. +5 +5.5 +5.5 +3.8 +5 +3.8 200 +0.5 50 750 +150 125 70 +200 +2000 V V V V V V
UNIT
VDD, VDD(O) supply voltages
mA V mA mW C C C V V
1. Machine model: equivalent to discharging a 200 pF capacitor through a 0 series resistor (`0 ' is actually 0.75 H + 10 ). 2. Human body model: equivalent to discharging a 100 pF capacitor through a 1500 series resistor. THERMAL CHARACTERISTICS SYMBOL Rth(j-a) PARAMETER thermal resistance from junction to ambient CONDITIONS in free air VALUE 60 UNIT K/W
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Philips Semiconductors
Product specification
2.9-Mbit field memory
SAA4955TJ
CHARACTERISTICS VDD = VDD(O) = VDD(P) = 3.0 to 3.6 V; Tamb = 0 to 70 C; 3 ns input transition times; unless otherwise specified. SYMBOL Supply VDD, VDD(O) supply voltages (pins 19 and 22) VDD(P) IDD(tot) IDD IDDstd supply voltage (pins 20 and 21) total supply current (IDD(tot) = IDD + IDD(O) + IDD(P)) operating supply current stand-by supply current minimum write/read cycle; outputs open after 1 RSTW/RSTR cycle; WE, RE and OE LOW minimum write/read cycle; outputs open 3.0 3.0 - 3.3 3.3 22 20 3 3.6 5.5 70 60 10 V V mA mA mA PARAMETER CONDITIONS MIN. TYP.(1) MAX. UNIT
minimum write/read cycle - -
IDD(O) IDD(P) VIH VIL ILI Ci VOH VOL ILO Co Tcy(SWCK) tW(SWCKH) tW(SWCKL) tsu(D) th(D) tsu(RSTW) th(RSTW) tsu(WE) th(WE) tW(WEL) tsu(IE) th(IE) tW(IEL) tt 1999 Apr 29
supply current supply current
- -
2 0 - - - - - - - - - - - - - - - - - - - - - 3
10 1
mA mA
Inputs (pins 3 to 18 and 23 to 26) HIGH-level input voltage LOW-level input voltage input leakage current input capacitance VI = 0 V to VDD(P) f = 1 MHz; VI = 0 V IOH = -5 mA IOL = 4.2 mA VO = 0 V to VDD(Q); RE and OE LOW f = 1 MHz; VO = 0 V see Fig.3 see Fig.3 see Fig.3 see Fig.3 2.0 -0.5 -10 - VDD(P) + 0.3 V +0.8 +10 7 - 0.4 +10 10 - - - - - - - - - - - - - 30 V A pF
Outputs (pins 27 to 38) HIGH-level output voltage LOW-level output voltage output leakage current output capacitance 2.4 - -10 - V V A pF
Write cycle timing; note 2 SWCK cycle time SWCK HIGH pulse width SWCK LOW pulse width set-up time data inputs (D0 to D11) set-up time RSTW hold time RSTW set-up time WE hold time WE WE LOW pulse width set-up time IE hold time IE IE LOW pulse width transition time (rise and fall) 26 7 7 5 3 5 3 5 3 8 5 3 8 - 10 ns ns ns ns ns ns ns ns ns ns ns ns ns ns
hold time data inputs (D0 to D11) see Fig.3 see Fig.3 see Fig.3 see Fig.7 see Fig.7 see Fig.7 see Fig.8 see Fig.8 see Fig.8 see Fig.3
Philips Semiconductors
Product specification
2.9-Mbit field memory
SAA4955TJ
SYMBOL
PARAMETER
CONDITIONS - - - 3
MIN.
TYP.(1) - - - - - - - - - - - - - - - 3
MAX.
UNIT
Read cycle timing; note 3 tACC ten(Q) tdis(Q) th(Q) Tcy(SRCK) tW(SRCKH) tW(SRCKL) tsu(RSTR) th(RSTR) tsu(RE) th(RE) tW(REL) tsu(OE) th(OE) tW(OEL) tt Notes 1. Typical values are valid for Tamb = 25 C, VDD = VDD(O) = VDD(P) = 3.3 V, all voltages referenced to GND. See Fig.1 for configuration. 2. The write cycle timing set-up and hold times are related to VIL of the rising edge of SWCK. They are valid for the specified LOW- and HIGH-level input voltages (VIL and VIH). 3. The read cycle timing set-up and hold times are related to VIL of the rising edge of SRCK. They are valid for the specified LOW- and HIGH-level input voltages (VIL and VIH). The load on each output is a 30 pF capacitor to ground in parallel with a 218 resistor to 1.31 V. 4. Disable times specified are from the initiating edge until the output is no longer driven by the memory. Disable times are measured by observing the output waveforms. Low values of load resistor and capacitor have to be used to obtain a short time constant. access time after SRCK output enable time after SRCK output disable time after SRCK output hold time after SRCK SRCK cycle time LOW-level pulse width of SRCK set-up time RSTR hold time RSTR set-up time RE hold time RE LOW-level pulse width of RE set-up time OE hold time OE LOW-level pulse width of OE transition time (rise and fall) see Fig.10 see Fig.14 note 4; see Fig.14 see Fig.10 see Fig.10 see Fig.10 see Fig.10 see Fig.10 see Fig.13 see Fig.13 see Fig.13 see Fig.14 see Fig.14 see Fig.14 see Fig.10 21 21 12 - - - - - - - - - - - - 30 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
26 7 7 5 3 5 3 9 5 3 9 -
HIGH-level pulse width of SRCK see Fig.10
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Philips Semiconductors
Product specification
2.9-Mbit field memory
SAA4955TJ
N handbook, full pagewidth - 2 Tcy(SWCK) SWCK
N-1
N
1
2 -VIH -VIL
th(RSTW) tw(SWCKH) tw(SWCKL) th(RSTW) RSTW tsu(D) tsu(RSTW)
tt tsu(RSTW) -VIH -VIL
th(D) D0 to D11 N-2 N-1 N 1 2 -VIH -VIL -VIH -VIL -VIH -VIL
MGK677
WE
IE
Fig.3 Write cycle timing diagram (reset write).
handbook, full pagewidth - 1 N
N Tcy(SWCK)
disable
disable
1 -VIH -VIL
SWCK
tw(SWCKH) RSTW
tw(SWCKL)
-VIH -VIL
D0 to D11
N-1
N
1
-VIH -VIL -VIH -VIL -VIH -VIL
WE
IE
MGK678
Fig.4 Write cycle timing diagram (reset write with WE LOW).
1999 Apr 29
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Philips Semiconductors
Product specification
2.9-Mbit field memory
SAA4955TJ
handbook, full pagewidth
start sequence (4 SWCK) 2 3 4 5
serial input of write block address (13 SWCK) 17
write latency (minimum 18 SWCK) 18 19 34 35 36
write data
1 SWCK
RSTW WE LOW: D0 controlled WE
IE
random write block address D0
MSB LSB
write data 0 at block address: write data 1 2 3
D1 to D11
0
1
2
3
MGK679
Fig.5 D0 controlled entry sequence of random write block access mode.
handbook, full pagewidth
start sequence (4 SWCK) 2 3 4 5
serial input of write block address (13 SWCK) 17
write latency (minimum 18 SWCK) 18 19 34 35 36
write data
1 SWCK
RSTW WE HIGH: IE controlled
WE
random write block address IE
MSB LSB
at block address: write data D0 to D11 0 1 2 3
MGK680
Fig.6 IE controlled entry sequence of random write block access mode.
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Philips Semiconductors
Product specification
2.9-Mbit field memory
SAA4955TJ
N handbook, full pagewidth - 1 SWCK
N
disable
disable
N+1 -VIH -VIL
tsu(WE)
th(WE) tsu(WE)
th(WE)
WE tw(WEL) tsu(D) N-1 th(D) N N+1
-VIH -VIL
D0 to D11
-VIH -VIL -VIH -VIL -VIH -VIL
IE
RSTW
MGK681
Fig.7 Write cycle timing diagram (write enable).
N handbook, full pagewidth- 1 SWCK
N
disable
disable
N+3 -VIH -VIL
tsu(IE)
th(IE) tsu(IE)
th(IE)
IE tw(IEL) tsu(D) N-1 th(D) N N+3
-VIH -VIL
D0 to D11
-VIH -VIL -VIH -VIL -VIH -VIL
WE
RSTW
MGK682
Fig.8 Write cycle timing diagram (input enable = write mask operation).
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Philips Semiconductors
Product specification
2.9-Mbit field memory
SAA4955TJ
handbook, full pagewidth
N
N+1
N+2
N+3
N+4
N+5
N+6
N+7 -VIH -VIL
SWCK
IE
-VIH -VIL
WE
-VIH -VIL
D0 to D11
N
N+1
N+2
N+3
N+6
N+7
-VIH N+8 -VIL
RSTW
-VIH -VIL N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 -VIH -VIL
SRCK
OE
-VIH -VIL
RE
-VIH -VIL new new high-Z N N+3 old N+4 old N+5 new N+6 new N+7 new N+8 -VIH -VIL
Q0 to Q11
RSTR
MGK683
-VIH -VIL
Fig.9 Write mask operation.
1999 Apr 29
15
Philips Semiconductors
Product specification
2.9-Mbit field memory
SAA4955TJ
N handbook, full pagewidth- 1 Tcy(SRCK) SRCK
N
1
2
3 -VIH -VIL
tw(SRCKH) tw(SRCKL) RSTR th(RSTR)
th(RSTR) tsu(RSTR)
tt tsu(RSTR) -VIH -VIL
tACC Q0 to Q11 N-2
th(Q) N-1 N 1 2 -VIH -VIL -VIH -VIL -VIH -VIL
MGK684
RE
OE
Fig.10 Read cycle timing diagram (reset read).
handbook, full pagewidthN
N Tcy(SRCK)
N
1
2 -VIH -VIL
SRCK
tw(SRCKH) tw(SRCKL) RSTR -VIH -VIL tACC Q0 to Q11 N-1 N tACC 1 -VIH -VIL -VIH -VIL -VIH -VIL
MGK685
RE
OE
Fig.11 Read cycle timing diagram (reset read with RE LOW).
1999 Apr 29
16
Philips Semiconductors
Product specification
2.9-Mbit field memory
SAA4955TJ
handbook, full pagewidth
start sequence (4 SRCK) 2 3 4 5
serial input of read block address (13 SRCK) 17
read latency (minimum 20 SRCK) 18 19 36 37 38
read data
1 SRCK
RSTR
RE
random read block address OE
MSB LSB
at block address: read data Q0 to Q11 high-Z 0 1 2
MGK686
Fig.12 Entry sequence of random read block access mode.
handbook, full pagewidthN
N
N
N+1
N+2 -VIH -VIL
SRCK
tsu(RE)
th(RE) tsu(RE)
th(RE)
RE tw(REL) Q0 to Q11 N-1 N
-VIH -VIL tACC N+1 -VIH -VIL -VIH -VIL -VIH -VIL
MGK687
OE
RSTR
Fig.13 Read cycle timing diagram (read enable).
1999 Apr 29
17
Philips Semiconductors
Product specification
2.9-Mbit field memory
SAA4955TJ
handbook, full pagewidth N
disable
disable
N+3
N+4 -VIH -VIL
SRCK
tsu(OE)
th(OE) tsu(OE)
th(OE)
OE tw(OEL) tdis(Q) N-1 high-Z N
-VIH -VIL tACC ten(Q) N+3 -VIH -VIL -VIH -VIL -VIH -VIL
MGK688
Q0 to Q11
RE
RSTR
Fig.14 Read cycle timing diagram (output enable).
1999 Apr 29
18
Philips Semiconductors
Product specification
2.9-Mbit field memory
SAA4955TJ
handbook, full pagewidth
1
2
3
39
40
41
42 -VIH -VIL
SWCK
RSTW
-VIH -VIL
WE and IE
-VIH -VIL new new 2 new 3 new 39 new 40 new 41 new 42 -VIH -VIL
D0 to D11
1
minimum number of SWCK cycles delay to get new data 1 2 3 -VIH -VIL
SRCK
RSTR
-VIH -VIL
RE and OE
-VIH -VIL new new 2
MGK689
Q1 to Q11
high-Z 1
-VIH -VIL
Fig.15 New data access.
1999 Apr 29
19
Philips Semiconductors
Product specification
2.9-Mbit field memory
SAA4955TJ
handbook, full pagewidth
1
2
3
19
20
21
22 -VIH -VIL
SWCK
RSTW
-VIH -VIL
WE and IE
-VIH -VIL new new 2 new 3 new 19 new 20 new 21 new 22 -VIH -VIL
D0 to D11
1
maximum number of SWCK cycles delay to get old data 1 2 3 -VIH -VIL
SRCK
RSTR
-VIH -VIL
RE and OE
-VIH -VIL old old 2
MGK690
Q1 to Q11
high-Z 1
-VIH -VIL
Fig.16 Old data access.
1999 Apr 29
20
Philips Semiconductors
Product specification
2.9-Mbit field memory
SAA4955TJ
handbook, fullreset pagewidth
signal serial clock
RSTW SWCK D0 to D11 data inputs 12 WE IE
16 15
25 26
RSTR SRCK Q0 to Q11 12
RSTW SWCK D0 to D11
16 15
25 26
RSTR SRCK Q0 to Q11 12 data outputs
SAA4955TJ
14 to 3 27 to 38
SAA4955TJ
14 to 3 27 to 38
17 18
24 23
RE OE
WE IE
17 18
24 23
RE OE
enable signal
MGK691
Fig.17 Cascade operation (signal connections).
handbook, full pagewidth
write new data read 2 times delayed old data
1
1 2
2 3
3 4
4 5
5 6
6 7 -VIH -VIL
SWCK and SRCK
RSTW and RSTR
-VIH -VIL
WE and IE and RE and OE
-VIH -VIL new new 2 new 3 new 4 new 5 new 6 -VIH -VIL
data inputs (x12)
1
old data outputs (x12) high-Z 1
old 2
old 3
old 4
old 5
old 6
MGK692
-VIH -VIL
Fig.18 Cascade operation (timing waveforms).
1999 Apr 29
21
Philips Semiconductors
Product specification
2.9-Mbit field memory
PACKAGE OUTLINE SOJ40: plastic small outline package; 40 leads (J-bent); body width 10.16 mm
SAA4955TJ
SOT449-1
X D c
y
eE
bp
b1 40 21 A wM
E
HE A
A2
pin 1 index A1 (A 3) 1 e ZD vM A detail X 20 Lp
0
5 scale
10 mm
DIMENSIONS (millimetre dimensions are derived from the original inch dimensions) UNIT mm A max. 3.68 A1 1.40 1.14 A2 2.29 2.18 A3 0.25 bp 0.51 0.38 b1 0.81 0.66 c 0.32 0.18 D(1) 26.2 25.9 E(1) 10.3 10.0 e 1.27 eE 9.4 HE 11.30 11.05 Lp 1.4 1.1 v 0.18 w 0.18 y 0.1 ZD
(1)
1.19 0.73
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT449-1 REFERENCES IEC JEDEC MS027 EIAJ EUROPEAN PROJECTION
ISSUE DATE 97-06-02
1999 Apr 29
22
Philips Semiconductors
Product specification
2.9-Mbit field memory
SOLDERING Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 230 C. Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results:
SAA4955TJ
* Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Manual soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
1999 Apr 29
23
Philips Semiconductors
Product specification
2.9-Mbit field memory
Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE WAVE BGA, SQFP PLCC(3), SO, SOJ not suitable suitable(2) suitable not recommended(3)(4) not recommended(5) suitable suitable suitable suitable suitable HLQFP, HSQFP, HSOP, HTSSOP, SMS not LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes
SAA4955TJ
REFLOW(1)
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
1999 Apr 29
24
Philips Semiconductors
Product specification
2.9-Mbit field memory
NOTES
SAA4955TJ
1999 Apr 29
25
Philips Semiconductors
Product specification
2.9-Mbit field memory
NOTES
SAA4955TJ
1999 Apr 29
26
Philips Semiconductors
Product specification
2.9-Mbit field memory
NOTES
SAA4955TJ
1999 Apr 29
27
Philips Semiconductors - a worldwide company
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For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1999
Internet: http://www.semiconductors.philips.com
SCA63
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
545004/00/02/pp28
Date of release: 1999 Apr 29
Document order number:
9397 750 05285

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