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general description the MAXQ7670A is a highly integrated solution for mea- suring multiple analog signals and outputting the results on a control area network (can) bus. the device oper- ates from a single 5v supply and incorporates a high- performance, 16-bit reduced instruction set computing (risc) core, a sar adc, and a can 2.0b controller, supporting transfer rates up to 1mbps. the 12-bit sar adc includes an amplifier with programmable gains of 1v/v or 16v/v, 8 input channels, and conversion rates up to 125ksps. the eight single-ended adc inputs can be configured as four unipolar or bipolar, fully differential inputs. for single-supply operation, the external 5v sup- ply powers the digital i/os and two separate integrated linear regulators that supply the 2.5v digital core and the 3.3v analog circuitry. each supply rail has a dedicated power-supply supervisor that provides brownout detec- tion and power-on reset (por) functions. the 16-bit risc microcontroller (?) includes 64kb (32k x 16) of non- volatile program/data flash and 2kb (1k x 16) of data ram. other features of the MAXQ7670A include a 4-wire spi interface, a jtag interface for in-system program- ming and debugging, an integrated 15mhz rc oscilla- tor, external crystal oscillator support, a timer/counter with pulse-width modulation (pwm) capability, and seven gpio pins with interrupt and wake-up capability. the system-on-a-chip (soc) MAXQ7670A is a ?- based, smart data acquisition system. as a member of the maxq family of 16-bit, risc ?s, the MAXQ7670A is ideal for low-cost, low-power, embedded-applica- tions such as automotive, industrial controls, and build- ing automation. the flexible, modular architecture used in the maxq ?s allows development of targeted prod- ucts for specific applications with minimal effort. the MAXQ7670A is available in a 40-pin, 5mm x 5mm tqfn package, and is specified to operate over the -40? to +125? automotive temperature range. applications automotive steering angle and torque sensors can-based automotive sensor applications industrial control building automation features high-performance, low-power, 16-bit risc core 0.166mhz to 16mhz operation, approaching 1mips/mhz low power (< 1ma/mips, v dvdd = +2.5v) 16-bit instruction word, 16-bit data bus 33 instructions, most require only one clock cycle 16-level hardware stack 16 x 16-bit, general-purpose working registers three independent data pointers with auto- increment/decrement low-power, divide-by-256, power-management modes (pmm) and stop mode program and data memory 64kb internal nonvolatile program/data flash 2kb internal data ram sar adc 8 single-ended/4 differential channels, 12-bit resolution pga gain = 1v/v or 16v/v 125ksps (75.5ksps with pga gain = 16v/v) timer/digital i/o peripherals can 2.0b controller (15 message centers) serial peripheral interface (spi) jtag interface (extensive debug and emulation support) single 16-bit/dual 8-bit timer/pwm seven general-purpose, digital i/o pins with external interrupt/wake-up features oscillator/clock module internal oscillator supports external crystal (8mhz or 16mhz) integrated 15mhz rc oscillator external clock source operation programmable watchdog timer power-management module power-on reset power-supply supervisor/brownout detection integrated +2.5v and +3.3v linear regulators MAXQ7670A microcontroller with 12-bit adc, pga, 64kb flash, and can interface ________________________________________________________________ maxim integrated products 1 19-4902; rev 0; 6/10 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. typical application circuit and pin configuration appear at end of data sheet. spi is a trademark of motorola, inc. maxq is a registered trademark of maxim integrated products, inc. ordering information part temp range pin-package MAXQ7670Aatl+ -40? to +125? 40 tqfn-ep* MAXQ7670Aatl/v+** -40? to +125? 40 tqfn-ep* /v denotes an automotive qualified part. + denotes a lead(pb)-free/rohs-compliant package. * ep = exposed pad. ** future product?ontact factory for availability. note: some revisions of this device may incorporate deviations from published specifications known as errata. multiple revisions of any device may be simultaneously available through various sales channels. for information about device errata, go to: http://www.maxim-ic.com/errata . datasheet.in
MAXQ7670A microcontroller with 12-bit adc, pga, 64kb flash, and can interface 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v dvddio = +5.0v, v avdd = +3.3v, v dvdd = +2.5v, v refadc = +3.3v, system clock = 16mhz. t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) (note 1) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. dvdd to dgnd ........................................................-0.3v to +3v dvddio to gndio ................................................-0.3v to +5.5v avdd to agnd ........................................................-0.3v to +4v dgnd to gndio. ..................................................-0.3v to +0.3v gndio to agnd. ..................................................-0.3v to +0.3v agnd to dgnd.....................................................-0.3v to +0.3v analog inputs to agnd..........................-0.3v to (v avdd + 0.3v) reset , digital inputs/outputs to gndio ............................................-0.3v to (v dvddio + 0.3v) xin, xout to dgnd ..............................-0.3v to (v dvdd + 0.3v) continuous power dissipation (t a = +70?) 40-pin tqfn (derate 36mw/? above +70?) ..........2857mw continuous current into any pin.......................................?0ma operating temperature range .........................-40? to +125? junction temperature ......................................................+150? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) ................................+300? soldering temperature (reflow) ......................................+260? parameter symbol conditions min typ max units power requirements dvdd regen2 = dvddio, dv dd av dd , dv dd dv ddio 2.25 2.5 2.75 avdd lrapd = 1, av dd dv ddio 3.0 3.3 3.6 supply voltage ranges dvddio 4.5 5.0 5.25 v shutdown (note 2) 3 10 a avdd supply current i avdd all analog functions enabled 6 7 ma adc, 25ksps, 2mhz adcclk 5200 adc, 125ksps, 2mhz adcclk 5600 avdd brownout interrupt monitor 3 analog module incremental subfunction supply current i avdd pga enabled 5500 ? cpu in stop mode, all peripherals disabled 25 200 ? high speed/2mhz mode (note 3) 2.0 2.5 high speed/16mhz mode (note 4) 11.3 low speed/625khz mode (note 5) 0.95 dvdd supply current i dvdd program flash erase or write 14 23 ma dvddio brownout reset monitor 1 hf crystal oscillator 60 digital peripheral incremental subfunction supply current i dvdd internal fixed-frequency oscillator 50 ? all digital i/os static at gndio or dv ddio 220a dvddio supply current i dvddio can transmitting, timer output switching (note 6) 0.2 0.3 ma datasheet.in
MAXQ7670A microcontroller with 12-bit adc, pga, 64kb flash, and can interface _______________________________________________________________________________________ 3 parameter symbol conditions min typ max units memory section flash memory size program or data storage 64 kb flash page size 16-bit word size 256 words flash erase/write endurance program or data (note 7) 10,000 cycles all flash, t a = +25? 100 flash data retention (note 7) all flash, t a = +85? 15 years flash page erase 20 50 flash erase time entire flash mass erase 200 500 ms flash single word programming 20 40 ? flash programming time entire flash programming 0.66 1.31 s ram memory size 2kb utility rom size 16-bit word size 4 kwords analog sense path (includes pga and adc) resolution n adc 12 bits pga gain = 16v/v, bipolar mode, v in = ?00mv, 75.5ksps ? ? integral nonlinearity inl adc pga gain = 1v/v, unipolar mode, v in = +1.0v, 125ksps ? ? lsb 12 differential nonlinearity dnl adc pga gain = 1v/v or 16v/v ?.5 ?.5 lsb 12 input-referred offset error test at t a = +25?, pga gain = 1v/v or 16v/v ? ?0 mv offset-error temperature coefficient pga gain = 16v/v, bipolar mode ? ?/? gain error pga gain = 16v/v, bipolar mode, excludes offset and reference error, test at t a = +25? -2 +2 % gain-error temperature coefficient pga gain = 16v/v, bipolar mode ? ppm/? conversion clock frequency f adcclk f sysclk = 8mhz or 16mhz 0.5 4.0 mhz pga gain = 16v/v, f adcclk = 2mhz 75.5 sample rate f sample pga gain = 1v/v, f adcclk = 2mhz 125 ksps pga gain = 16v/v, 13.5 adcclk cycles at 2mhz 6.75 channel select, track-and- hold acquisition time t acq pga gain = 1v/v, three adcclk cycles at 2mhz 1.5 ? conversion time t conv 13 adcclk cycles at 2mhz 6.5 ? electrical characteristics (continued) (v dvddio = +5.0v, v avdd = +3.3v, v dvdd = +2.5v, v refadc = +3.3v, system clock = 16mhz. t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) (note 1) datasheet.in
MAXQ7670A microcontroller with 12-bit adc, pga, 64kb flash, and can interface 4 _______________________________________________________________________________________ electrical characteristics (continued) (v dvddio = +5.0v, v avdd = +3.3v, v dvdd = +2.5v, v refadc = +3.3v, system clock = 16mhz. t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) (note 1) parameter symbol conditions min typ max units pga gain = 16v/v, 26.5 adcclk cycles at 2mhz 13.25 channel select plus conversion time t acq + t conv pga gain = 1v/v, 16 adcclk cycles at 2mhz 8 ? turn-on time t recov 10 ? aperture delay 60 ns aperture jitter 100 ps p-p at ain0?in7, unipolar mode, pga gain = 1v/v 0v refadc at ain0?in7, unipolar mode, pga gain = 16v/v 0 0.125 at ain0?in7, bipolar mode, pga gain = 1v/v -v refadc /2 +v refadc /2 differential input voltage range at ain0?in7, bipolar mode, pga gain = 16v/v -v refadc /32 +v refadc /32 v absolute input voltage range at ain0?in7 0 v avdd v input leakage current at ain0?in7 ?.1 a at ain0?in7, pga gain = 16v/v 50 input-referred noise at ain0?in7, pga gain = 1v/v 400 ? rms v in = 12mv p-p , pga gain = 16v/v 33 small-signal bandwidth (-3db) v in = 200mv p-p , pga gain = 1v/v 23 mhz v in = 150mv p-p , pga gain =16v/v 33 large-signal bandwidth (-3db) v in = 2.5v p-p , pga gain = 1v/v 19 mhz single-ended, any ain0?in7, pga gain = 16v/v 16 input capacitance (note 8) single-ended, any ain0?in7, pga gain = 1v/v 13 pf input common-mode rejection ratio cmrr ain0?in7, v cm = differential input range 75 db power-supply rejection ratio psrr av dd = 3.0v to 3.6v 90 db external reference inputs refadc input voltage range 1.0 3.3 v avdd v refadc leakage current adc disabled 1 a input capacitance (note 9) 20 pf +3.3v (avdd) linear regulator avdd output voltage lrapd = 0 3.15 3.3 3.45 v no-load quiescent current lrapd = 0, all internal analog peripherals disabled 10 ? datasheet.in
MAXQ7670A electrical characteristics (continued) (v dvddio = +5.0v, v avdd = +3.3v, v dvdd = +2.5v, v refadc = +3.3v, system clock = 16mhz. t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) (note 1) parameter symbol conditions min typ max units output current capability lrapd = 0 50 ma output short-circuit current lrapd = 0, avdd shorted to agnd 100 ma maximum avdd bypass capacitor to agnd lrapd = 0 0.47 ? +2.5v (dvdd) linear regulator dvdd output voltage regen2 = gndio 2.38 2.5 2.62 v no-load quiescent current regen2 = gndio, all internal digital peripherals disabled 15 ? output current capability regen2 = gndio 50 ma output short-circuit current regen2 = gndio, dv dd shorted to dgnd 100 ma maximum dvdd bypass capacitor to dgnd regen2 = gndio 0.47 ? supply-voltage supervisors and brownout detection dvdd reset threshold asserts reset if v dvdd is below this threshold 2.1 2.25 v dvdd interrupt threshold generates an interrupt if v dvdd falls below this threshold 2.25 2.38 v minimum dvdd interrupt and reset threshold difference 0.14 v avdd interrupt threshold generates an interrupt if v avdd falls below this threshold 3.0 3.15 v dvddio interrupt threshold generates an interrupt if v dvddio falls below this threshold 4.5 4.75 v dv dd 1 2.75 av dd 1 3.6 operational range dv ddio 1 5.25 v supervisor hysteresis ?.7 % can interface can baud rate f canclk = 8mhz 1 mbps canclk mean frequency error 8mhz or 16mhz, 50ppm external crystal 60 ppm canclk total frequency error 8mhz or 16mhz, 50ppm external crystal; measured over a 12ms interval; mean plus peak cycle jitter < 0.5 % microcontroller with 12-bit adc, pga, 64kb flash, and can interface _______________________________________________________________________________________ 5 datasheet.in
MAXQ7670A microcontroller with 12-bit adc, pga, 64kb flash, and can interface 6 _______________________________________________________________________________________ electrical characteristics (continued) (v dvddio = +5.0v, v avdd = +3.3v, v dvdd = +2.5v, v refadc = +3.3v, system clock = 16mhz. t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) (note 1) parameter symbol conditions min typ max units high-frequency crystal oscillator using external crystal 8 or 16 16 clock frequency external input (note 10) 0.166 16.67 mhz stability excluding crystal drift 25 ppm startup time f sysclk cycles 65,535 cycles xin input low voltage driven with external clock source 0.3 x v dvdd v xin input high voltage driven with external clock source 0.7 x v dvdd v internal fixed-frequency oscillator frequency f iffclk t a = t min to t max 13.8 15 16.35 mhz tolerance t a = +25? ?.4 % temperature drift t a = t min to t max 5% power-supply rejection t a = +25?, dv dd = 2.25v to 2.75v ?.5 % reset ( reset ) reset internal pullup resistance pulled up to dvddio 55 k ? reset output low voltage reset asserted, no external load 0.4 v reset output high voltage reset deasserted, no external load 0.9 x v dvddio v reset input low voltage driven with external clock source 0.3 x v dvdd v reset input high voltage driven with external clock source 0.7 x v dvddio v digital inputs (p0._, canrxd, miso, mosi, ss , sclk, tck, tdi, tms) input low voltage 0.8 v input high voltage 2.1 v input hysteresis 500 mv input leakage current v in = gndio or v dvddio , pullup disabled -10 ?.01 +10 ? input pullup resistance 55 k ? input pulldown resistance 55 k ? input capacitance 15 pf digital outputs (p0._, cantxd, mosi, sclk, ss , tdo) output low voltage i sink = 0.5ma 0.4 v output high voltage i source = 0.5ma v dvddio - 0.5 v datasheet.in
MAXQ7670A microcontroller with 12-bit adc, pga, 64kb flash, and can interface _______________________________________________________________________________________ 7 electrical characteristics (continued) (v dvddio = +5.0v, v avdd = +3.3v, v dvdd = +2.5v, v refadc = +3.3v, system clock = 16mhz. t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) (note 1) parameter symbol conditions min typ max units output capacitance i/o pins three-state 15 pf pd0._ = 0 880 maximum output impedance pd0._ = 1 450 ? system clock system clock frequency f sysclk from any clock source 0 16.67 mhz spi interface timing spi master operating frequency f mclk 0.5 x f sysclk 8 mhz spi slave mode operating frequency f sclk f sysclk /8 mhz sclk output pulse-width high/low t mch , t mcl t sysclk - 25 ns sclk input pulse-width high/low t sch , t scl t sysclk ns mosi output hold time after sclk sample edge t moh t sysclk - 25 ns mosi output setup time to sclk sample edge t mos t sysclk - 25 ns miso input setup time to sclk sample edge t mis 30 ns miso input hold time after sclk sample edge t mih 0ns sclk inactive to mosi inactive t mlh t sysclk - 25 ns mosi input setup time to sclk sample edge t sis 30 ns mosi input hold time after sclk sample edge t sih t sysclk + 25 ns miso output valid after sclk shift edge transition t sov 3 t sysclk + 25 ns miso output disabled after ss edge rise t slh 2 t sysclk + 50 ns ss falling edge to miso active t soe 2 t sysclk + 2.5 ns datasheet.in
MAXQ7670A microcontroller with 12-bit adc, pga, 64kb flash, and can interface 8 _______________________________________________________________________________________ note 1: all devices are 100% production tested at t a = +25? and +125?. temperature limits to t a = -40? are guaranteed by design. note 2: all analog functions disabled and all digital inputs connected to supply or ground. note 3: high-speed/8 mode without can; v dvdd = +2.5v, cpu and 16-bit timer running at 2mhz from an external, 16mhz crystal oscillator; all other peripherals disabled; all digital i/os static at v dvddio or gndio; t a = t min to t max . note 4: high-speed/1 mode with can; v dvdd = +2.5v, cpu and 16-bit timer running at 16mhz from an external, 16mhz crystal oscillator; can enabled and communicating at 500kbps; all other peripherals disabled, all digital i/os (except cantxd and canrxd) static at v dvddio or gndio, t a = t min to t max . note 5: low speed, pmm1 mode without can; v dvdd = +2.5v, cpu and one timer running from an external, 16mhz crystal oscilla- tor in pmm1 mode; all other peripherals disabled; all digital i/os static at v dvddio or gndio, t a = t min to t max . note 6: can transmitting at 500kbps; 16-bit timer output switching at 500khz; all active i/os are loaded with a 20pf capacitor; all remaining digital i/os are static at v dvddio or gndio, t a = t min to t max . note 7: guaranteed by design and characterization. note 8: this is not a static capacitance. it is the capacitance presented to the analog input when the t/h amplifier is in sample mode. note 9: the switched capacitor on the refadc input can disturb the reference voltage. to reduce this disturbance, place a 0.1? capacitor from refadc to agnd as close as possible to refadc. note 10: the digital design is fully static. however, the lower clock limit is set by a clock detect circuit. the MAXQ7670A switches to the internal rc clock if the external input goes below 166khz. this clock detect circuit also acts to detect a crystal failure when a crystal is used. electrical characteristics (continued) (v dvddio = +5.0v, v avdd = +3.3v, v dvdd = +2.5v, v refadc = +3.3v, system clock = 16mhz. t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) (note 1) parameter symbol conditions min typ max units ss falling edge to first sclk sample edge t sse 2 t sysclk + 5 ns sclk inactive to ss rising edge t sd t sysclk + 10 ns minimum cs pulse width t scw t sysclk + 10 ns datasheet.in
MAXQ7670A microcontroller with 12-bit adc, pga, 64kb flash, and can interface _______________________________________________________________________________________ 9 miso mosi sclk (ckpol/ckpha = 0/1 or 1/0 mode) sclk (ckpol/ckpha = 0/0 or 1/1 mode) sample edge shift edge t mlh t moh t mos t mih t mis t mcl t mch t mch t mclk t mcl high impedance figure 1. spi timing diagram in master mode t slh t sov t soe miso mosi t sis t sch t scl t scl t scw t sse t sch t sclk t sih t sd sample edge high impedance high impedance shift edge sclk (ckpol/ckpha = 0/1 or 1/0 mode) ss sclk (ckpol/ckpha = 0/0 or 1/1 mode) figure 2. spi timing diagram in slave mode datasheet.in
MAXQ7670A microcontroller with 12-bit adc, pga, 64kb flash, and can interface 10 ______________________________________________________________________________________ gpo._ output high voltage vs. source current i oh (ma) v oh (v) MAXQ7670A toc01 0 0.5 1.0 1.5 2.0 2.5 0 1 2 3 4 5 t a = -40 c t a = -40 c t a = +85 c t a = +85 c t a = +25 c t a = +25 c ps0._ = 1 t a = +105 c t a = +105 c ps0._ = 0 gpo._ output low voltage vs. sink current i ol (ma) v ol (v) MAXQ7670A toc02 0 0.5 1.0 1.5 2.0 2.5 0 1 2 3 4 5 t a = -40 c t a = +85 c t a = +25 c t a = +105 c t a = -40 c t a = +85 c t a = +25 c t a = +105 c ps0._ = 1 ps0._ = 0 adc inl vs. code (ref adc = +3.3v, 75ksps, pga gain = 16v/v) digital output code adc inl (lsb) MAXQ7670A toc03 0 1024 2048 3072 4096 -1.0 -0.4 -0.6 -0.8 -0.2 0 0.2 0.4 0.6 0.8 1.0 bipolar mode v in = -100mv to +100mv adc dnl vs. code (refadc = +3.3v, 75ksps, pga gain = 16v/v) digital output code adc dnl (lsb) MAXQ7670A toc04 0 1024 2048 3072 4096 -1.0 -0.4 -0.6 -0.8 -0.2 0 0.2 0.4 0.6 0.8 1.0 bipolar mode v in = -100mv to +100mv adc offset error vs. temperature temperature ( c) offset error (mv) MAXQ7670A toc05 -40 -25 -10 5 20 35 50 65 80 95 110 125 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 bipolar mode pga gain = 16v/v v in-diff = 0 v in-cm = +1.65v adc gain error vs. temperature temperature ( c) gain error (%) MAXQ7670A toc06 -40 -25 -10 5 20 35 50 65 80 95 110 125 -1.0 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 bipolar mode pga gain = 16v/v v in-diff = 200mv v in-cm = +1.65v 10ms/div dvdd, reset power-up characteristics dvddio 2v/div dvdd 1v/div MAXQ7670A toc07 reset 2v/div regen2 = gndio 20ms/div dvdd, reset power-down characteristics dvddio 2v/div dvdd 1v/div MAXQ7670A toc08 reset 2v/div regen2 = gndio maximum dvdd transient duration vs. boi threshold overdrive dv dd boi threshold overdrive (mv) maximum transient duration ( s) MAXQ7670A toc09 0 20 40 60 80 100 120 140 160 180 200 1 10 100 1000 boi asserted above this line typical operating characteristics (v dvddio = 5.0v, v avdd = 3.3v, v dvdd = 2.5v, f sysclk = 16mhz, adc resolution = 12 bits, v refdac = 3.3v, t a = +25?, unless otherwise noted.) datasheet.in
MAXQ7670A microcontroller with 12-bit adc, pga, 64kb flash, and can interface ______________________________________________________________________________________ 11 maximum dvddio transient duration vs. boi threshold overdrive dvddio boi threshold overdrive (mv) maximum transient duration ( s) MAXQ7670A toc10 0 20 40 60 80 100 120 140 160 180 200 1 10 100 1000 boi asserted above this line maximum avdd transient duration vs. boi threshold overdrive avdd boi threshold overdrive (mv) maximum transient duration ( s) MAXQ7670A toc11 0 20 40 60 80 100 120 140 160 180 200 1 10 100 1000 boi asserted above this line avdd linear regulator output voltage vs. dvddio supply voltage dvddio (v) avdd (v) MAXQ7670A toc12 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 lrapd = 0 i out = 10ma avdd linear regulator output voltage vs. temperature temperature ( c) avdd (v) MAXQ7670A toc13 -40 -25 -10 5 20 35 50 65 80 95 110 125 3.20 3.25 3.30 3.35 3.40 lrapd = 0 i out = 10ma avdd linear regulator output voltage vs. load current load current (ma) avdd (v) MAXQ7670A toc14 0 5 10 15 20 25 30 35 40 45 50 3.20 3.25 3.30 3.35 3.40 lrapd = 0 dvdd linear regulator output voltage vs. dvddio supply voltage dvddio (v) dvdd (v) MAXQ7670A toc15 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0 0.5 1.0 1.5 2.0 2.5 3.0 regen2 = dvddio i out = 10ma dvdd linear regulator output voltag e vs. temperature temperature ( c) dvdd (v) MAXQ7670A toc16 -40 -25 -10 5 20 35 50 65 80 95 110 125 2.40 2.45 2.50 2.55 2.60 regen2 = dvddio i out = 10ma dvdd linear regulator output voltage vs. load current load current (ma) dvdd (v) MAXQ7670A toc17 0 5 10 15 20 25 30 35 40 45 50 2.40 2.45 2.50 2.55 2.60 regen2 = dvddio rc oscillator output frequency vs. temperature temperature ( c) frequency (mhz) MAXQ7670A toc18 -40 -25 -10 5 20 35 50 65 80 95 110 125 14.0 14.5 15.0 15.5 16.0 16.5 17.0 typical operating characteristics (continued) (v dvddio = 5.0v, v avdd = 3.3v, v dvdd = 2.5v, f sysclk = 16mhz, adc resolution = 12 bits, v refdac = 3.3v, t a = +25?, unless otherwise noted.) datasheet.in
MAXQ7670A microcontroller with 12-bit adc, pga, 64kb flash, and can interface 12 ______________________________________________________________________________________ rc oscillator output frequency vs. dvdd dvdd (v) frequency (mhz) MAXQ7670A toc19 2.25 2.35 2.45 2.55 2.65 2.75 14.0 14.5 15.0 15.5 16.0 dvdd supply current vs. dvdd supply voltage MAXQ7670A toc020 dvdd supply voltage (v) dvdd supply current (ma) 2.625 2.500 2.375 2 4 6 8 10 12 14 16 18 20 0 2.250 2.750 flash erase note 4 in ec characteristics note 3 in ec characteristics note 5 in ec characteristics dvdd supply current vs. temperature MAXQ7670A toc21 temperature ( c) dvdd supply current (ma) 110 95 65 80 -10 5 20 35 50 -25 2 4 6 8 10 12 14 16 18 20 0 -40 125 flash erase note 3 in ec characteristics note 5 in ec characteristics note 4 in ec characteristics dvdd supply current vs. dvdd supply voltage MAXQ7670A toc22 dvdd supply voltage (v) dvdd supply current ( a) 2.625 2.500 2.375 24.0 24.5 25.0 25.5 26.0 26.5 23.5 2.250 2.750 stop mode dvdd supply current vs. temperature MAXQ7670A toc23 temperature ( c) dvdd supply current ( a) 110 95 80 65 50 35 20 5 -10 -25 23 24 25 26 27 28 22 -40 125 stop mode avdd supply current vs. avdd supply voltage MAXQ7670A toc24 avdd supply voltage (v) avdd supply current (na) 3.45 3.30 3.15 20 40 60 80 100 120 140 0 3.00 3.60 shutdown (note 2) in ec characteristics avdd supply current vs. temperature MAXQ7670A toc25 temperature ( c) avdd supply current (na) 110 95 65 80 -10 5 20 35 50 -25 20 40 60 80 100 120 140 0 -40 125 shutdown (note 2) in ec characteristics avdd supply current vs. avdd supply voltage MAXQ7670A toc26 avdd supply voltage (v) avdd supply current (ma) 3.45 3.30 3.15 5.7 5.8 5.9 6.0 5.6 3.00 3.60 all analog functions enabled avdd supply current vs. temperature MAXQ7670A toc27 temperature ( c) avdd supply current (ma) 110 95 80 65 50 35 20 5 -10 -25 5.4 5.6 5.8 6.0 6.2 5.2 -40 125 all analog functions enabled typical operating characteristics (continued) (v dvddio = 5.0v, v avdd = 3.3v, v dvdd = 2.5v, f sysclk = 16mhz, adc resolution = 12 bits, v refdac = 3.3v, t a = +25?, unless otherwise noted.) datasheet.in
MAXQ7670A microcontroller with 12-bit adc, pga, 64kb flash, and can interface ______________________________________________________________________________________ 13 avdd supply current vs. adc sampling rate MAXQ7670A toc28 adc sampling rate (ksps) avdd supply current (ma) 10 100 5.5 5.6 5.7 5.4 1 1000 pga gain = 16v/v dvddio dynamic supply current vs. dvddio supply voltage MAXQ7670A toc29 dvddio supply voltage (v) dvddio supply current ( a) 2.625 2.500 2.375 120 140 160 180 200 220 240 260 100 2.250 2.750 note 6 in ec characteristics dvddio dynamic supply current vs. temperature MAXQ7670A toc30 temperature ( c) dvddio supply current ( a) 110 95 80 65 50 35 20 5 -10 -25 210 220 230 240 250 200 -40 125 note 6 in ec characteristics dvddio static supply current vs. dvddio supply voltage MAXQ7670A toc31 dvddio supply voltage (v) dvddio supply current ( a) 5.125 5.00 4.875 60 80 100 120 140 160 40 4.750 5.250 dvddio static supply current vs. temperature MAXQ7670A toc32 temperature ( c) dvddio supply current ( a) 110 95 80 65 50 35 20 5 -10 -25 60 80 100 120 140 160 40 -40 125 typical operating characteristics (continued) (v dvddio = 5.0v, v avdd = 3.3v, v dvdd = 2.5v, f sysclk = 16mhz, adc resolution = 12 bits, v refdac = 3.3v, t a = +25?, unless otherwise noted.) dvddio incremental supply current vs. dvddio supply voltage MAXQ7670A toc33 dvddio supply voltage (v) dvddio supply current ( a) 5.125 5.000 4.875 1 2 3 4 5 0 4.750 5.250 boi enabled dvddio incremental supply current vs. temperature MAXQ7670A toc34 temperature ( c) dvddio supply current ( a) 5 -10 -25 50 35 20 110 95 80 65 1 2 3 4 5 0 -40 125 boi enabled adc sampling error vs. input source impedance source impedance ( ? ) sampling error (lsb) MAXQ7670A toc35 -5 -4 -3 -2 -1 0 1 1 10 100 1000 10,000 100,000 pga gain = 16v/v f s = 75ksps snr frequency (khz) magnitude (db) MAXQ7670A toc36 0 5 10 15 20 25 30 35 -140 -120 -100 -80 -60 -40 -20 0 f in = 10khz f s = 62.5ksps datasheet.in
MAXQ7670A microcontroller with 12-bit adc, pga, 64kb flash, and can interface 14 ______________________________________________________________________________________ pin description pin name function 1 ain7 analog input channel 7. ain7 is multiplexed to the pga or adc as single-ended analog input 7 or as a differential input with ain6. as a differential input, the polarity of ain7 is negative. 2 ain6 analog input channel 6. ain6 is multiplexed to the pga or adc as a single-ended analog input 6 or as a differential input with ain7. as a differential input, the polarity of ain6 is positive. 3 ain5 analog input channel 5. ain5 is multiplexed to the pga or adc as single-ended analog input 5 or as a differential input with ain4. as a differential input, the polarity of ain5 is negative. 4 ain4 analog input channel 4. ain4 is multiplexed to the pga or adc as single-ended analog input 4 or as a differential input with ain5. as a differential input, the polarity of ain4 is positive. 5 refadc adc external reference input. connect an external reference between 1v and v avdd . 6 agnd analog ground 7 ain3 analog input channel 3. ain3 is multiplexed to the pga or adc as single-ended analog input 3 or as a differential input with ain2. as a differential input, the polarity of ain3 is negative. 8 ain2 analog input channel 2. ain2 is multiplexed to the pga or adc as single-ended analog input 2 or as a differential input with ain3. as a differential input, the polarity of ain2 is positive. 9 ain1 analog input channel 1. ain1 is multiplexed to the pga or adc as single-ended analog input 1 or as a differential input with ain0. as a differential input, the polarity of ain1 is negative. 10 ain0 analog input channel 0. ain0 is multiplexed to the pga or adc as single-ended analog input 0 or as a differential input with ain1. as a differential input, the polarity of ain0 is positive. 11 i.c. internally connected. connect to gndio for proper operation. 12 p0.0 port 0 bit 0. p0.0 is a general-purpose digital i/o with interrupt/wake-up capability. 13 p0.1 port 0 bit 1. p0.1 is a general-purpose digital i/o with interrupt/wake-up capability. 14 p0.2 port 0 bit 2. p0.2 is a general-purpose digital i/o with interrupt/wake-up capability. 15, 22, 38 gndio digital i/o ground and regulator ground 16 canrxd can bus receiver input. can receiver input. 17 cantxd can bus transmitter output. can transmitter output. 18 ss active-low, spi port slave select input. in spi slave mode, this is the slave select input. in spi master mode, this is an input and connection is optional (connect if mode fault enable is required, refer to the maxq7670 user? guide for a description of the spicn register). in master mode, use an available gpio as a slave selector and pull ss high to dvddio through a pullup resistor. 19 p0.6/t0 port 0 bit 6/timer 0 i/o. p0.6 is a general-purpose digital i/o with interrupt/wake-up input capability. t0 is a primary timer/pwm input or output. the alternative function, t0, is selected using the t2cna0 register. when this function is selected, it overrides the gpio functionality. 20 p0.7/t0b port 0 bit 7/timer 0 output. p0.7 is a general-purpose digital i/o with interrupt/wake-up input capability. t0b is a secondary timer/pwm output. the alternative function, t0b, is selected using the t2cnb0 register. when this function is selected, it overrides the gpio functionality. 21, 39 dvddio digital i/o supply voltage and regulator supply input. dvddio supplies all digital i/o except for xin and xout, and supplies power to the two internal linear regulators, avdd and dvdd. bypass dvddio to gndio with a 0.1? capacitor as close as possible to the device. datasheet.in
MAXQ7670A microcontroller with 12-bit adc, pga, 64kb flash, and can interface ______________________________________________________________________________________ 15 pin description (continued) pin name function 23 sclk spi serial clock. sclk is the spi interface serial clock i/o. in spi master mode, sclk is an output. while in spi slave mode, sclk is an input. 24 mosi spi serial data i/o. mosi is the spi interface serial data output in master mode or serial data input in slave mode. 25 miso spi serial data i/o. miso is the spi interface serial data input in master mode or serial data output in slave mode. 26 regen2 active-low +2.5v linear regulator enable input. connect regen2 to gndio to enable the +2.5v linear regulator. connect to dvddio to disable the +2.5v linear regulator. 27 tdo jtag serial test data output. tdo is the jtag serial test, data output. 28 tms jtag test mode select. tms is the jtag test mode, select input. 29 tdi jtag serial test data input. tdi is the jtag serial test, data input. 30 tck jtag serial test clock input. tck is the jtag serial test, clock input. 31 p0.4/ adccnv port 0 bit 4/adc start conversion control. p0.4 is a general-purpose digital i/o with interrupt/wake-up capability. adccnv is a firmware-configurable, rising or falling edge, start/convert signal used to trigger adc conversions. the alternative function, adccnv, is selected using the register bits acnt[2:0]. when using adccnv as a trigger for adc conversion, set p0.4/adccnv as an input using the pd0 register. this action prevents any unintentional interference in the saradc operation. 32 p0.5 port 0 bit 5. p0.5 is a general-purpose digital i/o with interrupt/wake-up capability. 33 reset reset input/output. active-low input/output with internal 55k ? pullup to dvddio. drive low to reset the MAXQ7670A. the maxq20 ? core holds reset low during por and during dvdd brownout conditions. 34 dgnd digital ground 35 xout high-frequency crystal output. connect an external crystal to xin and xout for normal operation, or leave unconnected if xin is driven with an external clock source. leave unconnected if an external clock source is not used. 36 xin h i g h- fr eq uency c r ystal inp ut. c onnect an exter nal cr ystal or r esonator to x in and x o u t for nor m al op er ati on, or d r i ve x in w i th an exter nal cl ock sour ce. leave unconnected i f an exter nal cl ock sour ce i s not used . 37 dvdd d i g i tal s up p l y v ol tag e. d v d d sup p l i es i nter nal d i g i tal cor e and fl ash m em or y. d v d d i s d i r ectl y connected to the outp ut of the i nter nal + 2.5v l i near r eg ul ator . d i sab l e the i nter nal r eg ul ator ( thr oug h reg en 2 ) to connect an exter nal sup p l y. byp ass d v d d to d g n d w i th a 0.1? cap aci tor as cl ose as p ossi b l e to the d evi ce. 40 avdd analog supply voltage. avdd supplies pga and adc. avdd is directly connected to the output of the internal +3.3v linear regulator. disable the internal regulator (via software) to connect an external supply. bypass avdd to agnd with a 0.1? capacitor as close as possible to the device. ep exposed pad. connect ep to the ground plane. datasheet.in
MAXQ7670A microcontroller with 12-bit adc, pga, 64kb flash, and can interface 16 ______________________________________________________________________________________ refadc 10:1 mux 12-bit adc software- interrupt controller dvddio brownout monitor i/o buffers 6:1 mux ain0 ain1 ain7 ain6 ain1 ain3 ain5 ain7 ain9 agnd adcmx[3:0] hffint eifo spi t0i cansti caneri vibe viobi adcclk adce adcry gndio dvddio p0.7/t0b p0.6/t0 mosi miso serial peripheral interface (spi) port 0 i/o registers 16-bit timer0 t0clk t0i spi watchdog timer iffclk ewt 4k x 16 utility rom 16-bit maxq20 core risc cpu 64kb (32k x 16) program/data flash 2kb (1k x 16) data ram +2.5v linear regaulator dvdd power-on reset monitor hf clock prescaler adc clock prescaler can clock prescaler jtag interface port 0 i/o registers i/o buffers m u x m u x gndio hf xtal osc. iffclk timer clock prescaler hfe ife int fixed freq osc. sysclk sysclk xhfry hffint 2:1 dgnd can 2.0b interface i/o buffers cansti caneri gndio canclk cantxd canrxd gndio dvddio dgnd tck tms tdi tdo regen2 dvdd xout dgnd gndio dgnd gndio xin wdi vdpe dvdd reset dvddio dv dd wtr canclk adcclk t0clk ain2 ain3 ain4 ain5 dgnd gain = 1x, 16x pga pgae pd0 po0 pi0 eif0 hfclk dvddio adcref MAXQ7670A gndio dgnd ss sclk p0.5 p0.4/adccnv p0.2 p0.1 p0.0 avdd brownout monitor vabe vabi agnd adccnv adcby dvdd dvddio dvddio dvddio +3.3v linear regaulator gndio lrapd avdd avdd dvddio block diagram datasheet.in
MAXQ7670A microcontroller with 12-bit adc, pga, 64kb flash, and can interface ______________________________________________________________________________________ 17 detailed description the MAXQ7670A incorporates a 16-bit risc arithmetic logic unit (alu) with a harvard memory architecture that addresses 64kb (32k x 16) of flash and 2048 bytes (1024 x 16) of ram memory. this core combined with digital and analog peripherals provide versatile data-acquisition functions. the peripherals include up to seven digital i/os, a 4-wire spi interface, a can 2.0b bus, a jtag interface, a timer, an integrated rc oscilla- tor, two linear regulators, a watchdog timer, three power-supply supervisors, a 12-bit 125ksps sar adc with programmable-gain amplifier (pga) and eight sin- gle-ended or four differential multiplexed inputs. the power-efficient maxq20 ? core consumes less than 1ma/mips. refer to the maxq7670 user? guide for more detailed information on configuring and program- ming the MAXQ7670A. analog input peripheral the integrated 12-bit adc employs an ultra-low-power sar-based conversion method and operates up to 125ksps with pga = 1v/v (75.5ksps with pga = 16v/v). the integrated 8-channel multiplexer (mux) and pga allow the adc to measure eight single-ended (relative to agnd) or four fully differential analog inputs with software-selectable input ranges through the pga. see figures 3 and 4. 12-bit adc 125ksps data bus 12 pga 1v/v or 16v/v pgg adce 1 0 adcasd adcby actl timer 0 adcdul adcrdy adcbip conversion control adc clock div 8:1 mux adccd 1 0 3 2 adcmx 1 2 0 adcclk source refadc p0.4/adccnv agnd ain4 ain3 ain2 ain7 ain6 ain5 ain1 ain0 MAXQ7670A figure 3. simplified analog input diagram (eight single-ended inputs) datasheet.in
MAXQ7670A microcontroller with 12-bit adc, pga, 64kb flash, and can interface 18 ______________________________________________________________________________________ 12-bit adc 125ksps data bus 12 pgg adce 1 0 adcasd adcby timer 0 adcdul adcrdy adcbip conversion control adc clock div 4:1 mux 4:1 mux adccd 1 0 3 2 adcmx 1 2 0 adcclk source refadc p0.4/adccnv ain1 ain6 ain4 ain7 ain5 ain3 ain2 ain0 pga 1v/v or 16v/v actl MAXQ7670A figure 4. simplified analog input diagram (four fully differential inputs) datasheet.in
MAXQ7670A microcontroller with 12-bit adc, pga, 64kb flash, and can interface ______________________________________________________________________________________ 19 the MAXQ7670A adc uses a fully differential sar con- version technique and an integrated t/h (track and hold) block to convert voltage signals into a 12-bit digi- tal result. both single-ended and differential configura- tions are implemented using an analog input channel multiplexer that supports 8 single-ended or 4 differen- tial channels. in single-ended mode, the mux selects from either of the ground-referenced analog inputs ain0?in7. in dif- ferential input configuration, analog inputs are selected from the following pairs: ain0/ain1, ain2/ain3, ain4/ain5, and ain6/ain7. table 1 shows the single- ended and differential input configurations possible for the adc mux. analog input track and hold a sar conversion in the MAXQ7670A has different t/h cycles depending on whether a gain of 1 (bypass) or a gain of 16 (pga enabled) is selected. gain = 1v/v in gain = 1v/v, the conversion has a two-stage t/h cycle. in track mode, a positive input capacitor con- nects to the signal channel. a negative input capacitor connects to the reference channel. after the t/h enters hold mode, the difference between the signal and the reference channel is converted to a 12-bit value. this two-stage cycle takes 16 sarclks to complete. gain = 16v/v in gain = 16v/v, the conversion has a three-stage t/h cycle: amplification, adc track, and adc hold. first, the pga tracks the selected input and reference sig- nals. the pga amplifies the difference between the two signals and holds the result for the next stage, adc track. the adc tracks and converts the pga result into a 12-bit value. the sar operation itself does not change irrespective of the chosen gain. this three- stage cycle takes 26.5 sarclks to complete. figure 5 shows the conversion timing differences between gain = 1v/v and gain = 16v/v. sar channel select (register acnt[14:11]) signal channel into adc reference channel into adc measurement type 0000 ain0 agnd single-ended measurement on ain0 0001 ain1 agnd single-ended measurement on ain1 0010 ain2 agnd single-ended measurement on ain2 0011 ain3 agnd single-ended measurement on ain3 0100 ain4 agnd single-ended measurement on ain4 0101 ain5 agnd single-ended measurement on ain5 0110 ain6 agnd single-ended measurement on ain6 0111 ain7 agnd single-ended measurement on ain7 1000 reserved 1001 reserved 1010 ain0 ain1 ain0/ain1 1011 ain2 ain3 ain2/ain3 1100 ain4 ain5 ain4/ain5 1101 ain6 ain7 ain6/ain7 1110 reserved 1111 vcim differential zero offset trim table 1. adc mux input configurations datasheet.in
MAXQ7670A microcontroller with 12-bit adc, pga, 64kb flash, and can interface 20 ______________________________________________________________________________________ input impedance the input-capacitance charging rate determines the time required for the t/h to acquire an input signal. the required acquisition time lengthens with the increase of the input signals source resistance. any source below 5k ? does not significantly affect the adc? perfor- mance. a high-impedance source can be accommo- dated by placing a 1? capacitor between the input channel and agnd. the combination of analog-input source impedance and the capacitance at the analog input creates an rc filter that limits the analog-input bandwidth. controlling adc conversions use the following methods to control the adc conver- sion timing: 1) software register bit control 2) continuous conversion 3) internal timer (t0) 4) external input through adccnv refer to the maxq7670 user? guide for more detailed information on the adc and mux. por and brownout the MAXQ7670A operates from a single, external +5v supply connected to the dvddio. dvddio is the sup- ply rail for the digital i/o and the supply input for both integrated linear regulators. the +3.3v linear regulator powers avdd, while the +2.5v linear regulator powers dvdd. alternatively, connect regen2 to dvddio and apply external power supplies to avdd and dvdd. power supplies dvddio, dvdd, and avdd each include a brownout monitor that alerts the ? through an interrupt when the corresponding supply voltages drop below a defined threshold. this condition is gen- erally referred to as brownout interrupt (boi). enable boi by setting the vabe, vdbe, and vibe bits in the ape register. by continually checking for low supply voltages, appropriate action can be taken for brownout conditions. startup using internal regulators once the +5v dvddio supply reaches approximately 1.25v, the +2.5v linear regulator turns on and dvdd begins ramping. between the dvdd levels of 1v and the reset threshold, the dvdd monitor holds reset low. dvdd releases reset after reaching the reset threshold. the MAXQ7670A jumps to the reset vector location (8000h in the utility rom). during this time, dvdd finishes ramping to its nominal voltage of +2.5v. during this por time, the software-enabled +3.3v lin- ear regulator remains off. turn on the +3.3v linear regu- lator after the MAXQ7670A has completed its bootup routines and is running application code. to turn on the +3.3v regulator, set the lrapd bit in the ape register to 0. the avdd supply begins ramping to its nominal voltage of +3.3v. brownout detectors the MAXQ7670A features brownout monitors for the +5v dvddio, +3.3v avdd, and +2.5v dvdd power sup- plies. when enabled, these monitors generate interrupts when dvddio, avdd, or dvdd fall below their respec- tive brownout thresholds. monitoring the supply rails alerts the ? to brownout conditions so appropriate action can be taken. under normal conditions the dvddio brownout monitor signals a falling +5v supply before the dvdd or avdd brownout monitors indicate that the +2.5v or +3.3v are falling. the exceptions to this condi- tion are: ? if either dvdd or avdd are externally powered and the source of power is removed ? if there is some type of device failure that pulls the reg- ulator outputs low without affecting the +5v dvddio supply sar cycle pga = 1v/v sar cycle pga = 16v/v sar track hold and sar convert pga track pga hold, sar track hold and sar convert 3 sclk 13 sclk 7.5 sclk 6 sclk 13 sclk figure 5. conversion timing differences between gain = 1v/v and gain = 16v/v datasheet.in
MAXQ7670A microcontroller with 12-bit adc, pga, 64kb flash, and can interface ______________________________________________________________________________________ 21 the dvdd reset supervisor resets the MAXQ7670A when the +2.5v dvdd falls below the reset threshold. the processor remains in reset until dvdd returns above the reset threshold. the ? does not execute commands in reset mode. see figure 6 for the ? response to dvdd brownout and reset. refer to the maxq7670 user? guide for detailed pro- gramming information, and a more thorough descrip- tion of por and brownout behavior. internal 3.3v linear regulator the integrated 3.3v 50ma linear regulator or an exter- nal 3.3v supply powers avdd. the integrated 3.3v reg- ulator is inactive upon power-up. enable the integrated regulator with software programming after power-up. when using an external supply, connect a regulated 3.3v supply to avdd after applying dvddio. internal 2.5v linear regulator the integrated 2.5v 50ma linear regulator or an exter- nal 2.5v supply applied at dvdd powers dvdd. connect regen2 to gndio to enable the integrated regulator. connect regen2 to dvddio to use an external supply. when using an external supply, con- nect a regulated 2.5v supply to dvdd after applying dvddio. dvddio current requirements both internal linear regulators are capable of supplying up to 50ma each. when using the regulators to power avdd and dvdd and to provide power to external devices, make sure dvddio? power input can source a current greater than the sum of the MAXQ7670A sup- ply current and the load currents of the two regulators. dgnd nominal dvdd (+2.5v) brownout reset (bor) +2.38v internal reset bor state reset output +2.25v brownout interrupt (boi) dvlvl flag (asr[14]) dvbi flag (asr[4]) flag arbitrarily cleared by c vdbe bit set by c dvdd brownout interrupt threshold range figure 6. dvdd brownout and reset behavior datasheet.in
MAXQ7670A microcontroller with 12-bit adc, pga, 64kb flash, and can interface 22 ______________________________________________________________________________________ system clock generator the MAXQ7670A oscillator module provides the master clock generator that supplies the system clock for the ? core and all of the peripheral modules. the high-fre- quency oscillator operates with an 8mhz or 16mhz crystal. alternatively, use the integrated rc oscillator in applications that do not require precise timing. the MAXQ7670A executes most instructions in a single sysclk period. the oscillator module contains all of the primary clock generation circuitry. figure 7 shows a block diagram of the system clock module. the MAXQ7670A contains the following features for generating its master clock signal timing source: ? internal, fast-starting, 15mhz rc oscillator eliminates external crystal ? internal high-frequency oscillator that can drive an external 8mhz or 16mhz crystal ? external high-frequency 0.166mhz to 16mhz clock input ? power-up timer ? power-saving management modes ? fail-safe modes watchdog timer the primary function of the watchdog timer is to super- vise software execution, watching for stalled or stuck software. the watchdog timer performs a controlled system restart when the ? fails to write to the watch- dog timer register before a selectable timeout interval expires. a watchdog timer typically has four objectives: 1) to detect if a system is operating normally 2) to detect an infinite loop in any of the tasks 3) to detect an arbitration deadlock involving two or more tasks 4) to detect if some lower priority tasks are not getting to run because of higher priority tasks as illustrated in figure 8, the internal rc oscillator (clk_rc) drives the watchdog timer through a series of dividers. the programmable divider output deter- mines the timeout interval. when enabled, the interrupt flag wdif sets. a system reset occurs after a time delay (based on the divider ratio) unless an interrupt service routine clears the watchdog interrupt. the watchdog timer functions as the source of both the watchdog interrupt and the watchdog reset. the inter- rupt timeout has a default divide ratio of 2 12 of the clk_rc, with the watchdog reset set to timeout 2 9 clock cycles later. with the nominal rc oscillator value of 15mhz, an interrupt timeout occurs every 0.273ms, followed by a watchdog reset 34? later. the watchdog timer resets to the default divide ratio following any reset event. use the wd0 and wd1 bits in the wdcn register to increase the watchdog interrupt period. changing the wd[1:0] bits before a watchdog interrupt timeout occurs (i.e. before the watchdog reset counter begins) resets the watchdog timer count. the watch- dog reset timeout occurs 512 rc oscillator cycles after the watchdog interrupt timeout. for more information on the MAXQ7670A watchdog timer, refer to the maxq7670 user? guide. cd1 cd0 pmme sysclk mux clk_rc clock divide hf xtal osc rc osc xin xout xt exthf rce hfe figure 7. high-frequency and rc oscillator functional diagram ewdi wd0 rwt wd1 clk_rc (15mhz) interrupt wtrf reset wdif timeout time 2 12 div 2 12 div 2 3 div 2 3 div 2 3 2 15 2 18 2 21 ewt reset figure 8. watchdog functional diagram datasheet.in
MAXQ7670A microcontroller with 12-bit adc, pga, 64kb flash, and can interface ______________________________________________________________________________________ 23 timer and pwm the MAXQ7670A includes a 16-bit timer channel. the timer offers two ports, t0 and t0b, to facilitate pwm outputs, and capture timing events. the autoreload 16- bit timer/counter offers the following functions: ? 8-/16-bit timer/counter ? up/down autoreload ? counter function of external pulse ? capture ? compare ? pwm output ? event timer ? system supervisor refer to the maxq7670 user? guide and application note 3205: using timers in the maxq family of microcontrollers for more information about the timer module. can interface bus the MAXQ7670A incorporates a fully compliant can 2.0b controller. two groups of registers provide the ? interface to the can controller. to simplify the software associated with the operation of the can controllers, most of the global can status and controls as well as the individual mes- sage center control/status registers are located in the peripheral register map. the remaining registers asso- ciated with the data identification, identification masks, format, and data are located in a dual port memory to allow the can controller and the processor access to the required functions. the can controller can directly access the dual port memory. the processor accesses the dual port memory through a dedicated interface that consists of the can 0 data pointer (c0dp) and the can 0 data buffer (c0db) special function registers. see figure 9 for can controller details. can functional description the can module stores up to 15 messages. each mes- sage consists of an acceptance identifier and 8 bytes of data. the MAXQ7670A supports both the standard 11-bit and extended 29-bit identification modes. configure each of the first 14 message centers either to transmit or receive. message center 15 is a receive- only center, storing any message that centers 1?4 do not accept. a message center only accepts an incoming message if the following conditions are satisfied: ? the incoming message? arbitration value matches the message center? acceptance identifier ? the first 2 data bytes of the incoming message match the bytes in the media arbitration registers (c0ma0 and c0ma1) use the global mask registers to mask out bits in the incoming message that do not require a comparison. a message center, configured to transmit, meets these conditions: t/r = 1, tih = 0, dtup = 1, msrdy = 1, and mtrq = 1. the message center transmits its con- tents when it receives an incoming request message containing the same identifier (i.e., a remote frame). global control and status registers in the can unit enable the ? to evaluate error messages, validate and locate new data, establish the bus timing for the can bus, establish the identification mask bits, and verify the source of individual messages. in addition, each mes- sage center is individually equipped with the necessary status and controls to establish directions, interrupt gen- eration, identification mode (standard or extended), data field size, data status, automatic remote frame request and acknowledgment, and masked or nonmasked identi- fication acceptance testing. jtag interface bus the joint test action group (jtag) ieee ? 1149.1 stan- dard defines a unique method for in-circuit testing and programming. the MAXQ7670A conforms to this stan- dard, implementing an external test access port (tap) and internal tap controller for communication with a jtag bus master, such as an automatic test equipment (ate). for detailed information on the tap and tap controller, refer to ieee standard 1149.1 on the ieee website at www.standards.ieee.org. the jtag on the MAXQ7670A does not support boundary scan test capability. ieee is a registered service mark of the institute of electrical and electronics engineers. datasheet.in
MAXQ7670A microcontroller with 12-bit adc, pga, 64kb flash, and can interface 24 ______________________________________________________________________________________ the tap controller communicates synchronously with the host system (bus master) through four digital i/os: test mode select (tms), test clock (tck), test data input (tdi), and test data output (tdo). the internal tap module consists of several shift registers and a tap controller (see figure 11). the shift registers serve as transmit-and-receive data buffers for a debugger. 4-wire spi bus the MAXQ7670A includes a powerful hardware spi module, providing serial communication with a wide variety of external devices. the spi port on the MAXQ7670A is a fully independent module that is accessed through software. this full 4-wire, full-duplex serial bus module supports master and slave modes. can 0 controller block diagram dual port memory can processor can 0 peripheral registers message centers 1?15 bus activity wake-up 8-bit rx crc check bit destuff rx shift bit timing canrxd cantxd message center 2 arbitration 0?3 format data 0?7 message center 1 arbitration 0?3 format data 0?7 message center 15 control/status/mask registers arbitration 0?3 media arbitration 0?1 ext global mask 0?3 media id mask 0?1 std global mask 0?1 bus timing 0?1 msg15 mask 0?3 format data 0?7 message center 14 arbitration 0?3 format data 0?7 can 0 transmit msg ack can 0 interrupt register can 0 status register can 0 receive msg ack can 0 operation control can 0 control register can 0 data pointer can 0 message 1?15 control registers can 0 data buffer can 0 transmit error counter can 0 receive error counter can interrupt sources 8-bit tx crc generate can protocol fsm bit stuff tx shift MAXQ7670A figure 9. can 0 controller block diagram datasheet.in
MAXQ7670A microcontroller with 12-bit adc, pga, 64kb flash, and can interface ______________________________________________________________________________________ 25 the spi clock frequency is limited to sysclk/2 in mas- ter mode and sysclk/8 in slave mode. figure 10 shows the functional diagram of the spi port. figures 1 and 2 illustrate the timing parameters listed in the electrical characteristics table. general-purpose digital i/os the MAXQ7670A provides seven general-purpose digi- tal i/os (gpios). some of the gpios include an addi- tional special function (sf), such as a timer input/output. for example, the state of p0.6/t0 is pro- grammable to depend on timer channel 0 logic. when used as a port, each i/o is configurable for high-imped- ance, weak pullup to dvddio or pulldown to gndio. at power-up, each gpio is configured as an input with a pullup to dvddio. in addition, each gpio can be programmed to cause an interrupt (on falling or rising edges). in stop mode, use any interrupt to wake-up the device. the port direction (pd) register determines the input/output direction of each i/o. the port output (po) register contains the current state of the logic output buffers. when an i/o is configured as an output, writing to the po register controls the output logic state. reading the po register shows the current state of the output buffers, independent of the data direction. the sfr data bus read buffer shift register lsb(0) msb (15) miso master slave slave spi control unit sysclk spi interrupt /2 master (max) /8 slave (max) shift clk 0 7 spi contrl reg (spicn) spi contrl reg (spicf) spi contrl reg (spick) master/slave select sclk out sclk in spi enable master mosi sclk dvddio dvddio slave master MAXQ7670A ss figure 10. spi functional diagram datasheet.in
MAXQ7670A microcontroller with 12-bit adc, pga, 64kb flash, and can interface 26 ______________________________________________________________________________________ port input (pi) register is a read-only register that always reflects the logic state of the i/os. the drive capability of the i/o, when configured for out- put, depends on the value in the ps0 (pad drive strength) register and can be set for either 1ma or 2ma. when an i/o is configured as an input, writing to the po register enables/disables the pullup/pulldown resistor. the value in the pro (pad resistive pull direc- tion) register sets the enabled resistor at the i/o as either a pullup to dvddio or pulldown to gndio. refer to the maxq7670 user? guide for more detailed information. port characteristics the MAXQ7670A includes a bidirectional 7-bit i/o port (p0) whose features include: ? schmitt trigger input circuitry with software-selectable high-impedance or weak pullup to dvddio or pull- down to gndio ? software-selectable push-pull cmos output drivers capable of sinking and sourcing 0.5ma ? falling or rising edge interrupt capability ? p0.4, p0.6, and p0.7 i/os contain an additional special function, such as a logic input/output for a timer channel ? selectable pad drive strength and resistive pull direction refer to the maxq7670 user? guide for more details. figure 11 illustrates the functional blocks of an i/o. maxq20 core architecture the MAXQ7670A? core is a member of the low-cost, high-performance, cmos, fully static, 16-bit maxq20 core ?s. the MAXQ7670A is structured on a highly advanced, accumulator-based, 16-bit risc architec- ture. fetch and execution operations complete in one cycle without pipelining because the instruction con- tains both the op code and data. the result is a stream- lined 1 million instructions-per-second-per-megahertz (mips/mhz) ?. the highly efficient core is supported by a 16-level hardware stack, enabling fast subroutine calling and task switching. the internal data pointers manipulate data quickly and efficiently. multiple data pointers allow more than one function to access data memory without having to save and restore data pointers each time. the data pointers can automatically increment or decre- ment following an operation, eliminating the need for software intervention and increasing application speed. instruction set the instruction set is composed of fixed-length, 16-bit instructions that operate on registers and memory loca- tions. the highly orthogonal instruction set allows arith- metic and logical operations to use any register along with the accumulator. special-function registers (also called peripheral registers) control the peripherals and are subdivided into register modules. the modular fam- ily architecture allows new devices and modules to reuse code developed for existing products. the archi- tecture is transport-triggered. this means that writes or reads from certain register locations can also cause side effects to occur. these side effects form the basis for the higher-level op codes defined by the assembler, such as addc, or, jump, etc. memory organization the MAXQ7670A incorporates the following memory areas (see figure 12): ? 8kb (4k x 16) utility rom ? 64kb (32k x 16) of flash memory for program storage ? 2048 bytes (1024 x 16) of sram for storage of tempo- rary variables ? 16-level stack memory for storage of program return addresses and general-purpose use a 16-bit-wide x 16 deep internal hardware stack pro- vides storage for program return addresses and gener- al-purpose use. the MAXQ7670A core implicitly uses the stack when executing an interrupt service routine (isr) and also when running call, ret, and reti instructions. the stack can also be explicitly used by MAXQ7670A v dvddio p n pi0._ po0._ ps0._ pd0._ pullup/ pulldown logic pr0._ pd0._ po0._ p0._ figure 11. digital i/o circuitry datasheet.in
MAXQ7670A microcontroller with 12-bit adc, pga, 64kb flash, and can interface ______________________________________________________________________________________ 27 the application code to store data when context switch- ing (e.g., during a call or an interrupt). storing and retrieving data is executed through the push, pop, and popi instructions. the incorporation of flash memory allows device repro- gramming, eliminating the expense of discarding one- time programmable devices during development and field upgrades (see figure 13 for the flash memory sec- tor maps). a 16-word key protects the flash memory from access by unauthorized individuals. without supplying the 16- word key, the password lock (pwl) bit in the sc regis- ter remains set, and the utility rom is inaccessible. supplying the 16-word key makes the utility rom trans- parent. the password-unlock command is issued through the tap interface. the 16-word password is compared to the password in the program space to determine its validity. enabling a pseudo-von neumann memory map places the utility rom, code, and data memory into a single contiguous memory map. use this mapping scheme for applications that require dynamic program modification or unique memory configurations. executing from program space data space (word mode) 1024 x 16 data ram 4k x 16 utility rom 32k x 16 program flash ffffh a3ffh 7fffh 0000h a400h a000h 8fffh 8000h 8fffh 8000h 03ffh 0000h ffffh 7fffh 0400h 9000h data space (byte mode) 8k x 8 utility rom 2048 x 8 data ram ffffh 7fffh 0400h 03ffh 0000h 9000h 8fffh 8000h 1024 x 16 data ram 4k x 16 utility rom figure 12. MAXQ7670A memory map 32k x 16 program flash 7fffh 0000h 1 page = 256 words page 127 page 126 page 125 page 2 page 1 page 0 figure 13. flash memory sector maps datasheet.in
MAXQ7670A microcontroller with 12-bit adc, pga, 64kb flash, and can interface 28 ______________________________________________________________________________________ stack memory a 16-bit-wide x 16 deep internal hardware stack pro- vides storage for program return addresses and gener- al-purpose use. the processor uses the stack automatically when executing the call, ret, and reti instructions and when servicing interrupts. the stack stores and retrieves data through the push, pop, and popi instructions. on reset, the stack pointer, sp, initializes to the top of the stack (0fh). the call, push, and interrupt-vector- ing operations increment sp, then store a value at the location pointed to by sp. the ret, reti, pop, and popi operations retrieve the value at sp and then decrement sp. utility rom the utility rom is a 8kb (4k x 16) block of internal rom memory that defaults to a starting address of 8000h. the utility rom consists of subroutines accessed from application software. these include: ? in-system programming (bootstrap loader) over jtag and can ? in-circuit debug routines ? routines for in-application flash programming and fast table lookup following any reset, execution begins in the utility rom. the rom software determines whether the program exe- cution should immediately jump to location 0000h, the start of user-application code, or to one of the above rou- tines. utility rom routines are accessible in the applica- tion software. for more information on the utility rom contents, refer to the maxq7670 user? guide . programming flash memory the MAXQ7670A allows the user to program its flash through the jtag or the can port by allowing access to the rom-based bootloader through these ports. the bootloader is entered in one of three ways: by a jtag request during the power-up sequence, through a can request immediately after power-up when no password has been set, and by jumping to the bootloader from the application code. after a reset, the MAXQ7670A instruction pointer jumps to the beginning of rom code (0x8000). the rom code does some initial housekeep- ing and then looks for a request from the jtag port. if there is a valid request (i.e., spe = 1, pss = 00), the processor establishes communication between the rom bootloader and the jtag port. if there is no jtag request and the password has been set (0x0010 to 0x001f is not all 0s or all fs), then program execution jumps to the application code at address 0x0000. if the password has not been set (0x0010 to 0x001f is all 0s or all fs), the rom code monitors the can port for 5s waiting to receive 0x3e. if this character is not detected within 5s, program execution jumps to the application code at address 0x000. if 0x3e is detected during the five-second window, the can port is established as the bootloader communication port and the MAXQ7670A responds with 0x3e, verifying that it is in the loader mode. can bootloader communication speed is set to 500kbaud when using a 16mhz crystal and 250kbaud when using an 8mhz crystal. once communication has been established with the loader, the host has access to all the family 0 com- mands regardless of the state of the pwl bit. if pwl = 0, all the loader commands are accessible. family 0 commands all start with a 0 and provide basic function- ality, but do not allow access to information in either program memory or data memory. this prevents unau- thorized access of proprietary information. a mass erase of the flash sets all flash memory including the password to 0xffff. with this condition, it is as if no password has been set and the pwl bit is set to 0, which allows access to all loader commands. for more information on password protection and loader com- mands, refer to the maxq7670 user? guide . in-application programming the in-application programming feature allows the ? to modify its own flash program memory while simulta- neously executing its application software. this allows on-the-fly software updates in mission-critical applica- tions that cannot afford downtime. in-application pro- gramming also allows the application to develop custom loader software that can operate under the con- trol of the application software. the utility rom contains user-accessible flash programming functions that erase and program flash memory. these functions are described in detail in the maxq7670 user? guide . register set register sets control the MAXQ7670A functions. these registers provide a working space for memory opera- tions as well as configuring and addressing peripheral registers on the device. registers are divided into two major types: system registers and peripheral registers. the common register set, also known as the system registers, includes the alu, accumulator registers, data pointers, interrupt vectors and control, and stack point- er. tables 2? show the MAXQ7670A register set. datasheet.in
MAXQ7670A microcontroller with 12-bit adc, pga, 64kb flash, and can interface ______________________________________________________________________________________ 29 power management advanced power-management features minimize power consumption by dynamically matching the pro- cessing speed of the device to the required perfor- mance level. during periods of reduced activity, lower the system clock speed to reduce power consumption. use the source-clock-divide feature to reduce the sys- tem clock speed to 1/2, 1/4, and 1/8 of the source clock? speed. a lower power state is thus achievable without additional hardware. for extremely power-sen- sitive applications, two additional low-power modes are available: ? pmm: divide-by-256 power-management mode (pmme = 1) ? stop mode (stop = 1) enabling pmm reduces the system clock speed to 1/256 of the source clock speed, and significantly reduces power consumption. the optional switchback feature allows enabled interrupt sources including external, can, and spi interrupts to bring the ? out of the power-management mode and to run at a faster system clock speed. power consumption is minimal in stop mode. in this mode, the external oscillator, internal rc oscillator, sys- tem clock, and all processing activity stop. triggering an enabled external interrupt or applying an external reset signal to reset brings the ? out of stop mode. upon exiting stop mode, the ? can either wait for the external crystal to warm up, or execute immediately by using the internal rc oscillator as the crystal warms up. interrupts multiple interrupt sources are available for quick response to internal and external events. examples of events that can trigger an interrupt are: ? watchdog interrupt ? gpio0?pio7 interrupts ? spi mode fault, write collision, receive overrun, and transfer complete interrupts ? timer 0 low compare, low overflow, capture/compare, and overflow interrupts ? can0 receive and transmit interrupts and a change in can0 status register interrupt ? adc data ready interrupt ? voltage brownout interrupts ? crystal oscillator failure interrupt each interrupt has flag and enable bits. the flag indi- cates whether an interrupt event has occurred. enable the ? to generate an interrupt by setting the enable bit. interrupts are organized into modules. enable the interrupt individually, by module, and globally. the ? jumps to an isr after an enabled interrupt event occurs. use the interrupt identification register (iir) to determine whether the interrupt is a system or peripher- al interrupt. in the isr, clear the interrupt flag to elimi- nate repeated interrupts from the same event. after clearing the interrupt, allow a delay before issuing the return from interrupt (reti) instruction. asynchronous interrupt flags require a one-instruction delay and syn- chronous interrupt flags require a two-instruction delay. the maxq architecture uses a single interrupt vector (iv) and single isr design. the iv register holds the address of the isr. in the application code, assign a unique address to each isr. otherwise, the iv automat- ically jumps to 0000h, the beginning of application code, after an enabled interrupt occurs. reset sources reset sources are provided for ? control. although code execution stops in the reset state, the internal rc oscillator continues to oscillate. internal resets, such as the power-on and watchdog resets, pull reset low. power-on reset (por) an internal por circuit enhances system reliability. the por circuit forces the device to perform a por when- ever a rising voltage on dvdd climbs above the por threshold. at this point the following events occur: ? all registers and circuits enter the default state ? the por flag (wdcn.7) sets to indicate if the source of the reset was a loss of power ? the internal 15mhz rc oscillator becomes the clock source ? code execution begins at location 8000h refer to the maxq7670 user? guide for more information. watchdog timer reset the watchdog timer functions are described in the maxq7670 user? guide . execution resumes at loca- tion 8000h following a watchdog timer reset. external system reset pulling reset low externally causes the device to enter the reset state. the external reset functions as described in the maxq7670 user? guide . execution resumes at location 8000h after reset is released. datasheet.in
MAXQ7670A microcontroller with 12-bit adc, pga, 64kb flash, and can interface 30 ______________________________________________________________________________________ crystal selection the MAXQ7670A uses an 8mhz or 16mhz jauch jxg53p2 (or similar specification): frequency: 8mhz or 16mhz ?.25%. c load : 12pf. c o : < 7pf max. series resonance resistance: max 50 ? /300 ? for 16mhz/8mhz, respectively. note: series resonance resistance is the resistance observed when the resonator is in the series resonant condition. this is a parameter often stated by quartz crystal vendors and is called r1. when a resonator is used in the parallel resonant mode with an external load capacitance, as is the case with the MAXQ7670A oscillator circuit, the effective resistance is sometimes stated. this effective resistance at the loaded frequen- cy of oscillation is: r1 x (1 + (c o /c load ))2 for typical c o and c load values, the effective resis- tance can be greater than r1 by a factor of two. development and technical support highly versatile, affordably priced development tools for this ? are available from maxim and third-party suppliers. tools for the MAXQ7670A include: ? compilers ? evaluation kits ? jtag-to-serial converters for programming and debugging a list of development tool vendors can be found at www.maxim-ic.com/microcontrollers . for technical support, go to www.maxim-ic.com/support . module name (base specifier) register index ap (8h) a (9h) pfx (bh) ip (ch) sp (dh) dpc (eh) dp (fh) 0h ap a[0] pfx[0] ip 1h apc a[1] pfx[1] sp 2h a[2] pfx[2] iv 3h a[3] pfx[3] offs dp0 4h psf a[4] pfx[4] dpc 5h ic a[5] pfx[5] gr 6h imr a[6] pfx[6] lc0 grl 7h a[7] pfx[7] lc1 bp dp1 8h sc a[8] grs 9h a[9] grh ah a[10] grxl bh iir a[11] fp ch a[12] dh a[13] eh ckcn a[14] fh wdcn a[15] table 2. system register map datasheet.in
MAXQ7670A microcontroller with 12-bit adc, pga, 64kb flash, and can interface ______________________________________________________________________________________ 31 register bit register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ap (4 bits) ap 00000000 clr ids mod2 mod1 mod0 apc 00000000 z s gpf1 gpf0 ov c e psf 10000000 cgds ins ige ic 00000000 ims im5 im4 im3 im2 im1 im0 imr 00000000 tap cda1 cda0 upa rod pwl sc 100 000s*0 iis ii5 ii4 ii3 ii2 ii1 ii0 iir 00000000 xt rgmd stop swb pmme cd1 cd0 ckcn s* 0 s* 0 0 0 0 1 por ewdi wd1 wd0 wdif wtrf ewt rwt wdcn s* s* 0 0 0 s* s* 0 a[n] (16 bits) a[n] (0..15) 0000000000 0 00 0 0 0 pfx[n] (16 bits) pfx[n] (0..15) 0000000000 0 00 0 0 0 ip (16 bits) ip 1000000000 0 00 0 0 0 sp (4 bits) sp 0000000000 0 01 1 1 1 iv (16 bits) iv 0000000000 0 00 0 0 0 lc[0] (16 bits) lc[0] 0000000000 0 00 0 0 0 lc[1] (16 bits) lc[1] 0000000000 0 00 0 0 0 offs (8 bits) offs 00000000 wbs2 wbs1 wbs0 sdps1 sdps0 dpc 0000000000 0 11 1 0 0 gr.15 gr.14 gr.13 gr.12 gr.11 gr.10 gr.9 gr.8 gr.7 gr.6 gr.5 gr.4 gr.3 gr.2 gr.1 gr.0 gr 0000000000 0 00 0 0 0 gr.7 gr.6 gr.5 gr.4 gr.3 gr.2 gr.1 gr.0 grl 00000000 bp (16 bits) bp 0000000000 0 00 0 0 0 gr.7 gr.6 gr.5 gr.4 gr.3 gr.2 gr.1 gr.0 gr.15 gr.14 gr.13 gr.12 gr.11 gr.10 gr.9 gr.8 grs 0000000000 0 00 0 0 0 gr.15 gr.14 gr.13 gr.12 gr.11 gr.10 gr.9 gr.8 grh 00000000 gr.7 gr.7 gr.7 gr.7 gr.7 gr.7 gr.7 gr.7 gr.7 gr.6 gr.5 gr.4 gr.3 gr.2 gr.1 gr.0 grxl 0000000000 0 00 0 0 0 fp (16 bits) fp 0000000000 0 00 0 0 0 dp[0] (16 bits) dp[0] 0000000000 0 00 0 0 0 dp[1] (16 bits) dp[1] 0000000000 0 00 0 0 0 table 3. system register bit and reset values *bits indicated by an "s" are only affected by a por and not by other forms of reset. these bits are set to 0 after a por. refe r to the maxq7670 user? guide for more information. datasheet.in
MAXQ7670A microcontroller with 12-bit adc, pga, 64kb flash, and can interface 32 ______________________________________________________________________________________ register index m0 (0h) m1 (1h) m2 (2h) m3 (3h) m4 (4h) m5 (5h) 0h po0 t2cna0 c0c 1h t2ho c0s ape 2h t2rho coir acntl 3h eifo t2cho c0te 4h c0re 5hc0r 6h spib c0dp 7h spicn c0db 8h pi0 spicf t2cnbo c0rms adcd 9h spick t2vo c0tma ah fcntl t2ro aie bh eieo t2co asr ch oscc dh eh fh 10h pd0 t2cfg0 11h fpctl c0m1c 12h c0m2c 13h eieso c0m3c 14h c0m4c 15h c0m5c 16h c0m6c 17h c0m7c 18h ps0 icdt0 c0m8c 19h icdt1 c0m9c 1ah icdc c0m10c 1bh pro icdf c0m11c 1ch id0 icdb c0m12c 1dh icda c0m13c 1eh icdd c0m14c 1fh tm c0m15c table 4. peripheral register map datasheet.in
MAXQ7670A microcontroller with 12-bit adc, pga, 64kb flash, and can interface ______________________________________________________________________________________ 33 register bit register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 po0.7 po0.6 po0.5 po0.4 po0.2 po0.1 po0.0 po0 0 0 0 0 0 0 0 011 1 101 1 1 ie7 ie6 ie5 ie4 ie2 ie1 ie0 eif0 0 0 0 0 0 0 0 000 0 000 0 0 pi0.7 pi0.6 pi0.5 pi0.4 pi0.2 pi0.1 pi0.0 pi0 0 0 0 0 0 0 0 0 st st st st 0 st st st ex7 ex6 ex5 ex4 ex2 ex1 ex0 eie0 0 0 0 0 0 0 0 0 00 0 000 0 0 pd0.7 pd0.6 pd0.5 pd0.4 pd0.2 pdo.1 pd0.0 pd0 0 0 0 0 0 0 0 0 00 0 000 0 0 it7 it6 it5 it4 it2 it1 it0 eies0 0 0 0 0 0 0 0 000 0 000 0 0 ps7 ps6 ps5 ps4 ps2 ps1 ps0 ps0 0 0 0 0 0 0 0 000 0 000 0 0 pr7 pr6 pr5 pr4 pr2 pr1 pr0 pr0 0 0 0 0 0 0 0 000 0 000 0 0 spib.15 spib.14 spib.13 spib.12 spib.11 spib.10 spib.9 spib.8 spib.7 spib.6 spib.5 spib.4 spib.3 spib.2 spib.1 spib.0 spib 0 0 0 0 0 0 0 0 00 0 000 0 0 stby spic rovr wcol modf modfe mstm spien spicn 0 0 0 0 0 0 0 0 00 0 000 0 0 espii chr ckpha ckpol spicf 0 0 0 0 0 0 0 0 00 0 000 0 0 spick7 spick6 spick5 spick4 spick3 spick2 spick1 spick0 spick 0 0 0 0 0 0 0 000 0 000 0 0 fbusy fc2 fc1 fc0 fcntl 0 0 0 0 0 0 0 010 0 000 0 0 dpmg fpctl 0 0 0 0 0 0 0 000 0 000 0 0 id0.7 id0.6 id0.5 id0.4 id0.3 id0.2 id0.1 id0.0 id0 0 0 0 0 0 0 0 0 00 0 000 0 0 et2 t2oe0 t2pol0 tr2l tr2 cprl2 ss2 g2en t2cna0 0 0 0 0 0 0 0 0 00 0 000 0 0 t2h0.7 t2h0.6 t2h0.5 t2h0.4 t2h0.3 t2h0.2 t2h0.1 t2h0.0 t2h0 0 0 0 0 0 0 0 0 00 0 000 0 0 t2rh0.7 t2rh0.6 t2rh0.5 t2rh0.4 t2rh0.3 t2rh0.2 t2rh0.1 t2rh0.0 t2rh0 0 0 0 0 0 0 0 000 0 000 0 0 t2ch0.7 t2ch0.6 t2ch0.5 t2ch0.4 t2ch0.3 t2ch0.2 t2ch0.1 t2ch0.0 t2ch0 0 0 0 0 0 0 0 000 0 000 0 0 et2l t2oe1 t2pol1 tf2 tf2l tcc2 tc2l t2cnb0 0 0 0 0 0 0 0 000 0 000 0 0 t2v0.15 t2v0.14 t2v0.13 t2v0.12 t2v0.11 t2v0.10 t2v0.9 t2v0.8 t2v0.7 t2v0.6 t2v0.5 t2v0.4 t2v0.3 t2v0.2 t2v0.1 t2v0.0 t2v0 0 0 0 0 0 0 0 0 00 0 000 0 0 t2r0.15 t2r0.14 t2r0.13 t2r0.12 t2r0.11 t2r0.10 t2r0.9 t2r0.8 t2r0.7 t2r0.6 t2r0.5 t2r0.4 t2r0.3 t2r0.2 t2r0.1 t2r0.0 t2r0 0 0 0 0 0 0 0 0 00 0 000 0 0 t2c0.15 t2c0.14 t2c0.13 t2c0.12 t2c0.11 t2c0.10 t2c0.9 t2c0.8 t2c0.7 t2c0.6 t2c0.5 t2c0.4 t2c0.3 t2c0.2 t2c0.1 t2c0.0 t2c0 0 0 0 0 0 0 0 0 00 0 000 0 0 t2c1 t2div2 t2div1 t2div0 t2md ccf1 ccf0 c/t2 t2cfg0 00000000000000 0 0 icdt0.15 icdt0.14 icdt0.13 icdt0.12 icdt0.11 icdt0.10 icdt0.9 icdt0.8 icdt0.7 icdt0.6 icdt0.5 icdt0.4 icdt0.3 icdt0.2 icdt0.1 icdt0.0 icdt0 db db db db db db db db db db db db db db db db icdt1.15 icdt1.14 icdt1.13 icdt1.12 icdt1.11 icdt1.10 icdt1.9 icdt1.8 icdt1.7 icdt1.6 icdt1.5 icdt1.4 icdt1.3 icdt1.2 icdt1.1 icdt1.0 icdt1 db db db db db db db db db db db db db db db db dme rege cmd3 cmd2 cmd1 cmd0 icdc 0 0 0 0 0 0 0 0 dw 0 dw 0 dw dw dw dw pss1 pss0 spe txc icdf 00000000000000 0 0 icdb.7icdb.6icdb.5icdb.4icdb.3icdb.2ic db.1 icdb.0 icdb 00000000000000 0 0 icda.15 icda.14 icda.13 icda.12 icda.11 icda.10 icda.9 icda.8 icda.7 icda.6 icda.5 icda.4 icda.3 icda.2 icda.1 icda.0 icda 00000000000000 0 0 icdd.15 icdd.14 icdd.13 icdd.12 icdd.11 icdd.10 icdd.9 icdd.8 icdd.7 icdd.6 icdd.5 icdd.4 icdd.3 icdd.2 icdd.1 icdd.0 icdd 00000000000000 0 0 table 5. peripheral register bit functions and reset values datasheet.in
MAXQ7670A microcontroller with 12-bit adc, pga, 64kb flash, and can interface 34 ______________________________________________________________________________________ register bit register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 crtms crtm testcan dcw ftest doff srt scanmode tme tm 00000000000000 0 0 erie stie pde siesta crst autob ercs swint c0c 00000000000010 0 1 bss ec96/128 wks rxs txs er2 er1 er0 c0s 00000000000000 0 0 intin7 intin6 intin5 intin4 intin3 intin2 intin1 intin0 c0ir 00000000000000 0 0 c0te.7 c0te.6 c0te.5 c0te.4 c0te.3 c0te.2 c0te.1 c0te.0 c0te 00000000000000 0 0 c0re.7 c0re.6 c0re.5 c0re.4 c0re.3 c0re.2 c0re.1 c0re.0 c0re 00000000000000 0 0 can0ba incdec aid c0bpr7 c0bpr6 c0bie c0ie cor 00000000000000 0 0 c0dp.15 c0dp.14 c0dp.13 c0dp.12 c0dp.11 c0dp.10 c0dp.9 c0dp.8 c0dp.7 c0dp.6 c0dp.5 c0dp.4 c0dp.3 c0dp.2 c0dp.1 c0dp.0 c0dp 00000000000000 0 0 c0db.15 c0db.14 c0db.13 c0db.12 c0db.11 c0db.10 c0db.9 c0db.8 c0db.7 c0db.6 c0db.5 c0db.4 c0db.3 c0db.2 c0db.1 c0db.0 c0db 00000000000000 0 0 c0rms.15 c0rms.14 c0rms.13 c0rms.12 c0rms.11 c0rms.10 c0rms.9 c0rms.8 c0rms.7 c0rms.6 c0rms.5 c0rms.4 c0rms.3 c0rms.2 c0rms.1 c0rms 00000000000000 0 0 c0tma.15 c0tma.14 c0tma.13 c0tma.12 c0tma.11 c0tma.10 c0tma.9 c0tma.8 c0tma.7 c0tma.6 c0tma.5 c0tma.4 c0tma.3 c0tma.2 c0tma.1 c0tma 00000000000000 0 0 msrdy eti eri intrq extrq mtrq row/tih dtup c0m1c 00000000000000 0 0 msrdy eti eri intrq extrq mtrq row/tih dtup c0m2c 00000000000000 0 0 msrdy eti eri intrq extrq mtrq row/tih dtup c0m3c 00000000000000 0 0 msrdy eti eri intrq extrq mtrq row/tih dtup c0m4c 00000000000000 0 0 msrdy eti eri intrq extrq mtrq row/tih dtup c0m5c 00000000000000 0 0 msrdy eti eri intrq extrq mtrq row/tih dtup c0m6c 00000000000000 0 0 msrdy eti eri intrq extrq mtrq row/tih dtup c0m7c 00000000000000 0 0 msrdy eti eri intrq extrq mtrq row/tih dtup c0m8c 00000000000000 0 0 msrdy eti eri intrq extrq mtrq row/tih dtup c0m9c 00000000000000 0 0 msrdy eti eri intrq extrq mtrq row/tih dtup c0m10c 00000000000000 0 0 msrdy eti eri intrq extrq mtrq row/tih dtup c0m11c 00000000000000 0 0 msrdy eti eri intrq extrq mtrq row/tih dtup c0m12c 00000000000000 0 0 table 5. peripheral register bit functions and reset values (continued) datasheet.in
MAXQ7670A microcontroller with 12-bit adc, pga, 64kb flash, and can interface ______________________________________________________________________________________ 35 bits indicated by ?are unused. bits indicated by ?b?have read/write access only in background or debug mode. these bits are cleared after a por. bits indicated by ?w?are only written to in debug mode. these bits are cleared after a por. the oscc register is cleared to 0002h after a por and is not affected by other forms of reset. register bit register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 msrdy eti eri intrq extrq mtrq row/tih dtup c0m13c 00000000000000 0 0 msrdy eti eri intrq extrq mtrq row/tih dtup c0m14c 00000000000000 0 0 msrdy eti eri intrq extrq mtrq row/tih dtup c0m15c 00000000000000 0 0 lrapd vibe vdbe vdpe vabe pgg0 biase adce ape 00100100000000 0 0 adcmx3 adcmx2 adcmx1 adcmx0 adcbip adcdul adcrsef adcasd adcby adcs2 adcs1 adcs0 acnt 0000000000000 0 0 adcd.9 adcd.8 adcd.7 adcd.6 adcd.5 adcd.4 adcd.3 adcd.2 adcd.1 adcd.0 adcd 00000000000000 0 0 hffie viobie dvbie avbie adcie aie 00000000000000 0 0 violvl dvlvl avlvl xhfry hffint viobi dvbi avbi adcry asr 00000000000000 0 0 adccd1 adccd0 xte rce oscc 00000000000000 0 0 table 5. peripheral register bit functions and reset values (continued) datasheet.in
MAXQ7670A microcontroller with 12-bit adc, pga, 64kb flash, and can interface 36 ______________________________________________________________________________________ MAXQ7670A 12-bit adc pga x16 mux mux -2nf -2nf r+dr r-dr r-dr r+dr vbridgea gnda outa+ outa- -2nf -2nf r+dr r-dr r-dr r+dr vbridgeb gndb outb+ outb- dual-bridge sensor -2nf -2nf r+dr r-dr r-dr r+dr vbridgea gnda outa+ outa- -2nf -2nf 0.47 f r+dr r-dr r-dr r+dr vbridgeb gndb outb+ outb- dual-bridge sensor ain0 ain2 ain4 ain6 ain1 ain3 ain5 ain7 gpio 16-bit timer spi jtag can 2.0b 64kb program/data flash 2kb data ram maxq20 core 16-bit risc micro 0.47 f +3.3v 16mhz avdd digital i/o spi refadc i.c. 0.1 f 0.1 f 0.1 f 15 f dvddio p0.7/t0b p0.6/t0 p0.5 p0.4/adccnv sclk miso mosi ss p0.2 p0.1 p0.0 jtag can tck tdi tms cantxd canrxd tdo dvdd agnd gndio dgnd en hold 10 f max5024lasa out +12v reset reset set regen2 external reset is optional in gnd v dd (+5v) xin xout txd v cc rxd max13053asa/aut s ref gnd v dd +2.5v canh canl to can bus to can bus 60 ? 60 ? 4.7nf typical application circuit datasheet.in
MAXQ7670A microcontroller with 12-bit adc, pga, 64kb flash, and can interface ______________________________________________________________________________________ 37 MAXQ7670A top view 5 6 4 3 22 21 23 p0.0 p0.2 gndio canrxd cantxd 24 i.c. dvdd xout dgnd gndio dvddio avdd reset p0.5 11 12 ain4 14 15 16 17 37 38 39 40 36 34 33 32 refadc agnd tms tdo regen2 miso p0.1 xin 13 35 7 ain3 mosi 8 9 10 ain2 ain1 ain0 sclk gndio *ep dvddio ain5 2 25 tdi ain6 1 26 27 28 29 30 tck ss p0.6/to p0.7/tob p0.4/adccnv 18 19 20 31 ain7 + pin configuration chip information process: cmos package information for the latest package outline information and land patterns, go to www.maxim-ic.com/packages . note that a ?? ?? or ??in the package code indicates rohs status only. package draw- ings may show a different suffix character, but the drawing per- tains to the package regardless of rohs status. package type package code outline no. land pattern no. 40 tqfn-ep t4055+1 21-0140 90-0121 datasheet.in
MAXQ7670A microcontroller with 12-bit adc, pga, 64kb flash, and can interface maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 38 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2010 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 0 6/10 initial release datasheet.in

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