application note 1 of 10 www.xicor.com AN21 x5043/x5045 system supervisors manage 8051 type microcontrollers by applications staff, may 2001 both the x5043 and x5045 feature a power on reset circuit, low voltage reset controller, programmable watchdog timer, and 4k bits of high speed, three-wire serial, nonvolatile eeprom in a single 8-pin package. power-on-reset (por) the x5043/x5045 power-on-reset circuit holds the reset pin active for 250ms when the system power is applied. this prevents the microcontroller from operating while the power supply is stabilizing. this improves the reliability of system start up. low voltage reset (lvr) during operation, the low voltage reset circuit monitors the supply voltage. if the voltage drops below a speci?d minimum, the x5043/x5045 drives the reset pin active. this stops the operation of the microcontroller to prevent unexpected operation. if the microcontroller operates at voltages that are too low, the microcontroller or a peripheral device may fail, causing the system to "lock-up" or resulting in data corruption. watchdog timer while the por and lvr circuits help prevent system problems, the watchdog timer helps the system recover when there is a problem. the watchdog timer works by resetting the system when there is a time-out. the micro- controller continually resets the timer, as part of the software loop, before the timer times-out. if there is ever a software problem, such as an in?ite loop or an opera- tion that waits for a peripheral device, the watchdog timer expires and resets the microcontroller. hardware implementation the circuit shown in fig. 1 includes both a manual and x5043 controlled reset. r1 serves as a pull-up resistor for the x5043 open-drain (i.e. active low) reset output. the 2n7000 n-mosfet is used to invert the active low reset, to directly control the 8031 rst pin. the circuit shown in fig. 2 has both a manual and x5045 controlled reset. the circuit in figure 2 is preferable because the x24045 has the correct reset polarity for the 8051. software implementation the following routines are included for implementing an interface to the x5043/x5045: wren_cmd ?this routine sets the write enable latch, which must be set before writing to either the eeprom memory array or the status register. the wel bit is auto- matically reset after a write operation. wrdi_cmd ?this command resets the write enable latch. wrsr_cmd ?this operation writes the watchdog timeout period bits (wd0, wd1) and the block protect bits (bp0, bp1) in the status register. rdsr_cmd ?this routine reads the status register. byte_write ?this command writes a single byte to the eeprom memory array. byte_read ?this command reads a single byte from the eeprom memory array. page_write ?this operation writes 3 consecutive bytes to the eeprom memory array. it can easily be modi?d to write an entire page (maximum of 16 bytes). sequ_read ?this routine reads three consecutive bytes from the eeprom memory array. it can be easily modi?d to read any number of bytes. rst_wdog ?this routine is used to reset the watchdog timer without sending a command.
2 of 10 application note www.xicor.com figure 1. connecting an x5043 to an 8051 microcontroller, with manual reset control figure 2. connecting an x5045 to an 8051 microcontroller, with manual reset control p0.0 p0.1 p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 p2.0 p2.1 p2.2 p2.3 p2.4 p2.5 p2.6 p2.7 rd wr psen ale/p txd rxd ea/vp x1 x2 reset int0 int1 t0 t1 p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 p1.6 p1.7 31 19 18 9 12 13 14 15 1 2 3 4 5 6 7 8 so si sck cs reset wp vcc sw1 r2 10k m1 r1 10k vcc x5043 u1 u2 8051 3 7 vcc c1 1uf 2 5 6 1 39 38 37 36 35 34 33 32 21 22 23 24 25 26 27 28 17 16 29 30 11 10 p0.0 p0.1 p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 p2.0 p2.1 p2.2 p2.3 p2.4 p2.5 p2.6 p2.7 rd wr psen ale/p txd rxd ea/vp x1 x2 reset int0 int1 t0 t1 p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 p1.6 p1.7 31 19 18 9 12 13 14 15 1 2 3 4 5 6 7 8 so si sck cs reset wp vcc sw1 r1 10k vcc x5043 u1 u2 8051 3 7 vcc 2 5 6 1 39 38 37 36 35 34 33 32 21 22 23 24 25 26 27 28 17 16 29 30 11 10
3 of 10 application note www.xicor.com $ title(x5043/8031/1.0) ;******************************************************************************************** ;*copyright (c) 1994 xicor, inc. ;*author: richard downing ;******************************************************************************************** ;* the purpose of this code is to provide routines to interface the xicor x5043 with the 8031 ;* microcontroller. the interface uses the 8031's general purpose parallel port 1 and connects ;* p1.0 to the chip select line (/cs), p1.1 to the serial input data line (si), p1.2 to the ;* serial clock line (sck) and p1.3 to the serial output data line (so). ;* ;* all x5043 commands are provided. these are :- ;* ;* 1. set write enable latch ;* 2. reset write enable latch ;* 3. write status register ;* 4. read status register ;* 5. single byte write ;* 6. single byte read ;* 7. page write ;* 8. sequential read ;* 9. reset watchdog timer ;* ;* the code writes 00h to the status register; reads the status register; writes 11h to ;* address 55h in byte mode; performs a single byte read from address 55h; writes 22h, ;* 33h, 44h to addresses 1f0h, 1f1h, 1f2h in page mode; performs a sequential read ;* from addresses 1f0h, 1f1h, 1f2h; and resets watchdog timer. this code can also be used with ;* the x5045 which is identical to the x5043, except for its reset output polarity. ;******************************************************************************************** ;* constants cs bit p1.0 ; port 1 bit 0 used for chip select (/cs) si bit p1.1 ; port 1 bit 1 used for serial input (ci) sck bit p1.2 ; port 1 bit 2 used for serial clock (sck) so bit p1.3 ; port 1 bit 3 used for serial output (so) wren_inst equ 06h ; write enable latch instruction (wren) wrdi_inst equ 04h ; write disable latch instruction (wrdi) wrsr_inst equ 01h ; write status register instruction (wrsr) rdsr_inst equ 05h ; read status register instruction (rdsr) write_inst equ 02h ; write memory instruction (write) read_inst equ 03h ; read memory instruction (read) byte_addr equ 55h ; memory address for byte mode operations byte_data equ 11h ; data byte for byte write operation page_addr equ 1f0h ; memory address for page mode operations page_data1 equ 22h ; 1st data byte for page write operation page_data2 equ 33h ; 2nd data byte for page write operation page_data3 equ 44h ; 3rd data byte for page write operation status_reg equ 00h ; status register max_poll equ 99h ; maximum number of polls init_state equ 09h ; initialization value for control ports user equ 030h ; address location of user code
4 of 10 application note www.xicor.com ;******************************************************************************************** ;* internal ram stack_top equ 060h; stack top ;******************************************************************************************** ;* code org 0000h ; reset vectors to this location ljmp main org 0100h main: mov sp, #stack_top ; initialize stack pointer clr ea ; disable interupts mov p1, #init_state ; init control lines (/cs & so =1, sck & si =0) lcall wren_cmd ; set write enable latch lcall wrsr_cmd ; write 00h to status register lcall wren_cmd ; set write enable latch lcall byte_write ; write 11h to address 55h (byte write) lcall byte_read ; read from address location 55h (byte read) lcall wren_cmd ; set write enable latch lcall page_write ; page write 22h/33h/44h to addresses 1f0/1/2h lcall sequ_read ; seq. read from address locations 1f0/1/2h lcall rst_wdog ; reset watchdog timer jmp user ;******************************************************************************************** ;* name: wren_cmd ;* description: set write enable latch ;* function: this routine sends the command to enable writes to the eeprom memory array or ;* status register ;* calls: outbyt ;* input: none ;* outputs: none ;* register usage: a ;******************************************************************************************** wren_cmd: clr sck ; bring sck low clr cs ; bring /cs low mov a, #wren_inst lcall outbyt ; send wren instruction clr sck ; bring sck low setb cs ; bring /cs high ret
5 of 10 application note www.xicor.com ;******************************************************************************************** ;* name: wrdi_cmd ;* description: reset write enable latch ;* function: this routine sends the command to disable writes to the eeprom memory array or ;* status register ;* calls: outbyt ;* input: none ;* outputs: none ;* register usage: a ;******************************************************************************************** wrdi_cmd: clr sck ; bring sck low clr cs ; bring /cs low mov a, #wrdi_inst lcall outbyt ; send wrdi instruction clr sck ; bring sck low setb cs ; bring /cs high ret ;******************************************************************************************** ;* name: wrsr_cmd ;* description: write status register ;* function: this routine sends the command to write the wd0, wd1, bp0 and bp0 eeprom ;* bits in the status register ;* calls: outbyt, wip_poll ;* input: none ;* outputs: none ;* register usage: a ;******************************************************************************************** wrsr_cmd: clr sck ; bring sck low clr cs ; bring /cs low mov a, #wrsr_inst lcall outbyt ; send wrsr instruction mov a, #status_reg lcall outbyt ; send status register clr sck ; bring sck low setb cs ; bring /cs high lcall wip_poll ; poll for completion of write cycle ret ;******************************************************************************************** ;* name: rdsr_cmd ;* description: read status register ;* function: this routine sends the command to read the status register ;* calls: outbyt, inbyt ;* input: none ;* outputs: a = status register ;* register usage: a ;******************************************************************************************** rdsr_cmd: clr sck ; bring sck low clr cs ; bring /cs low
6 of 10 application note www.xicor.com mov a, #rdsr_inst lcall outbyt ; send rdsr instruction lcall inbyt ; read status register clr sck ; bring sck low setb cs ; bring /cs high ret ;******************************************************************************************** ;* name: byte_write ;* description: single byte write ;* function: this routine sends the command to write a single byte to the eeprom memory array ;* calls: outbyt, wip_poll ;* input: none ;* outputs: none ;* register usage: a, b ;******************************************************************************************** byte_write: mov dptr, #byte_addr ; set address of byte to be written clr sck ; bring sck low clr cs ; bring /cs low mov a, #write_inst mov b, dph mov c, b.0 mov acc.3, c lcall outbyt ; send write instruction including msb of address mov a, dpl lcall outbyt ; send 8 lsbs of address mov a, #byte_data lcall outbyt ; send data byte clr sck ; bring sck low setb cs ; bring /cs high lcall wip_poll ; poll for completion of write cycle ret ;******************************************************************************************** ;* name: byte_read ;* description: single byte read ;* function: this routine sends the command to read a single byte from the eeprom memory array ;* calls: outbyt, inbyt ;* input: none ;* outputs: a = read byte ;* register usage: a, b ;******************************************************************************************** byte_read: mov dptr, #byte_addr ; set address of byte to be read clr sck ; bring sck low clr cs ; bring /cs low mov a, #read_inst mov b, dph mov c, b.0 mov acc.3, c lcall outbyt ; send read instruction including msb of address mov a, dpl
7 of 10 application note www.xicor.com lcall outbyt ; send 8 lsbs of address lcall inbyt ; read data byte clr sck ; bring sck low setb cs ; bring /cs high ret ;******************************************************************************************** ;* name: page_write ;* description: page write ;* function: this routine sends the command to write three consecutive bytes to the eeprom ;* memory array using page mode ;* calls: outbyt, wip_poll ;* input: none ;* outputs: none ;* register usage: a, b ;******************************************************************************************** page_write: mov dptr, #page_addr ; set address of 1st byte to be written clr sck ; bring sck low clr cs ; bring /cs low mov a, #write_inst mov b, dph mov c, b.0 mov acc.3, c lcall outbyt ; send write instruction including msb of address mov a, dpl lcall outbyt ; send 8 lsbs of address mov a, #page_data1 lcall outbyt ; send 1st data byte mov a, #page_data2 lcall outbyt ; send 2nd data byte mov a, #page_data3 lcall outbyt ; send 3rd data byte clr sck ; bring sck low setb cs ; bring /cs high lcall wip_poll ; poll for completion of write cycle ret ;******************************************************************************************** ;* name: sequ_read ;* description: sequential read ;* function: this routine sends the command to read three consecutive bytes from the eeprom ;* memory array using sequential mode ;* calls: outbyt, inbyt ;* input: none ;* outputs: a = last byte read ;* register usage: a, b ;******************************************************************************************** sequ_read: mov dptr, #page_addr ; set address of 1st byte to be read clr sck ; bring sck low clr cs ; bring /cs low mov a, #read_inst
8 of 10 application note www.xicor.com mov b, dph mov c, b.0 mov acc.3, c lcall outbyt ; send read instruction with msb of address mov a, dpl lcall outbyt ; send low order address byte lcall inbyt ; read 1st data byte lcall inbyt ; read 2nd data byte lcall inbyt ; read 3rd data byte clr sck ; bring sck low setb cs ; bring /cs high ret ;******************************************************************************************** ;* name: rst_wdog ;* description: reset watchdog timer ;* function: this routine resets the watchdog timer without sending a command ;* calls: none ;* input: none ;* outputs: none ;* register usage: none ;******************************************************************************************** rst_wdog: clr cs ; bring /cs low to reset watchdog timer setb cs ; bring /cs high ret ;******************************************************************************************** ;* name: wip_poll ;* description: write-in-progress polling ;* function: this routine polls for completion of a nonvolatile write cycle by examining the ;* wip bit of the status register ;* calls: rdsr_cmd ;* input: none ;* outputs: none ;* register usage: r1, a ;******************************************************************************************** wip_poll: mov r1, #max_poll ; set maximum number of polls wip_poll1: lcall rdsr_cmd ; read status register jnb acc.0, wip_poll2 ; if wip bit '0' write cycle completed djnz r1, wip_poll1 ; if wip bit '1' continue polling wip_poll2: ret
9 of 10 application note www.xicor.com ;******************************************************************************************** ;* name: outbyt ;* description: sends byte to eeprom ;* function: this routine shifts out a byte, starting with the msb, to the eeprom ;* calls: none ;* input: a = byte to be sent ;* outputs: none ;* register usage: r0, a ;******************************************************************************************** outbyt: mov r0, #08 ; set bit counter to eight outbyt1: clr sck ; bring sck low rlc a ; shift byte left through carry mov si, c ; send data bit in carry setb sck ; bring sck high djnz r0, outbyt1 ; finish if last data bit clr si ; place si in known condition ret ;******************************************************************************************** ;* name: inbyt ;* description: recieves byte from eeprom ;* function: this routine recieves a byte, msb first, from the eeprom ;* calls: none ;* input: none ;* outputs: a = recieved byte ;* register usage: r0, a ;******************************************************************************************** inbyt: mov r0, #08 ; set bit counter to eight inbyt1: setb sck ; bring sck high clr sck ; bring sck low mov c, so ; receive data bit and store in carry rlc a ; shift byte left through carry djnz r0, inbyt1 ; finish if last data bit ret end
10 of 10 application note www.xicor.com xicor, inc., the xicor logo, xdcp, xbga, autostore, direct write cell, concurrent read-write, pass, mps, pushpot, block lock, i dentiprom, e2key, x24c16, secureflash, and serialflash are all trademarks or registered trademarks of xicor, inc. all other brand and product names menti oned herein are used for identi?ation purposes only, and are trademarks or registered trademarks of their respective holders. xicor incor p orated, 1511 bucke y e drive, mil p itas, california 95035-7493
|
