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gl9711 pci express tm pipe x1 phy datasheet revision 1.10 jul. 04, 2006 genesys logic, inc.
gl9711 pci express tm pipe x1 phy ? 2000-2006 genesys logic inc. - all rights reserved. page 2 copyright: copyright ? 2006 genesys logic incorporated. all rights reserved. no part of the materials may be reproduced in any form or by any means without prior written consent of genesys logic inc.. disclaimer: all materials are provided "as is" without express or implied warranty of any kind. no license or right is granted under any patent or trademark of genesys logic inc.. genesys logic hereby disclaims all warranties and conditions in regard to materials, including all warranties, implied or express, of merchantability, fitness for any particular purpose, and non-infringement of intellectual property. in no event shall genesys logic be liable for any damages including, without limitation, damages resulting from loss of information or profits. please be advised that the materials may contain errors or ommisions. genesys logic may make changes to the materials or to the products described therein at any time without notice. trademarks: is a registered trademark of genesys logic, inc. all trademarks are the properties of their respective owners. office: genesys logic, inc. 12f, no. 205, sec. 3, beishin rd., shindian city, taipei, taiwan tel: (886-2) 8913-1888 fax: (886-2) 6629-6168 http://www.genesyslogic.com
gl9711 pci express tm pipe x1 phy ? 2000-2006 genesys logic inc. - all rights reserved. page 3 revision history revision date description 0.95 7/11/2005 preliminary release 0.96 7/27/2005 1. modify table3.1 C ball out, p.11 2. modify pipe interface and other signals , table3.4 C pin descriptions, p.15~p.17 3. modify ch4.2 registers descriptions, p.19 4. modify ch6.10 operation mode and multi-functional pins, p.28 5. modify table6.1-pin functions, p.28~p.30 6. modify table8.1~8.5, p.36~p.37 0.97 09/20/2005 modify package dimension,ch9 , p.40 0.98 11/15/2005 1. add bottom view , figures.3.1, p.10 2. update table3.4, p.15~p.18 3. update table3.5, p.18 4. modify the default value of reg0 and reg1, table4.1, p.19 5. modify ch4.2 registers descriptions for reg0 and reg1, p.20 6. add ch 4.3, p.22~p.25 7. update table 7.5 for power consumption, p.35 8. change txdx to rxdx, figure 8.4, p.39 9. the minimum and maximum value of t cycle, table8.2 and table 8.5, p.40 1.00 12/15/2005 1. update table 7.8 for temperature ranges (p.37) 2. update table 8.1~8.4 for output delay of rx bus (p.39~p.40) 1.01 04/13/2006 1. modify the description of osc25mi and osc25mo signals, table 3.4, p.15 2. swap the pin out of osc25mi and osc25mo in table 3.1~table 3.4. 3. update table 7.1 for deleting i dd1-x4 , i dd2-x4 , i dd3-x4 , i dd1-x2 , i dd2-x2 , and i dd3-x2 six items, p.34 4. update table 7.8 for deleting the i supply-1.8 item and adding ja , jt and jc three items, p.37 1.02 04/26/2006 divide table 7.8 into table 7.8(temperature range) and table 7.9(thermal characteristics), p.37 1.10 07/04/2006 1. update table 3.5 for the parameter of buffer i/o, p.18 2. remove table 7.2, p.34 3. update fig. 8.1, 8.2 and table 8.1~8.5 for pipe input and output timing characteristic, p.38~p.40
gl9711 pci express tm pipe x1 phy ? 2000-2006 genesys logic inc. - all rights reserved. page 4 table of contents chapter 1 general description.................................................8 chapter 2 features...........................................................................9 chapter 3 pin assignment............................................................10 3.1 p inout ..................................................................................................10 3.2 b all o ut .............................................................................................10 3.3 p in l ist ................................................................................................11 3.4 p in d escriptions ................................................................................15 chapter 4 registers........................................................................19 4.1 r egisters b ase a ddress ...................................................................19 4.2 r egisters d escriptions ....................................................................20 4.3 smb us p rotocal ...............................................................................22 chapter 5 block diagram............................................................26 5.1 s implified d iagram ...........................................................................26 5.2 t ransmitter d ata p ath p er l ane ..................................................27 5.3 r eceiver d ata p ath p er l ane .........................................................28 chapter 6 function description.............................................29 6.1 c lock and r eset ................................................................................29 6.2 r eceiver d etection ..........................................................................29 6.3 b eacon t ransmitting and d etection ............................................29 6.4 r eceiver s tatus r eport ..................................................................29 6.5 l oopback ............................................................................................30 6.6 p olarity i nversion ...........................................................................30 6.7 s etting n egative d isparity ............................................................30 6.8 b ehavior s ummary ............................................................................31 6.9 p ower s aving s upport ......................................................................31 6.10 o peration m ode and m ulti -f unctional p ins ............................32 chapter 7 electrical characteristics..............................34 7.1 dc v oltage s pecifications .............................................................34
gl9711 pci express tm pipe x1 phy ? 2000-2006 genesys logic inc. - all rights reserved. page 5 7.2 t ransmit and r eceive l atency t ime .............................................34 7.3 t ransition t ime of p ower s tate ....................................................34 7.4 p ower c onsumption ..........................................................................35 7.5 d ifferential t ransmitter and r eceiver s erial o utput ...........35 7.6 r ecommended o perating c onditions ...........................................37 chapter 8 pipe timing characteristics..............................38 8.1 i nput s etup , h old t ime and o utput t iming ..................................38 8.2 r eference t iming i nformation ......................................................40 chapter 9 package dimension...................................................41 chapter 10 ordering information.........................................42
gl9711 pci express tm pipe x1 phy ? 2000-2006 genesys logic inc. - all rights reserved. page 6 list of figures f igure 3.1 - 233 p in lfbga p inout d iagram ..........................................................10 f igure 4.1 C smb us t opology of gl9711................................................................22 f igure 4.2 C d ata v alidity ........................................................................................23 f igure 4.3 C start and stop c ondition ...............................................................23 f igure 4.4 C ack and nack s ignaling of smb us .................................................24 f igure 4.5 C smb us p acket p rotocol d iagram e lement k ey ............................24 f igure 4.6 C w rite b yte p rotocol ..........................................................................25 f igure 4.7 C r ead b yte p rotocol ............................................................................25 f igure 4.8 C t he m inimum w ait t ime from p ower on to p rogramming r egisters .....................................................................................................................25 f igure 5.1 - s implified d iagram ...............................................................................26 f igure 5.2 - t ransmitter d ata p ath per l ane .......................................................27 f igure 5.3 - r eceiver d ata p ath per l ane .............................................................28 f igure 8.1 C d efinition of i nput s etup and h old t ime ..........................................38 f igure 8.2 C d efinition of o utput t iming ..............................................................39 f igure 9.1 - gl9711 233 p in lfbga p ackage ..........................................................41
gl9711 pci express tm pipe x1 phy ? 2000-2006 genesys logic inc. - all rights reserved. page 7 list of tables t able 3.1 - b all o ut ...................................................................................................10 t able 3.2 - n umeric p in l ist ......................................................................................11 t able 3.3 - a lphabetic p in l ist ................................................................................13 t able 3.4 - p in d escriptions ......................................................................................15 t able 3.5 - p arameter of b uffer i/o.......................................................................18 t able 4.1 - b ase a ddress for r egisters ..................................................................19 t able 6.1 - p in f unctions ...........................................................................................32 t able 7.1 - dc v oltage s pecifications ...................................................................34 t able 7.2 - t ransmit and r eceive l atency t ime ...................................................34 t able 7.3 C t ransition t ime of p ower s tate .........................................................34 t able 7.4 - p ower c onsumption of e ach p ower s tate in d ifferent o peration m ode .............................................................................................................................35 t able 7.5 C t ransmitter s erial o utput .................................................................35 t able 7.6 C r eceiver s erial o utput ........................................................................36 t able 7.7 C t emperature r ange ...............................................................................36 t able 7.8 C t hermal c haracteristics ....................................................................36 t able 8.1 C i nput s etup , h old t ime and o utput t iming for 8- bit sdr m ode ...39 t able 8.2 C i nput s etup , h old t ime and o utput t iming for 8- bit ddr m ode ...40 t able 8.3 C i nput s etup , h old t ime and o utput t iming for 16- bit m ode ..........40 t able 8.4 C i nput s etup , h old t ime and o utput t iming for 10- bit sdr m ode .40 t able 8.5 C i nput s etup , h old t ime and o utput t iming for 10- bit ddr m ode .40 t able 8.6 C r eference t iming i nformation ...........................................................40 t able 10.1 - o rdering i nformation .........................................................................42
gl9711 pci express tm pipe x1 phy ? 2000-2006 genesys logic inc. - all rights reserved. page 8 chapter 1 general description the gl9711 is a 1-lane pci express phy layer controller, which is compliant with pci express base specification rev. 1.0a and intel s phy interface for the pci express architecture rev. 1.0. it integrates one serdes and the physical coding sublayer (pcs) which performs 8b/10b encoding and decoding, elastic buffer and receiver detection, data serialization and deserialization. the serdes in the gl9711 supports an effective serial interface speed (2.5 gb/s) of data bandwidth, intended for use in ultrahigh-speed bi-directional data transmission system. the gl9711 can also be externally configured for various parallel bus width which is flexible and suitable for implementation. it also supports four operational states for power management to minimize power consumption. for production and self-test purposes, the gl9711 provides bist and an internal loopback capability. the primary application of this chip is to provide very high-speed i/o data channels for point-to-point baseband data transmission over an on-chip termination resister of 50 ohm +/- 10%. this device can also be used to replace parallel data transmission architectures by providing a reduction in the number of traces, connector pins, and transmit/receive pins. parallel data loaded into the transmitter is delivered to the receiver over a serial channel. it is then reconstructed into its original parallel format. the maximum data transfer rate in each direction is 256m bytes per second. it also offers various power saving modes to significantly reduce power consumption as well as scalability for a higher data rate in the future.
gl9711 pci express tm pipe x1 phy ? 2000-2006 genesys logic inc. - all rights reserved. page 9 chapter 2 features l complies with pci express base specification rev. 1.0a l complies with intel s phy interface for pci express architecture rev. 1.0 l integrates 2.5 gigabit per second (gpbs) serializer/deserializer l supports 8-bit or 10-bit parallel interface @250mhz l supports 16-bit parallel interface @125mhz l supports ddr configuration for 8-bit or 10-bit mode l beacon transmission and reception l receiver detection l transmission and detection of electrical idle l clock tolerance for 600 ppm in frequencies between bit rates at the two end of a link l on-chip 8-bit/10-bit encoding/decoding and comma alignment l on-chip pll provides clock synthesis l 1.8-v power supply for core l 2.5-v power supply for io l above 2.0 kv esd protection l 0.18 m m process l available in lfbga-233 package
gl9711 pci express tm pipe x1 phy ? 2000-2006 genesys logic inc. - all rights reserved. page 10 chapter 3 pin assignment 3.1 pinout a b c d e f g h j k l n p r m t u 1716151413121110 9 8 7 6 5 4 3 2 1 bottom view figure 3.1 - 233 pin lfbga pinout diagram 3.2 ball out table 3.1 - ball out 1 2 3 4 5 6 7 8 9 a refclkp nc vddtx nc vddrx nc vddtx nc vddrx b refclkn nc vsstx nc vssrx nc vsstx nc vssrx c osc25mo nc nc vdd18 nc nc vsstx vddpll nc d osc25mi vdd25 nc vss vss nc vdd18 rterm vsspll e nc nc nc nc f vss nc nc nc g nc vdd25 nc nc vss vss vss h nc nc nc nc vss vss vss j nc vss nc nc vss vss vss k vdd25 nc nc vdd12 vss vss vss l vss vss nc vdd18 vss vss vss m vss nc vdd18 nc n nc vss nc nc p vdd25 nc nc nc nc nc nc nc vss
gl9711 pci express tm pipe x1 phy ? 2000-2006 genesys logic inc. - all rights reserved. page 11 r nc nc nc nc nc nc vss nc opmode0 t nc vdd25 nc nc vdd25 vdd18 nc nc nc u vss nc vss nc physts nc nc nc vdd25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 a txn vddtx rxn vddrx nc vddtx nc vddrx b txp vsstx rxp vssrx nc vsstx nc vssrx c vdd18 nc vdd18 nc txd9 vssgr txd14 txd15 d nc nc nc txd8 txd11 txd12 vdd25 nc e txd13 txdk1 txd10 rxdk1 f nc nc rxd8 vdd25 g vss vss nc rxd9 rxd10 rxd12 h vss vss rxd13 rxd11 rxd15 vdd18 j vss vss vdd12 vss rxd14 vdd18 k vss vss txd2 vdd25 txdk0 nc l vss vss txcmp txd6 txd1 txd0 m rxsts1 txd4 txd3 vss n rxd3 rxdk0 txd7 txd5 p pd1 rxvld nc rxd7 rxd5 rxd1 vss rxsts0 r scc txdet/ lpbk txidle vdd25 nc rxd4 rxd0 vdd25 t testd pd0 rxidle nc pclk vss rxd2 rxsts2 u opmode1 testc rst_n rxplr vss nc rxd6 vdd25 10 11 12 13 14 15 16 17 3.3 pin list table 3.2 - numeric pin list pin# pin name pin# pin name pin# pin name pin# pin name pin# pin name a1 refclkp c1 osc25mo e1 nc g1 nc j1 nc a2 nc c2 nc e2 nc g2 vdd25 j2 vss a3 vddtx c3 nc e3 nc g3 nc j3 nc a4 nc c4 vdd18 e4 nc g4 nc j4 nc a5 vddrx c5 nc e5 g5 j5 a6 nc c6 nc e6 g6 j6 a7 vddtx c7 vsstx e7 g7 vss j7 vss a8 nc c8 vddpll e8 g8 vss j8 vss a9 vddrx c9 nc e9 g9 vss j9 vss a10 txn c10 vdd18 e10 g10 vss j10 vss a11 vddtx c11 nc e11 g11 vss j11 vss a12 rxn c12 vdd18 e12 g12 j12
gl9711 pci express tm pipe x1 phy ? 2000-2006 genesys logic inc. - all rights reserved. page 12 a13 vddrx c13 nc e13 g13 j13 a14 nc c14 txd9 e14 txd13 g14 nc j14 vdd12 a15 vddtx c15 vssgr e15 txdk1 g15 rxd9 j15 vss a16 nc c16 txd14 e16 txd10 g16 rxd10 j16 rxd14 a17 vddrx c17 txd15 e17 rxdk1 g17 rxd12 j17 vdd18 b1 refclkn d1 osc25mi f1 vss h1 nc k1 vdd25 b2 nc d2 vdd25 f2 nc h2 nc k2 nc b3 vsstx d3 nc f3 nc h3 nc k3 nc b4 nc d4 vss f4 nc h4 nc k4 vdd12 b5 vssrx d5 vss f5 h5 k5 b6 nc d6 nc f6 h6 k6 b7 vsstx d7 vdd18 f7 h7 vss k7 vss b8 nc d8 rterm f8 h8 vss k8 vss b9 vssrx d9 vsspll f9 h9 vss k9 vss b10 txp d10 nc f10 h10 vss k10 vss b11 vsstx d11 nc f11 h11 vss k11 vss b12 rxp d12 nc f12 h12 k12 b13 vssrx d13 txd8 f13 h13 k13 b14 nc d14 txd11 f14 nc h14 rxd13 k14 txd2 b15 vsstx d15 txd12 f15 nc h15 rxd11 k15 vdd25 b16 nc d16 vdd25 f16 rxd8 h16 rxd15 k16 txdk0 b17 vssrx d17 nc f17 vdd25 h17 vdd18 k17 nc pin# pin name pin# pin name pin# pin name pin# pin name l1 vss n1 nc r1 nc u1 vss l2 vss n2 vss r2 nc u2 nc l3 nc n3 nc r3 nc u3 vss l4 vdd18 n4 nc r4 nc u4 nc l5 n5 r5 nc u5 physts l6 n6 r6 nc u6 nc l7 vss n7 r7 vss u7 nc l8 vss n8 r8 nc u8 nc l9 vss n9 r9 opmode0 u9 vdd25 l10 vss n10 r10 scc u10 opmode1 l11 vss n11 r11 txdet/lpbk u11 testc l12 n12 r12 txidle u12 rst_n l13 n13 r13 vdd25 u13 rxplr l14 txcmp n14 rxd3 r14 nc u14 vss
gl9711 pci express tm pipe x1 phy ? 2000-2006 genesys logic inc. - all rights reserved. page 13 l15 txd6 n15 rxdk0 r15 rxd4 u15 nc l16 txd1 n16 txd7 r16 rxd0 u16 rxd6 l17 txd0 n17 txd5 r17 vdd25 u17 vdd25 m1 vss p1 vdd25 t1 nc m2 nc p2 nc t2 vdd25 m3 vdd18 p3 nc t3 nc m4 nc p4 nc t4 nc m5 p5 nc t5 vdd25 m6 p6 nc t6 vdd18 m7 p7 nc t7 nc m8 p8 nc t8 nc m9 p9 vss t9 nc m10 p10 pd1 t10 testd m11 p11 rxvld t11 pd0 m12 p12 nc t12 rxidle m13 p13 rxd7 t13 nc m14 rxsts1 p14 rxd5 t14 pclk m15 txd4 p15 rxd1 t15 vss m16 txd3 p16 vss t16 rxd2 m17 vss p17 rxsts0 t17 rxsts2 blank table 3.3 - alphabetic pin list pin name pin# pin name pin# pin name pin# pin name pin# pin name pin# nc c3 nc g4 nc f15 nc a6 vss h7 nc c5 nc e2 txcmp l14 nc a2 vss h8 nc c6 nc f3 nc r3 nc b14 vss h9 nc c9 nc d3 nc g1 txp b10 vss h10 nc c11 nc e3 txd8 d13 nc b6 vss h11 nc c13 nc e4 txd9 c14 nc b2 vss j2 nc d6 nc f4 txd10 e16 vdd12 j14 vss j7 nc d10 nc c2 txd11 d14 vdd12 k4 vss j8 nc d11 rxdk1 e17 txd12 d15 vdd18 c4 vss j9 nc d12 rxdk0 n15 txd13 e14 vdd18 c10 vss j10 nc k17 nc t1 txd14 c16 vdd18 c12 vss j11 opmode0 r9 nc e1 txd15 c17 vdd18 d7 vss j15 opmode1 u10 nc t13 txd0 l17 vdd18 h17 vss k7 osc25mo c1 rxidle t12 txd1 l16 vdd18 j17 vss k8 osc25mi d1 nc t8 txd2 k14 vdd18 l4 vss k9
gl9711 pci express tm pipe x1 phy ? 2000-2006 genesys logic inc. - all rights reserved. page 14 pclk t14 nc p8 txd3 m16 vdd18 m3 vss k10 pd0 t11 nc a16 txd4 m15 vdd18 t6 vss k11 pd1 p10 rxn a12 txd5 n17 vdd25 d2 vss l1 physts u5 nc a8 txd6 l15 vdd25 d16 vss l2 refclkn b1 nc a4 txd7 n16 vdd25 f17 vss l7 refclkp a1 nc b16 nc u4 vdd25 g2 vss l8 rst_n u12 rxp b12 nc r6 vdd25 k1 vss l9 rterm d8 nc b8 nc t4 vdd25 k15 vss l10 rxd8 f16 nc b4 nc p6 vdd25 p1 vss l11 rxd9 g15 nc u15 nc u2 vdd25 r13 vss m1 rxd10 g16 rxplr u13 nc r5 vdd25 r17 vss m17 rxd11 h15 nc t9 nc t3 vdd25 t2 vss n2 rxd12 g17 nc r8 nc r4 vdd25 t5 vss p9 rxd13 h14 nc f14 nc k2 vdd25 u9 vss p16 rxd14 j16 nc g14 nc k3 vdd25 u17 vss r7 rxd15 h16 nc d17 nc j1 vddpll c8 vss t15 rxd0 r16 rxsts0 p17 nc j4 vddrx a17 vss u1 rxd1 p15 rxsts1 m14 nc h1 vddrx a13 vss u3 rxd2 t16 rxsts2 t17 nc j3 vddrx a9 vss u14 rxd3 n14 nc p5 nc h2 vddrx a5 vssgr c15 rxd4 r15 nc r2 nc h3 vddtx a15 vsspll d9 rxd5 p14 nc p4 txdet/lpbk r11 vddtx a11 vssrx b17 rxd6 u16 nc h4 txdk1 e15 vddtx a7 vssrx b13 rxd7 p13 nc f2 txdk0 k16 vddtx a3 vssrx b9 nc n4 nc g3 nc p7 vss d4 vssrx b5 nc p2 nc p12 nc l3 vss d5 vsstx b15 nc p3 rxvld p11 nc r14 vss f1 vsstx b11 nc r1 nc u7 txidle r12 vss g7 vsstx b7 nc m4 nc u6 nc u8 vss g8 vsstx c7 nc n1 scc r10 nc t7 vss g9 vsstx b3 nc n3 testc u11 nc a14 vss g10 nc m2 testd t10 txn a10 vss g11
gl9711 pci express tm pipe x1 phy ? 2000-2006 genesys logic inc. - all rights reserved. page 15 3.4 pin descriptions table 3.4 - pin descriptions pipe interface pin name i/o standard pin# type description rst_n lvcmos2 u12 i global reset pclk sstl2_i t14 o parallel interface clock all data movement across the parallel interface is synchronous to this clock. 1. for 8-bit mode: pclk operates at 250 mhz and is applied to synchronize all txd, rxd data bus and all commands. 2. for 16-bit mode: pclk operates at 125 mhz and is applied to synchronize all txd, rxd data bus and all commands. 3. for 10-bit mode(tbc): pclk operates at 250 mhz and is applied to synchronize the txd data bus and all commands. rxsts[2:0] sstl2_i t17, m14, p17 o 1. for 8-bit and 16-bit modes: encodes receiver status and error codes for the received data stream and receiver detection 000 received data ok 001 1 skp added 010 1 skp removed 011 receiver detected 100 8b/10b decode error 101 elastic buffer overflow 110 elastic buffer underflow 111 receiver disparity error 2. for 10-bit modes: rxsts[2]: rbc, synchronize the rxd data bus rxsts[1]: rxprsnt, report the result of receiver detection rxsts[0]: rxd9, bit 9 of rxd data bus rxidle lvcmos2 t12 o indicates receiver detection of an electrical idle this is an asynchronous signal. physts sstl2_i u5 o used to communicate completion of several phy functions including power state transitions and receiver detection rxvld lvcmos2 p11 o indicates symbol lock and valid data on rxdx and rxdkx txcmp sstl2_i l14 i 1. for 8-bit and 16-bit modes: sets the running disparity to negative 2. for 10-bit mode: txd9, bit 9 of txd data bus txidle lvcmos2 r12 i forces tx output to electrical idle
gl9711 pci express tm pipe x1 phy ? 2000-2006 genesys logic inc. - all rights reserved. page 16 rxdk[1:0] sstl2_i e17, n15 o 1. for 8-bit and 16-bit modes: k-code indication for the received symbols in 8-bit mode, rxdk = rxdk0 in 16-bit mode, rxdk = {rxdk1, rxdk0} 2. for 10-bit mode: rxdk[0]: rxd8, bit 8 of rxd data bus rxd[15:0] sstl2_i h16, j16, h14, g17, h15, g16, g15, f16, p13, u16, p14, r15, n14, t16, p15, r16 o rxd[7:0]: parallel data output bus for all 8-bit, 16-bit and 10-bit modes rxd[15:0]: parallel data output bus for 16-bit mode only txdk[1:0] sstl2_i e15, k16 i 1. for 8-bit and 16-bit modes: k-code indication for the transmitted symbols in 8-bit mode, txdk = txdk0 in 16-bit mode, txdk = {txdk1, txdk0} 2. for 10-bit mode: txdk[0]: txd8, bit 8 of txd data bus txd[15:0] sstl2_i c17, c16, e14, d15, d14, e16, c14, d13, n16, l15, n17, m15, m16, k14, l16, l17 i txd[7:0]: parallel data input bus for all 8-bit, 16-bit and 10-bit modes txd[15:0]: parallel data input bus for 16-bit mode only txdet/lpbk lvcmos2 r11 i receiver detection/loopback pd[1:0] lvcmos2 p10, t11 i sets the power states 00 p0, normal operation 01 p0s, low recovery time latency, power saving state 10 p1, longer recovery time(64us max) latency, lower power state 11 p2, lowest power state rxplr lvcmos2 u13 i inverts the polarity on the rxp/rxn power and ground signals pin name pin# type description vdd25 d2, d16, f17, g2, k1, k15, p1, r13, r17, t2, t5, u9, u17 p 2.5v power supplies for general i/o vdd18 c4, c10, c12, d7, h17, j17, l4, m3, t6 p 1.8v power supplies for core and bias voltage vdd12 j14, k4 p 1.25v reference voltage for high speed i/o vss d4, d5, f1, g7, g8, g9, g10, g11, h7, h8, h9, h10, h11, j2, j7, j8, j9, j10, j11, j15, k7, k8, k9, k10, k11, l1, l2, l7, l8, l9, l10, l11, m1, m17, n2, p9, p16, r7, t15, u1, u3, u14 p digital ground vddpll c8 p 1.8v power supplies for internal pll vsspll d9 p ground for internal pll vddrx vssrx a17, a13, a9, a5 b17, b13 , b9, b5 p 1.8v power supplies for receiver part vddtx vsstx a15, a11, a7, a3 b15, b11, b7, c7, b3 p 1.8v power supplies for transceiver part
gl9711 pci express tm pipe x1 phy ? 2000-2006 genesys logic inc. - all rights reserved. page 17 vssgr c15 p ground for the guard ring of the serdes block serial signals pin name pin# type description rxn a12 i received serial input, complement rxp b12 i received serial input, true rterm d8 i connects an external 5.1k w resistor to ground for calibrating the on-chip termination resistors txn a10 o transmitted serial output, complement txp b10 o transmitted serial output, true other signals pin name i/o standard pin# type description refclkp analogue a1 i reference clock signal refclkn analogue b1 i reference clock signal osc25mo crystal c1 o connect to 25mhz crystal when using crystal as the reference clock source osc25mi crystal/ oscillator d1 i connect to 25mhz crystal/oscillator when using crystal/oscillator as the reference clock source testc/smc lvcmos2 u11 i test clock/smbus clock testd/smd lvcmos2 t10 i/o test data/smbus data scc lvcmos2 r10 i configures clock input source when scc=1, the chip clock sources from a pair of differential signals, refclkp and refclkn, with a nominal frequency of 100 mhz. when scc=0, the chip clock sources from a crystal at 25mhz. opmode[1:0] lvcmos2 u10, r9 i operational mode of the gl9711 00 8-bit mode 01 16-bit mode 10 10-bit mode 11 internal use only nc - a2, a4, a6, a8, a14, a16, b2, b4, b6, b8, b14, b16, c2, c3, c5, c6, c9, c11, c13, d3, d6, d10, d11, d12, d17, e1, e2, e3, e4, f2, f3, f4, f14, f15, g1, g3, g4, g14, h1, h2, h3, h4, j1, j3, j4, k2, k3, k17, l3, - no connection
gl9711 pci express tm pipe x1 phy ? 2000-2006 genesys logic inc. - all rights reserved. page 18 m2, m4, n1, n3, n4, p2, p3, p4, p5, p6, p7, p8, p12, r1, r2, r3, r4, r5, r6, r8, r14, t1, t3, t4, t7, t8, t9, t13, u2, u4, u6, u7, u8, u15 note: nc pins should be left open on circuit board. table 3.5 - parameter of buffer i/o v ih (input high voltage, v) v il (input low voltage, v) v oh (output high voltage, v) v ol (output low voltage, v) buffer type min norm max min norm max min norm max min norm max lvcmos2 1.7 - - - - 0.7 2.4 - - - - 0.4 sstl2 1.57 - - - - 0.93 1.76 - - - - 0.74
gl9711 pci express tm pipe x1 phy ? 2000-2006 genesys logic inc. - all rights reserved. page 19 chapter 4 registers there are some registers built-in the gl9711 for test purpose. these registers can be accessed through a serial bus interface using pin testc and testd. registers at offset 05h ~ 0bh are for internal test only. please be careful to leave them as default values. 4.1 registers base address table 4.1 - base address for registers mnemonic offset description default revid 00h revision id and auto-calibration result register 8 bxxxx1xxx xcvropt 01h transceiver option register 8 he9 lpbktest 02h bist and beacon/test data pattern register, part 1 8 h00 bcnpat2 03h beacon/test data pattern register, part 2 8 h03 bcnpat3 04h beacon/test data pattern register, part 3 8 hff - 05h for internal test only - - 06h for internal test only - - 07h for internal test only - - 08h for internal test only - - 09h for internal test only - - 0ah for internal test only - - 0bh for internal test only - bt 0ch buffer test register 8 h00 slcdt 0dh serial loopback and comma detect test register 8 h00 notation: r/w read / write r/o read only w/o write only r/w1c read / write 1 to clear r/w/c read / write and hardware automatic clear
gl9711 pci express tm pipe x1 phy ? 2000-2006 genesys logic inc. - all rights reserved. page 20 4.2 registers descriptions offset 00h C revid . default value = 8 bxxxx1xxx rev3 rev2 rev1 rev0 by1 rcal0 rcal1 rcal2 r r r r r r r r 7-4 rev[3:0] chip revision code 3 by1 x1 package 2-0 rcal[0:2] calibration result of on-chip termination resistors offset 01h C xcvropt .. . default value = 8 he9 sw1 sw0 dem1 dem0 bw0 bw1 rdef feval r/w r/w r/w r/w r/w r/w r/w r/w 7-6 sw[1:0] swing control of transmitter output output swing (differential, peak-to-peak) 00 0.6v 01 0.8v 10 1.0v 11 1.2v 5-4 dem[1:0] de-emphasis control of transmitter output amount of de-emphasis 00 no de-emphasis 01 -1.6db 10 -3.5db 11 -6.0db 3-2 bw[0:1] bandwidth control of clock recovery circuit relative bandwidth 00 1 01 2 10 4 11 reserved 1 rdef disable calibration of on-chip termination resistors and leave the resistors to their default value 0 feval force calibration of on-chip termination resistors when rdef =0, writing a one to this bit will make the resistors re-calibrated. this bit is auto-cleared and always read as zero.
gl9711 pci express tm pipe x1 phy ? 2000-2006 genesys logic inc. - all rights reserved. page 21 offset 02h C lpbktest .. . default value = 8 h00 bist0 bist1 bist2 -- bcn19 bcn18 bcn17 bcn16 r/w r/w r/w -- r/w r/w r/w r/w 7-5 bist[0:2] select of built-in test pattern bit pattern 00x bist disabled 100 0000000000 0000000000 010 1111111111 1111111111 110 0101010101 0101010101 101 0011111010 1010101010 1100000101 0101010101 011 0011111010 1010 0 * 01010 1100000101 0101 1 * 10101 111 prbs pattern it should be noted that the expected pattern while bist[0:2]=011 is the same as bist[0:2]=101. but when coming out of the transmitter, the two bits with * in bist[0:2]=011 are different from bist[0:2]=101. as a result, even when there is no bit error, there will be bit errors intentionally introduced to verify the bist circuit is functional. 4 reserved - 3-0 bcn[19:16] data pattern for beacon and txtest offset 03h C bcnpat2 . . default value = 8 h03 bcn15 bcn14 bcn13 bcn12 bcn11 bcn10 bcn9 bcn8 r/w r/w r/w r/w r/w r/w r/w r/w 7-0 bcn[15:8] data pattern for beacon and txtest offset 04h C bcnpat3 . . default value = 8 hff bcn7 bcn6 bcn5 bcn4 bcn3 bcn2 bcn1 bcn0 r/w r/w r/w r/w r/w r/w r/w r/w 7-0 bcn[7:0] data pattern for beacon and txtest offset 0ch C bt ... ... . default value = 8 h00 -- -- ddr ren txtest plpbk skpdel skpadd -- -- r/w r/w r/w r/w r/w r/w 7-6 reserved - 5 ddr enable ddr at pipe interface and make pclk = 125mhz @ 8/10-bit mode 4 ren enable terminator for refclkp/n 3 txtest enable transmitter test with data pattern bcn[19:0], which are programmed in reg02h, 03h and 04h 2 plpbk enable parallel loopback of pcs
gl9711 pci express tm pipe x1 phy ? 2000-2006 genesys logic inc. - all rights reserved. page 22 1 skpdel enable skp deleting test of skp ordered sets 0 skpadd enable skp adding test of skp ordered sets offset 0dh C slcdt ... ... . default value = 8 h00 -- slpbk -- -- -- fencd -- -- -- r/w -- -- -- r/w -- -- 7 reserved - 6 slpbk enable serial loopback 5-3 reserved - 2 fencd force comma detect 1-0 reserved - 4.3 smbus protocal gl9711 registers are programmed by system management bus (smbus). fig. 4.1 shows the smbus topology. the v dd power is 2.5v +/- 10% and the pull up resistor is 1k . both smbclk and smbdat lines are bi-directional, connected to 2.5v supply voltage through a pull-up resistor. the operating frequency is 10~100khz and the smbus address of gl9711 is 7 h2c. figure 4.1 C smbus topology of gl9711
gl9711 pci express tm pipe x1 phy ? 2000-2006 genesys logic inc. - all rights reserved. page 23 smbus uses fixed voltage levels to define the logic zero and logic one on the bus respectively. the data on smbdat must be stable during the high period of the clock. data can change state only when smbclk is low. fig. 4.2 illustrates the relationships. figure 4.2 C data validity two unique bus situations define a message start and stop condition. 1. a high to low transition of the smbdat line while smbclk is high indicates a message start condition. 2. a low to high transition of the smbdat line while smbclk is high defines a message stop condition. figure 4.3 C start and stop condition
gl9711 pci express tm pipe x1 phy ? 2000-2006 genesys logic inc. - all rights reserved. page 24 every byte consists of 8 bits. each byte transferred on the bus must be followed by an acknowledge bit. bytes are transferred with the most significant bit (msb) first. fig. 4.4 illustrates the positioning of acknowledge (ack) and not acknowledge (nack) pulses relative to other data. figure 4.4 C ack and nack signaling of smbus below is a key to the protocol diagrams. s start condition sr repeated start condition rd read (bit value of 1) wr write (bit value of 0) x shown under a field indicates that that ` field is required to have the value of x a acknowledge (this bit position may be 0 for an ack or 1 for a nack) p stop condition master-to-gl9711 gl9711-to-master figure 4.5 C smbus packet protocol diagram element key
gl9711 pci express tm pipe x1 phy ? 2000-2006 genesys logic inc. - all rights reserved. page 25 the first byte of a write byte access is the command code. the next one byte is the data to be written. in this example the master asserts gl9711 s address followed by the write bit. gl9711 acknowledges and the master delivers the command code. gl9711 again acknowledges before the master sends the data byte. gl9711 acknowledges the data byte, and the entire transaction is finished with a stop condition. figure 4.6 C write byte protocol reading data is slightly more complicated than writing data. first the host must write a command to gl9711. then it must follow that command with a repeated start condition to denote a read from gl9711 s address. gl9711 then returns one byte of data. note that there is no stop condition before the repeated start condition, and that a nack signified the end of the read transfer. figure 4.7 C read byte protocol gl9711 requires a minimum time (16us) to reach the steady state after power on. so the master must start programming at least 16us later after power on. figure 4.8 C the minimum wait time from power on to programming registers
gl9711 pci express tm pipe x1 phy ? 2000-2006 genesys logic inc. - all rights reserved. page 26 chapter 5 block diagram 5.1 simplified diagram figure 5.1 - simplified diagram
gl9711 pci express tm pipe x1 phy ? 2000-2006 genesys logic inc. - all rights reserved. page 27 5.2 transmitter data path per lane data x16 or x8 optional 16, 8-bit x8 8b 10b encoding x10 parallel to serial conversion transmitter differential driver txp txn txidle txdet/lpbk pclk 250 mhz txcmp txdk0,txdk1 2.5 ghz from pll loopback path from receiver figure 5.2 - transmitter data path per lane
gl9711 pci express tm pipe x1 phy ? 2000-2006 genesys logic inc. - all rights reserved. page 28 5.3 receiver data path per lane differential recieiver data recovery circuit (drc) serial to paralle elastic buffer loopback path to transmitter rxn rxp rxidle clock recovery circuit 2.5 ghz k28.5 detection rxvld rxplr receiver status rxsts x10 x10 8b 10b decoder x8 optional 8, 16-bit data x16 or x8 rxdk recovered symbol clock buffer overflow/underflow skp added/removed decode error disparity error 250 mhz pcl figure 5.3 - receiver data path per lane
gl9711 pci express tm pipe x1 phy ? 2000-2006 genesys logic inc. - all rights reserved. page 29 chapter 6 function description 6.1 clock and reset the clock source of the gl9711 comes externally from either the 100 mhz differential clock pair or the 25mhz crystal, which is selectable by pin scc. the gl9711 uses the clock source with its pll to generate the 2.5 ghz bit rate for transmitting and receiving. the gl9711 also drives a clock output for the synchronization of mac interface. since the mac interface can be configured to 8-bit, 16-bit and 10-bit mode, the clock, pclk, runs at 250 mhz for 8-bit mode and 125 mhz for 16-bit mode. the mac should use the rising edge of the clock to send and receive parallel data. to initialize the gl9711, the mac should assert the reset of the gl9711 to low. while the reset is asserted, the mac should also make txdet/lpbk deasserted, txidle asserted, txcmp deasserted, rxplr deasserted and pd[1:0] = p1. when the gl9711 senses its reset asserted, it will drive its physts high immediately. after the reset deasserted, the gl9711 requires typically 16.7us for internal pll stable and then transitions its physts to low. when mac deasserts the reset, it should monitor the state of physts to make sure the gl9711 is ready for normal operation. 6.2 receiver detection the receiver detection can only be performed while the gl9711 is in p1 state. to instruct the gl9711 to enter a receiver detection sequence, the mac asserts txdet/lpbk and hold it asserted until the gl9711 asserts physts for response. while finishing the receiver detection, the gl9711 will assert physts and present a appropriate value to rxsts[2:0] to signal a detection completion. when the mac detects physts asserted, it knows the detection result from rxsts[2:0] and can deassert txdet/lpbk. 6.3 beacon transmitting and detection beacon transmitting is required for the gl9711 in p2 state to wake up the receiver in the other side of the link. when the gl9711 is in p2 state, the mac can deassert txidle to instruct the gl9711 to repeatedly transmit a beacon. for the beacon receiving side, if the gl9711 receives a beacon, it will transition rxidle to low to indicate an exit from electrical idle. when the gl9711 is in p2 state and mac senses the rxidle transitioned from high to low, it knows a beacon has been detected. 6.4 receiver status report l add and remove a skp the gl9711 implements an elastic buffer to compensate the clock rate difference between the recovery clock and its transmit clock. while receiving a skp ordered-set, compliant to pci express base specification rev. 1.0a, the gl9711 can insert or remove one skp symbol in the skp ordered-set to avoid the buffer overrun or underrun. whenever adding or removing a skp symbol, the gl9711 will signal physts and corresponding rxsts[2:0] to mac. skp ordered-set received rxsts code add a skp 001b remove a skp 010b l receiver detected detected result rxsts code receiver not present 000b receiver present 011b
gl9711 pci express tm pipe x1 phy ? 2000-2006 genesys logic inc. - all rights reserved. page 30 l 8b/10b decode error when the gl9711 decodes the received 10-bit symbol and detects an error code which does not correspond to any valid data, it will replace the code with an edb symbol, assert physts and encode rxsts[2:0] with the values of decode error status, 3 b100. l elastic buffer overrun and underrun when the overrun or underrun of the elastic buffer occurs, the gl9711 will assert physts and encode rxsts[2:0] with the values of decode error status. elastic buffer rxsts code overrun 101b underrun 110b in the case of elastic buffer overrun, the gl9711 drops the symbol. for the elastic buffer underrun, the gl9711 inserts the edb symbol. the physts and rxsts[2:0] are presented on the mac interface during the clock cycle where gl9711 drops or inserts the symbol. l disparity errors to report a disparity error detected, the gl9711 asserts physts and encodes rxsts[2:0] with the values of decode error status, 3 b111. 6.5 loopback the gl9711 supports a loopback mode to re-transmit its received data. when the mac sets the gl9711 in p0 state and asserts txdet/lpbk, the gl9711 enters a loopback. in loopback, the gl9711 transmits data from it received data instead of mac interface. meanwhile, it presents the received data on the mac interface as normal operation. when set into loopback mode and acting as a loopback slave according to the pci express base specification rev. 1.0a, the gl9711 received data from the loopback master. if the master intends to end the loopback, it sends an electrical idle ordered-set to the gl9711. when the mac detects the electrical idle ordered-set, it de-asserts txdet/lpbk and asserts txidle to instruct the gl9711 to stop loopback. the mac should take care the gl9711 has retransmit at least three bytes of the electrical idle before it makes the gl9711 s transmitter into electrical idle. 6.6 polarity inversion the gl9711 supports lane polarity inversion. while pin rxplr asserted, the gl9711 inverts its received data on the mac interface. 6.7 setting negative disparity to set the running disparity to negative, the mac asserts txcmp for one pclk cycle that matches with the data that is to be transmitted where running disparity is negative.
gl9711 pci express tm pipe x1 phy ? 2000-2006 genesys logic inc. - all rights reserved. page 31 6.8 behavior summary pd[1:0] txdet/lpbk txidlex behavior 0 0 gl9711 is transmitting data from mac interface normally. 0 1 gl9711 is not transmitting and is in electrical idle. 1 0 gl9711 enters loopback mode. p0 1 1 illegal x 0 illegal p0s x 1 gl9711 is not transmitting and is in electrical idle. x 0 illegal 0 1 gl9711 is idle. p1 1 1 gl9711 performs a receiver detection. x 0 gl9711 transmits a beacon. p2 x 1 gl9711 is idle. 6.9 power saving support the gl9711 supports four power states including p0, p0s, p1 and p2 and can be controlled to perform active state power management on a pci express link. p0 is the normal operational state where data and control packets can be transmitted and received. when directed from p0 to a lower power state, the gl9711 can immediately take appropriate power saving actions. the power saving scheme of the gl9711 for various power down states is listed in the table below. pd[1:0] transmitter receiver pll pclk output p0 on on on on p0s high-impedance electrical idle on on on p1 high-impedance electrical idle off but exit from electrical idle is detectable on on p2 high-impedance electrical idle (capable of transmitting a beacon) off but exit from electrical idle is detectable off off
gl9711 pci express tm pipe x1 phy ? 2000-2006 genesys logic inc. - all rights reserved. page 32 6.10 operation mode and multi-functional pins there are four modes for gl9711 operation which is selected by pin opmode[1:0]. mode [1] [0] description 1 0 0 8 bit mode 2 0 1 16 bit mode 3 1 0 10 bit mode 4 1 1 internal use only mode 1 : the gl9711 is configured into 8-bit parallel bus. the parallel bus is synchronous with pclk at 250 mhz. mode 2 : the gl9711 acts as a 1-lane phy with a 16-bit parallel interface at 125 mhz. mode 3 : the gl9711 is configured as a serdes with 10-bit parallel bus. mode 4 : for internal use only table 6.1 - pin functions pin number mode 1 mode 2 mode 3 t14 pclk(o) pclk(o) tbc(o) c17 txd15(i) c16 txd14(i) e14 txd13(i) d15 txd12(i) d14 txd11(i) e16 txd10(i) c14 txd9(i) d13 txd8(i) n16 txd7(i) txd7(i) txd7(i) l15 txd6(i) txd6(i) txd6(i) n17 txd5(i) txd5(i) txd5(i) m15 txd4(i) txd4(i) txd4(i) m16 txd3(i) txd3(i) txd3(i) k14 txd2(i) txd2(i) txd2(i) l16 txd1(i) txd1(i) txd1(i) l17 txd0(i) txd0(i) txd0(i) e15 txdk1(i) k16 txdk(i) txdk0(i) txd8(i) r12 txidle(i) txidle(i) txidle(i) l14 txcmp(i) txcmp(i) txd9(i) u13 rxplr(i) rxplr(i) rxplr(i) h16 rxd15(o) j16 rxd14(o) h14 rxd13(o) g17 rxd12(o) h15 rxd11(o)
gl9711 pci express tm pipe x1 phy ? 2000-2006 genesys logic inc. - all rights reserved. page 33 g16 rxd10(o) g15 rxd9(o) f16 rxd8(o) p13 rxd7(o) rxd7(o) rxd7(o) u16 rxd6(o) rxd6(o) rxd6(o) p14 rxd5(o) rxd5(o) rxd5(o) r15 rxd4(o) rxd4(o) rxd4(o) n14 rxd3(o) rxd3(o) rxd3(o) t16 rxd2(o) rxd2(o) rxd2(o) p15 rxd1(o) rxd1(o) rxd1(o) r16 rxd0(o) rxd0(o) rxd0(o) e17 rxdk1(o) n15 rxdk(o) rxdk0(o) rxd8(o) p11 rxvld(o) rxvld(o) rxvld(o) t17 rxsts2(o) rxsts2(o) rbc(o) m14 rxsts1(o) rxsts1(o) rxprsnt(o) p17 rxsts0(o) rxsts0(o) rxd9(o) u5 physts(o) physts(o) physts(o) t12 rxidle(o) rxidle(o) rxidle(o)
gl9711 pci express tm pipe x1 phy ? 2000-2006 genesys logic inc. - all rights reserved. page 34 chapter 7 electrical characteristics 7.1 dc voltage specifications table 7.1 - dc voltage specifications symbol parameter min typ max unit vdd25 phy interface voltage 2.375 2.5 2.625 v vdd18 core voltage 1.71 1.8 1.89 v vdd12 reference voltage for phy inerface 1.1875 1.25 1.3125 v vddtx voltage for transmitters 1.71 1.8 1.89 v vddrx voltage for receivers 1.71 1.8 1.89 v vddpll voltage for pll 1.71 1.8 1.89 v 7.2 transmit and receive latency time table 7.2 - transmit and receive latency time symbol parameter min typ max unit t tx-lat transmit latency, time for data moving from mac interface (pclk rising edge) to tx serial lines (the first bit of 10-bit symbol) 25 - 30 ns t rx-lat receive latency, time for data moving from rx serial lines (the first bit of 10- bit symbol) to mac interface (pclk rising edge) 48 - 54 ns 7.3 transition time of power state table 7.3 C transition time of power state symbol parameter min typ max unit t p0s-p0 time for phy to return to p0, after having been in p0s . time is measured when pd[1:0] are set to p0 until the phy asserts physts 52 - 74 ns t p1-p0 time for phy to return t o p0, after having been in p1. time is measured when pd[1:0] are set to p0 until the phy asserts physts 52 - 74 ns t p2-p1 time for phy to return to p1 , after having been in p2. time is measured when pd[1:0] are set to p1 until the phy asserts physts 16 - 17 m s t p0-p0s time for phy to return to p0s , after having been in p0 . time is measured when pd[1:0] are set to p0s until the phy asserts physts 52 - 74 ns t p0-p1 time for phy to return to p1 , after having been in p0. time is measured when pd[1:0] are set to p1 until the phy asserts physts 52 - 74 ns t p0-p2 time for phy to return to p2 , after having been in p0 . time is measured when pd[1:0] are set to p2 until the phy asserts physts 16 - 17 m s
gl9711 pci express tm pipe x1 phy ? 2000-2006 genesys logic inc. - all rights reserved. page 35 7.4 power consumption l power consumption table 7.4 - power consumption of each power state in different operation mode current at 2.5v (ma) current at analogue 1.8v (ma) current at digital 1.8v (ma) operation condition power state operation mode power consumption (mw) 59 90 57 all on p0 16-bit @125mhz pclk 412.1 12 71 49 pll on tx idle rx on p0s 16-bit @125mhz pclk 246 12 64 38 pll on tx idle rx idle p1 16-bit @125mhz pclk 213.6 6 36 6 pll off tx idle rx idle p2 16-bit @3.13mhz pclk 90.6 7.5 differential transmitter and receiver serial output l transmitter serial output table 7.5 C transmitter serial output symbol parameter min typ max unit ui unit interval 399.88 400 400.12 ps v tx-diffp-p differential peak to peak output voltage 0.8 - 1.2 ui v tx-de-ratio de- emphasized differential output voltage (ratio) -3.0 -3.5 -4.0 db t tx-eye minimum tx eye width 0.7 - - ui t tx-eye-median-to-max-jitter maximum time between the jitter median and maximum deviation from the median - - 0.15 ui t tx-rise , t tx-fall d+/d- tx output rise/fall time 0.125 - - ui v tx-cm-acp rms ac peak comm on mode output voltage - - 20 ma v tx-cm-dc-active-idle-delta absolute delta of dc common mode voltage during l0 and electrical idle 0 - 100 ma v tx-cm-dc-line-delta absolute delta of dc common mode voltage between d+ and d- 0 - 25 ma v tx-idle-diffp elect rical idle differential peak output 0 - 20 ma
gl9711 pci express tm pipe x1 phy ? 2000-2006 genesys logic inc. - all rights reserved. page 36 voltage v tx-rcv-detect the amount of voltage change allowed during receiver detection - - 600 ma v tx-dc-cm the tx dc common mode voltage 0 - 3.6 v i tx-short tx short circuit current limit - - 90 ma t tx-idle-min minimum time spent in electrical idle 50 - - ui t tx-idle-set-to-idle maximum time to transition to a valid electrical idle after sending an electrical idle ordered set - - 20 ui t tx-idle-to-diff-data maximum time to transition to valid tx specificat ions after leaving an electrical idle condition - - 20 ui rl tx-diff differential return loss 12 - - db rl tx-cm common mode return loss 6 - - db z tx-diff-dc dc differential tx impedance 80 100 120 c tx ac coupling capacitor 75 - 200 nf tcrosslink crosslink random timeout 0 - 1 ms l receiver serial output table 7.6 C receiver serial output symbol parameter min typ max unit ui unit interval 399.88 400 400.12 ps v rx-diffp-p differential input peak to peak voltage 0.175 - 1.2 v t rx-eye minimum receiver eye width 0.4 - - ui t rx-eye-median-to-max-jitter m aximum time between the jitter median and maximum deviation from the median - - 0.3 ui v rx-cm-acp ac peak common mode input voltage - - 150 mv rl rx-diff differential return loss 15 - - db rl rx-cm common mode return loss 6 - - db z rx-diff-dc dc differential input impedance 80 100 120 z rx-dc dc input impedance 40 50 60 z rx-high-imp-dc powered down dc input impedance 200k - - v rx-idle-det-diffp-p electrical idle detect threshold 65 - 175 mv t rx-idle-det-diff-entertime u nexpected electrical idle enter detect threshold integration time - - 10 ms
gl9711 pci express tm pipe x1 phy ? 2000-2006 genesys logic inc. - all rights reserved. page 37 7.6 recommended operating conditions table 7.7 C temperature range symbol parameter min typ max unit t junctoin junction operating temperature range 0 - 125 t a operating ambient temperature range 0 - 75 t stg storage temperature range -40 - 150 table 7.8 C thermal characteristics symbol parameter min typ max unit ja (0 m/s) - 33.2 - /w ja (1 m/s) - 28.7 - /w ja (2 m/s) thermal resistance from junction to ambient ps: (x m/s) means the air flow velocity (jedec jesd51-6 moving air, maximum reflow temperature for smt is 255 ~260 ) - 27.5 - /w jt thermal characterization parameter from junction-to-top center (jedec jesd51-2 still air, maximum reflow temperature for smt is 255 ~260 ) - 0.39 - /w jc thermal resistance from junction to case (jedec jesd51-2 still air, maximum reflow temperature for smt is 255 ~260 ) - 12.3 - /w
gl9711 pci express tm pipe x1 phy ? 2000-2006 genesys logic inc. - all rights reserved. page 38 chapter 8 pipe timing characteristics 8.1 input setup, hold time and output timing figure 8.1 C definition of input setup and hold time
gl9711 pci express tm pipe x1 phy ? 2000-2006 genesys logic inc. - all rights reserved. page 39 figure 8.2 C definition of output timing table 8.1 C input setup, hold time and output timing for 8-bit sdr mode symbol parameter min typ max unit t cycle pclk cycle time 3.99 4 4.01 ns duty- h duty cycle for pclk high 35 - 50 % t is input setup time - - 1 ns t ih input hold time 1 - - ns t co clock to output delay - 2.7 3.2 ns t oh output hold time 1 2.1 - ns table 8.2 C input setup, hold time and output timing for 8-bit ddr mode symbol parameter min typ max unit t cycle pclk cycle time 7.98 8 8.02 ns t is input setup time - - 1.4 ns t ih input hold time 0.5 - - ns t co clock to output delay - 1.5 1.6 ns t oh output hold time 0.8 1 - ns
gl9711 pci express tm pipe x1 phy ? 2000-2006 genesys logic inc. - all rights reserved. page 40 table 8.3 C input setup, hold time and output timing for 16-bit mode symbol parameter min typ max unit t cycle pclk cycle time 7.98 8 8.02 ns duty- h duty cycle for pclk high 48 - 50 % t is input setup time - - 1.4 ns t ih input hold time 0.5 - - ns t co clock to output delay - 5.3 5.6 ns t oh output hold time 4.3 4.7 - ns table 8.4 C input setup, hold time and output timing for 10-bit sdr mode symbol parameter min typ max unit t cycle pclk cycle time 3.99 4 4.01 ns duty- h duty cycle for pclk high 35 - 50 % t is input setup time - - 1 ns t ih input hold time 1 - - ns t co clock to output delay - 4 4.2 ns t oh output hold time 3.4 3.7 - ns table 8.5 C input setup, hold time and output timing for 10-bit ddr mode symbol parameter min typ max unit t cycle pclk cycle time 7.98 8 8.02 ns t is input setup time - - 1.4 ns t ih input hold time 0.5 - - ns t co clock to output delay - 4.1 4.3 ns t oh output hold time 3.5 3.7 - ns 8.2 reference timing information table 8.6 C reference timing information symbol parameter min typ max unit t recdet time for receiver detection - 10 - us t physts-reset timing from de- asserting rst_n to the falling edge of physts - 16.7 - us t reset reset assertion time to gl9711 10 - - us
gl9711 pci express tm pipe x1 phy ? 2000-2006 genesys logic inc. - all rights reserved. page 41 chapter 9 package dimension figure 9.1 - gl9711 233 pin lfbga package
gl9711 pci express tm pipe x1 phy ? 2000-2006 genesys logic inc. - all rights reserved. page 42 chapter 10 ordering information table 10.1 - ordering information part number package green version status GL9711-TGGXX 233-pin lfbga green package xx engineering sample

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