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copyright ? cirrus logic, inc. 2005 (all rights reserved) preliminary product information this document contains information for a new product. cirrus logic reserves the right to modify this product without notice. http://www.cirrus.com low voltage class-d pwm headphone amplifier features ? up to 95 db dynamic range ? 1.8 v to 2.4 v analog and digital supplies ? sample rates up to 96 khz ? digital tone control ? 3 selectable hpf and lpf corner frequencies ? 12 db boost for bass and treble - 1 db step size ? programmable digital volume control ? +18 to -96 db in 1 db steps ? peak signal soft limiting ? de-emphasis for 32 khz, 44.1 khz, and 48 khz ? selectable outputs for each channel, including ? channel a: r, l, mono (l + r) / 2, mute ? channel b: r, l, mono (l + r) / 2, mute ? pwm popguard ? ? 23 mw/channel into 16 ? @ 2.4 v description the cs44l11 is a complete stereo digital-to-pwm class-d audio amplifier syst em controller including in- terpolation, volume control, and a headphone amplifier in a 16-pin tssop package. the cs44l11 architecture us es a direct-to-digital ap- proach that maintains digital signal integrity to the final output filter. this minimize s analog interference effects that can negatively affect system performance. the cs44l11 contains on-chip digital bass and treble boost, peak signal limitin g, and de-emphasis. the pwm amplifier can achieve greater than 90% efficiency. this efficiency leads to longer battery life for portable sys- tems, smaller device package, less heat sink requirements, and smaller power supplies. the cs44l11 is ideal for portable audio, headphone amplifiers, and mobile phones. ordering information CS44L11-CZZ, lead free -10 to 70 c 16-pin tssop multibit ? modulator with correction multibit ? modulator with correction digital volume control, bass/treble boost, compression limiting, de-emphasis control port scl/dif0 mclk serial port sda/dem pwm conversion pwm conversion hp_b va_hpb gnd_hpb level shifter va_hpa level shifter hp_a gnd_hpa rst interpolation sclk lrck input sampling rate lrclk/mclk ratio sdin audio vd cs44l11 july '05 ds640pp4
2 ds640pp4 cs44l11 table of contents 1. characteristics and specificat ions ................ ................ ................ ............. ............. ........... 4 performance specifications.................................................................................................... 5 switching characteristics ...................................................................................................... .8 switching characteristics - control port - i2c format ............................................... 9 2. typical connection diagrams ............................................................................................... .10 3. register quick reference .............................................................................................. ..... 12 4. register descriptions ..................................................................................................... .......... 13 4.1 power and muting control (add ress 02h) .................................................................................... .13 4.1.1 soft ramp and zero cross control (szc) . ...................................................................... 13 4.1.2 power down (pdn) ............................... ........................................................................ .. 13 4.1.3 float output (flt) ..................................................................................................... ..... 13 4.1.4 ramp-up bypass (rupbyp) . ................ ................. ................ ................ ................ ......... 14 4.1.5 ramp-down bypass (rdnbyp) ................ ................ ................ ................ ............. ......... 14 4.2 channel a volume control (addr ess 03h) (vola) ....................................................................... 14 4.3 channel b volume control (addr ess 04h) (volb) ....................................................................... 14 4.4 tone control (address 05h) ................................................................................................ .......... 15 4.4.1 bass boost level (bb) ................................................................................................... .. 15 4.4.2 treble boost level (tb) ................................................................................................. .. 15 4.5 mode control 1 (address 06h) .............................................................................................. ........ 15 4.5.1 bass boost corner frequency (bbcf) ...... ...................................................................... 16 4.5.2 treble boost corner frequency (tbcf) .......................................................................... 16 4.5.3 tone control mode (tc) .................................................................................................. 17 4.5.4 tone control enable (tc_en) .............. .......................................................................... 17 4.5.5 peak signal limiter enable (lim_en) ... .......................................................................... 17 4.6 limiter attack rate (address 07h) (arate) . ................................................................................ 18 4.7 limiter release rate (address 08h) (rrate) ........................................................................ 18 4.8 volume and mixing control (address 09h) ................................................................................... 19 4.8.1 ramp speed (rmp_sp) .................................................................................................. 19 4.8.2 atapi channel mixing and muting (atapi) .................................................................... 19 4.9 mode control 2 (address 0ah) .............................................................................................. ....... 20 4.9.1 master clock divide enable (mclkdiv) ......................................................................... 20 4.9.2 clock divide (clkdiv) ................................................................................................... .. 20 4.9.3 double-speed mode (dbs) ............................................................................................. 21 4.9.4 frequency shift (frqsft) .............................................................................................. 21 4.9.5 de-emphasis control (dem) .......................................................................................... 22 4.10 mode control 3 (address 0bh) ................ ............................................................................. ...... 23 4.10.1 digital interface formats (dif) ............. .......................................................................... 2 3 4.10.2 channel a volume = channel b volume (a=b) ............................................................. 23 4.10.3 volume control bypass (vcbyp) ............ ...................................................................... 23 4.10.4 control port enable (cp_en) ........................................................................................ 23 4.10.5 freeze (freeze) ........................................................................................................ .. 24 4.11 revision indicator (address 0ch)[read only] ........................................................................... 24 5. pin description ........................................................................................................... ................... 25 6. applications ............................................................................................................. .................... 26 6.1 grounding and power supply decoupling .................................................................................... 2 6 6.2 clock modes ............................................................................................................... .................. 26 6.3 de-emphasis ............................................................................................................... ................. 26 6.4 pwm popguard transient control ............................................................................................ ... 26 6.5 recommended power-up sequence ........................................................................................... 27 6.5.1 stand-alone mode ........................................................................................................ ... 27 6.5.2 control port mode ....................................................................................................... ..... 27 7. control port interface .................................................................................................... ....... 28
ds640pp4 3 cs44l11 7.1 i2c format ................................................................................................................ .................... 28 7.1.1 writing in i2c format ................................................................................................... ..... 28 7.1.2 reading in i2c format ... ................................................................................................ ... 28 7.2 memory address pointer (map) ............................................................................................ ..... 28 7.2.1 incr (auto map increment enable) ................................................................................ 28 7.2.2 map3-0 (memory address po inter) ................................................................................. 29 8. parameter definitions ..................................................................................................... .......... 32 9. references ................................................................................................................ ..................... 32 10. package dimensions ....................................................................................................... .......... 33 11. revision history ......................................................................................................... ................ 34 list of figures figure 1. serial audio data interface timing ...... ............................................................................. ............ 8 figure 2. control port timing - i2c format..................................................................................... .............. 9 figure 3. typical cs44l11 connection diagram stand-alone mode ........................................................ 10 figure 4. typical cs44l11 connection diagram control port mode......................................................... 11 figure 5. dynamics control block diagram ....................................................................................... ........ 20 figure 6. de-emphasis curve.................................................................................................... ................ 22 figure 7. control port timing, i2c format...................................................................................... ............ 29 figure 8. single-speed st opband rejection ...................................................................................... ........ 29 figure 9. single-speed transition band ............. ............................................................................ ........... 29 figure 10. single-speed transition band (detail)............................................................................... ....... 29 figure 11. single-speed passband ripple ........................................................................................ ........ 29 figure 12. double-speed st opband rejection..................................................................................... ...... 30 figure 13. double-speed transition band........................................................................................ ......... 30 figure 14. double-speed transition band (detail) ............................................................................... ..... 30 figure 15. double-speed passband ripple........................................................................................ ....... 30 figure 16. left-justified, up to 24-bit data................................................................................... .............. 31 figure 17. right-justified, 24-bit data ........................................................................................ ............... 31 figure 18. i2s, up to 24-bit data.............................................................................................. .................. 31 figure 19. right-justified, 16-bit data ........................................................................................ ............... 31 list of tables table 1. register quick reference .............................................................................................. .............. 12 table 2. example volume settings ..................... .......................................................................... ............. 14 table 3. example bass boost settings ................... ........................................................................ ........... 15 table 4. example treble boost settings......................................................................................... ........... 15 table 5. base boost corner freque ncies in single-speed mode.............................................................. 16 table 6. base boost corner freque ncies in double-speed mode ............................................................ 16 table 7. treble boost corner freq uencies in single-speed mode............................................................ 16 table 8. example limiter attack rate settings.................................................................................. ........ 18 table 9. example limiter release rate settings................................................................................. ...... 18 table 10. atapi decode ......................................................................................................... .................. 19 table 11. single-speed clock modes - control port mode ....................................................................... 21 table 12. single-speed clock modes - stand-alone mode....................................................................... 21 table 13. double-speed clock modes - control port mode ...................................................................... 22 table 14. digital interface format (stand-alone mode).......................................................................... ... 25 table 15. revision history ..................................................................................................... .................... 34
4 ds640pp4 cs44l11 1. characteristics and specifications (all min/max characterist ics and specifications are guaranteed over th e specified operating conditions. typical per- formance characteristics and specifications are derived from measurem ents taken at nominal supply voltages and ta = 25c.) specified operating conditions (gnd = 0 v, all voltages with respect to 0 v) absolute maximum ratings (gnd = 0 v; all voltages with respect to 0 v. operation beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes.) parameters symbol min typ max units dc power supplies: headphone digital va_hpx vd 1.7 1.7 - - 2.5 2.5 v v ambient temperature t a -10 - 70 c parameters symbol min max units dc power supplies: headphone digital va_hpx vd -0.3 -0.3 3.0 3.0 v v input current, any pin except supplies i in 10 ma digital input voltage v ind -0.3 vd + 0.4 v ambient operating temperature (power applied) t a -55 125 c storage temperature t stg -65 150 c
ds640pp4 5 cs44l11 performance specifications (full-scale output sine wave, 997 hz, mclk = 12.288 m hz, measurement bandwidth 10 hz to 20 khz, unless otherwise specified; fs for single-speed mode = 48 khz, sclk = 3.072 mhz; fs for double-speed mode = 96 khz, sclk = 6.144 mhz. test load rl= 16 ? , cl = 10 pf. performance results are measured in production using a 4700 f capacitor on the va_hpx pins. result s will be degraded if smalle r value capacitors are used.) parameter symbol min typ max unit headphone output dynamic performance for vd = va_hpx = 2.4 v dynamic range 18 to 24-bit a-weighted unweighted 16-bit a-weighted unweighted 90 88 88 86 95 93 93 91 - - - - db db db db total harmonic distortion + noise 0 dbfs -20 dbfs -60 dbfs thd+n - - - -60 -73 -33 -55 - - db db db interchannel isolation (1 khz) -tbd-db headphone output dynamic performance for vd = va_hpx = 1.8 v dynamic range 18 to 24-bit a-weighted unweighted 16-bit a-weighted unweighted 87 85 85 83 92 90 90 88 - - - - db db db db total harmonic distortion + noise 0 db -20 db -60 db thd+n - - - -55 -70 -30 -50 - - db db db interchannel isolation (1 khz) -60-db pwm headphone output full-scale headphone output voltage -0.75 x va_hp -vpp headphone output quiescent voltage - 0.5 x va_hp -vdc interchannel gain mismatch -0.1-db modulation index --85% maximum headphone output va_hpx=2.4 v rms ac-current va_hpx=1.8 v i hp - - 38 28 - - ma ma parameter single-speed mode double-speed mode symbol min typ max min typ max unit digital filter response (note 1) ) passband to -0.05 db corner (note 2) to -0.1 db corner to -3 db corner 0 - 0 - - - .4535 - .4998 - 0 0 - - - - .4426 .4984 fs fs fs frequency response 10 hz to 20 khz (note 3) -.02 - +.08 0 - +0.11 db stopband .5465 - - .577 - - fs stopband attenuation (note 4) 50 - - 55 - - db group delay tgd - 9/fs - - 4/fs - s
6 ds640pp4 cs44l11 notes: 1. filter response is not tested but is guaranteed by design. 2. response is clock-dependent and will scale wi th fs. note that the response plots ( figures 8 - 15 ) have been normalized to fs and can be de-normalized by multiplying the x-axis scale by fs. 3. referenced to a 1 khz, full-scale sine wave. 4. for single-speed mode, the measurement bandwidth is 0.5465 fs to 3 fs. for double-speed mode, the measurement bandwidth is 0.577 fs to 1.4 fs. 5. de-emphasis is not available in double-speed mode. passband group delay deviation 0 - 40 khz 0 - 20 khz - - - 0.36/fs - - - - 1.39/fs 0.23/fs - - s s de-emphasis error fs = 32 khz (relative to 1 khz) fs = 44.1 khz fs = 48 khz - - - - - - +.2/-.1 +.05/-.14 +0/-.22 (note 5) db db db parameter single-speed mode double-speed mode symbol min typ max min typ max unit
ds640pp4 7 cs44l11 digital characteristics (gnd = 0 v; all voltages with respect to 0 v.) power and thermal characteristics (gnd = 0 v; all voltages with respect to 0 v. hp_x outputs unloaded.) notes: 6. power down mode is defined as rst = low with all clocks and data lines held static. 7. normal operation is defined as rst = hi. parameters symbol min typ max units high-level input voltage v ih 0.7 x vd - - v low-level input voltage v il --0.3 x vdv input leakage current i in --10 a input capacitance -8-pf parameters symbol min typ max units power down (note 6) power supply current vd = va_hpx = 2.4 v vd = va_hpx = 1.8 v - - 380 110 - - a a normal operation (note 7) power supply current vd = va_hpx = 2.4 v vd = va_hpx = 1.8 v - - 14 9 - - ma ma total power dissipation- vd = va_hpx = 2.4 v normal operation (note 6) vd = va_hpx = 1.8 v - - 34 16 - - mw mw maximum headphone power output (1 khz full-scale sine wave va_hpx = 2.4 v into 16 ? load) va_hpx = 1.8 v - - 23 13 - - mw mw power supply rejection ratio psrr - 0 - db package thermal resistance ja -75-c/watt
8 ds640pp4 cs44l11 switching characteristics (gnd = 0 v; all voltages with respect to 0 v.) parameters symbol min typ max units input sample rate single-speed mode double-speed mode fs fs 8 50 - - 50 100 khz khz mclk duty cycle 40 50 60 % lrck duty cycle 40 50 60 % sclk pulse width low t sclkl 20 - - ns sclk pulse width high t sclkh 20 - - ns sclk period single-speed mode t sclkw --ns double-speed mode t sclkw --ns sclk rising to lrck edge delay t slrd 20 - - ns sclk rising to lrck edge setup time t slrs 20 - - ns sdin valid to sclk rising setup time t sdlrs 20 - - ns sclk rising to sdin hold time t sdh 20 - - ns 1 128 () fs --------------------- - 1 64 () fs ------------------ - sclkh t slrs t slrd t sdlrs t sdh t sclkl t sdin sclk lrck sclkw t figure 1. serial audi o data interface timing
ds640pp4 9 cs44l11 switching characteristics - control port - i2c format (gnd = 0 v; all voltages with respect to 0 v.) notes: 8. data must be held for sufficient ti me to bridge the transition time, t fc , of scl. 9. the acknowledge delay is based on mclk and can limit the maximum transaction speed. 10. for single-speed mode and for double-speed mode. parameter symbol min max unit scl clock frequency f scl - 100 khz rst rising edge to start t irs 500 - ns bus free time between transmissions t buf 4.7 - s start condition hold time (prior to first clock pulse) t hdst 4.0 - s clock low time t low 4.7 - s clock high time t high 4.0 - s setup time for repeated start condition t sust 4.7 - s sda hold time from scl falling (note 8) t hdd 0-s sda setup time to scl rising t sud 250 - ns rise time of scl and sda t rc , t rc -1s fall time scl and sda t fc , t fc -300ns setup time for stop condition t susp 4.7 - s acknowledge delay from scl falling (note 9) t ack - (note 10) ns 5 256 fs --------------------- 5 128 fs --------------------- t buf t hdst t low t hdd t high t sud stop start sda scl t irs rst t hdst t rc t fc t sust t sus p start stop repeated t rd t fd t ack figure 2. control port timing - i2c format
10 ds640pp4 cs44l11 2. typical connection diagrams rst va_hpb 1.8 to 2.4 v supply 100f + va_hpa vd 12 13 7 6 supply + 1.8 to 2.4 v 10 15 g nd gnd gnd digital a udio source dif0 dem mode control 11 14 0.22 f 0.22 f hp _a hp _b 100 h 100 h 220 f 220 f + + 16 ? headphones low esr tantalum 1.0f 0.1f 5 4 3 2 1 mclk sclk lrck sdin 1.0f 0.1f 9 16 8 vd figure 3. typical cs44l11 conn ection diagram stand-alone mode cs44l11 * filter component values shown are for a 16 ? load. please see the cdb44l11 datasheet for information on how to calculate filter values for other loads.
ds640pp4 11 cs44l11 va_hpb .8 to 2.4 v supply 100f + va_hpa vd 12 13 7 6 supply + 1.8 to 2.4 v 10 15 g nd gnd gnd digital a udio source control logic 11 14 0.22 f 0.22 f hp _a hp _b 100 h 100 h 220 f 220 f + + 16 ? headphones low esr tantalum 1.0f 0.1f 5 4 3 2 1 mclk sclk lrck sdin 1.0f 0.1f 8 scl rst 16 sda 9 supply 1.8 to 2.4 v rpullup vd figure 4. typical cs44l11 conn ection diagram co ntrol port mode cs44l11 * filter component values shown are for a 16 ? load. please see the cdb44l11 datasheet for infor- mation on how to calculate filter values for other loads.
12 ds640pp4 cs44l11 3. register quick reference addr function 7 6 5 4 3 2 1 0 2h power and muting control szc1 szc0 pdn flt rupbyp rdnbyp reserved reserved default 10100000 3h channel a volume control vola7 vola6 vola5 vola4 vola3 vola2 vola1 vola0 default 00000000 4h channel b volume control volb7 volb6 volb5 volb4 volb3 volb2 volb1 volb0 default 00000000 5h tone control bb3 bb2 bb1 bb0 tb3 tb2 tb1 tb0 default 00000000 6h mode control 1 bbcf1 bbcf0 tbcf1 tbcf0 tc1 tc0 tc_en lim_en default 00000000 7h limiter attack rate arate7 arate6 arate5 arate4 arate3 arate2 arate1 arate0 default 00010000 8h limiter release rate rrate7 rrate6 rrate5 rrate4 rrate3 rrate2 rrate1 rrate0 default 00100000 9h volume and mixing control reserved reserved rmp_sp 1 rmp_sp 0 atapi3 atapi2 atapi1 atapi0 default 00011001 ah mode control2 mclkdiv clkdv1 clkdv0 dbs frqsft 1 frqsft 0 dem1 dem0 default 00000000 bh mode control 3 dif1 dif0 a=b vcbyp cp_en f reeze reserved reserved default 00000000 ch revision indicator reserved reserved reserved reserved rev3 rev2 rev1 rev0 default 0000read only read only read only read only table 1. register quick reference
ds640pp4 13 cs44l11 4. register descriptions 4.1 power and muting control (address 02h) 4.1.1 soft ramp and zero cross control (szc) default = 10 00 - immediate change 01 - zero cross control 10 - ramped control 11 - reserved function: immediate change when immediate change is select ed, all level changes will take effect immediately in one step. zero cross control zero cross enable dict ates that signal level cha nges, either by attenuation changes or muting, will occur on a signal zero crossing to mi nimize audible artifacts. the req uested level change will occur after a time-out period of 512 sample periods (10.7 ms at 48 kh z sample rate) if the signal does not encounter a zero crossing. the zero cross function is independe ntly monitored and implemented for each channel. ramped control soft ramp allows level changes, both muting and a ttenuation, to be implemented by incrementally ramp- ing, in 1/8 db steps, from the current level to the new level at a rate of 1 db per 8 left/right clock periods. note: ramped control is not available in double-speed mode. 4.1.2 power down (pdn) default = 1 0 - disabled 1 - enabled function: the entire device will enter a lo w-power state when this fu nction is enabled, and the contents of the control registers are retained in this mode. the power-down bit defaults to ?enabled? on power-up and must be disabled before normal operation in control port mode can occur. 4.1.3 float output (flt) default = 0 0 - disabled 1 - enabled function: when enabled, this bit will cause the headphone output of the cs44l11 to float when in the power down state (pdn=1). the float function can be used in sing le-ended applications to maintain the charge on the 76543210 szc1 szc0 pdn flt rupbyp rdnbyp reserved reserved 10100000
14 ds640pp4 cs44l11 dc-blocking capacitor during power tr ansients. on power transitions, the output will quickly change to the bias point; however, if th e dc-blocking capacitor still has a full char ge, as in short power cycles, the tran- sition will be very small, o ften inaudible. refer to section 6.4. 4.1.4 ramp-up bypass (rupbyp) default = 0 0 - normal 1 - bypass function: when in normal mode, the duty cycle of the output pw m signal is increased at a rate determined by the ramp speed variable (rmp_spx). normal mode is us ed in single-ended applications to reduce pops in the output caused by the dc-blocking capacitor. when the ramp-up function is bypassed in single-ended applications, there will be an abrupt change in the ou tput signal. refer to section 6.4 . 4.1.5 ramp-down bypass (rdnbyp) default = 0 0 - disabled 1 - enabled function: when in normal mode, the duty cycle of the output pwm signal is decreased at a rate determined by the ramp speed variable (rmp_spx). normal mode is us ed in single-ended applications to reduce pops in the output caused by the dc-blocki ng capacitor and changes in bias conditions. when the ramp-down function is bypassed in single-e nded applications, there will be an ab rupt change in the output signal. refer to section 6.4 . 4.2 channel a volume control (address 03h) (vola) 4.3 channel b volume control (address 04h) (volb) default = 0 db (no attenuation) function: the volume control registers allow independent control of the signal levels in 1 db increments from +18 to -96 db. volume settings are decoded using a 2?s complement code, as shown in table 2 . the volume changes are implemented as dictated by the soft and zero cross bits. all volume settings less than -96 db are equivalent to muting the channel via the atapi bits (see section 4.8.2 ). note: all volume settings greater than +18 db are interpreted as +18 db. 76543210 volx7 volx6 volx5 volx4 volx3 volx2 volx1 volx0 00000000 binary code decimal value volume setting 00001100 12 +12 db 00000111 7 +7 db 00000000 0 0 db 11000100 -60 -60 db 10100110 -90 -90 db table 2. example volume settings
ds640pp4 15 cs44l11 4.4 tone control (address 05h) 4.4.1 bass boost level (bb) default = 0 db (no bass boost) function: the level of the shelving bass boost filter is set by bass boost level. the level can be adjusted in 1 db increments from 0 to +12 db of boost. boost levels are decoded as shown in table 3 . levels above +12 db are interpreted as +12 db. 4.4.2 treble boost level (tb) default = 0 db (no treble boost) function: the level of the shelving treble boost filter is set by treble boost level. the le vel can be adjusted in 1 db increments from 0 to +12 db of boost. boost levels are decoded as shown in table 4 . levels above +12 db are interpreted as +12 db. note: treble boost is not available in double-speed mode. 4.5 mode control 1 (address 06h) 76543210 bb3 bb2 bb1 bb0 tb3 tb2 tb1 tb0 00000000 binary code decimal value boost setting 0000 0000 0 0 db 0000 0010 2 +2 db 0000 0110 6 +6 db 0000 1001 9 +9 db 0000 1100 12 +12 db table 3. example bass boost settings binary code decimal value boost setting 0000 0000 0 0 db 0000 0010 2 +2 db 0000 0110 6 +6 db 0000 1001 9 +9 db 0000 1100 12 +12 db table 4. example treble boost settings 76543210 bbcf1 bbcf0 tbcf1 tbcf0 tc1 tc0 tc_en lim_en 00000000
16 ds640pp4 cs44l11 4.5.1 bass boost corner frequency (bbcf) default = 00 00 - 50 hz 01 - 100 hz 10 - 200 hz 11 - reserved function: the bass boost corner frequency is user-selectable. the corner frequency is a function of lrck (sam- pling frequency), the dbs bit and the bbcf bits as shown in table 5 and table 6 . 4.5.2 treble boost corn er frequency (tbcf) default = 00 00 - 2 khz 01 - 4 khz 10 - 7 khz 11 - reserved function: the treble boost corner frequency is user selectable. the corner frequency is a function of lrck (sam- pling frequency) and the tbcf bits as shown in table 7 . note: treble boost is not available in double-speed mode. bbcf fs lrck in single-speed mode (dbs=0) 48 khz 24 khz 12 khz 8 khz 00 50 hz 25 hz 12.5 hz 8.33 hz 01 100 hz 50 hz 25 hz 16.7 hz 10 200 hz 100 hz 50 hz 33.3 hz 11 reserved reserved reserved reserved table 5. base boost corner frequencies in single-speed mode bbcf fs lrck in double-speed mode (dbs=1) 96 khz 48 khz 24 khz 16 khz 00 50 hz 25 hz 12.5 hz 8.33 hz 01 100 hz 50 hz 25 hz 16.7 hz 10 200 hz 100 hz 50 hz 33.3 hz 11 reserved reserved reserved reserved table 6. base boost corner frequencies in double-speed mode tbcf fs lrck in single-speed mode (dbs=0) 48 khz 24 khz 12 khz 8 khz 00 2khz 1khz 0.5khz 0.33khz 01 4 khz 2 khz 1 khz 0.67 khz 10 7 khz 3.5 khz 1.75 khz 1.17 khz 11 reserved reserved reserved reserved table 7. treble boost corner frequencies in single-speed mode
ds640pp4 17 cs44l11 4.5.3 tone control mode (tc) default = 00 00 - all settings are taken from user registers 01 - 12 db of bass boost at 100 hz and 6 db of treble boost at 7 khz (at lrck = 48 khz) 10 - 8 db of bass boost at 100 hz and 4 db of treble boost at 7 khz (at lrck = 48 khz) 11 - 4 db of bass boost at 100 hz and 2 db of treble boost at 7 khz (at lrck = 48 khz) function: the tone control mode bits determine how the ba ss boost and treble boost features are configured. the user-defined settings from the bass and treble boost level and corner frequency registers are used when these bits are set to ?00?. alternately, one of three pre-defined settings may be used (these settings are a function of lrck - refer to tables 5 , 6 , and 7 ). note: treble boost is not available in double-speed mode. 4.5.4 tone control enable (tc_en) default = 0 0 - disabled 1 - enabled function: the bass boost and treble boost features are active when this function is enabled. 4.5.5 peak signal limiter enable (lim_en) default = 0 0 - disabled 1 - enabled function: the cs44l11 will limit the maximum si gnal amplitude to prevent clippi ng when this fu nction is enabled. peak signal limiting is performed by first decrea sing the bass and treble boost levels. if the signal is still clipping, the digital attenuation is increased. the attack rate is determin ed by the limiter attack rate register. once the signal has dropped below the clipping level, the attenuation is decreased back to the user-se- lected level, followed by the bass boost being increase d back to the user-selected level. the release rate is determined by the limiter release rate register. note: the a=b bit should be set to ?1? for optimal limiter performance.
18 ds640pp4 cs44l11 4.6 limiter attack rate (address 07h) (arate) default = 10h - 2 lrck?s per 1/8 db function: the limiter attack rate is user-selectable. the rate is a function of sampling frequency, fs, and the value in the limiter attack rate register. rates are calculated using the function rate = 32/{value}, where {value} is the decimal value in the limiter attack rate regi ster and rate is in lrck?s per 1/8 db of change. a value of zero in this register is not recommended, as it will induce erratic beha vior of the limiter. use the lim_en bit to disable the limiter function (see "peak signal limiter enable (lim_en)" ). 4.7 limiter release rate (address 08h) (rrate) default = 20h - 16 lrck?s per 1/8 db function: the limiter release rate is user-selectable. the rate is a function of sampling frequency, fs, and the value in the limiter release rate register. rates are ca lculated using the function rate = 512/{value}, where {value} is the decimal value in the limiter release rate register and rate is in lrck?s per 1/8 db of change. note: a value of zero in this register is not recommended, as it will induce erratic behavior of the limiter. use the lim_en bit to disable the limiter function (see "peak signal limiter enable (lim_en)" ). 76543210 arate7 arate6 arate5 arate4 arate3 arate2 arate1 arate0 00010000 binary code decimal value lrck?s per 1/8 db 00000001 1 32 00010100 20 1.6 00101000 40 0.8 00111100 60 0.53 01011010 90 0.356 table 8. example limiter attack rate settings 76543210 rrate7 rrate6 rrate5 rrate4 rrate3 rrate2 rrate1 rrate0 00100000 binary code decimal value lrck?s per 1/8 db 00000001 1 512 00010100 20 25 00101000 40 12 00111100 60 8 01011010 90 5 table 9. example limiter release rate settings
ds640pp4 19 cs44l11 4.8 volume and mixing control (address 09h) 4.8.1 ramp speed (rmp_sp) default = 01 00 - ramp speed = approximately 0.1 seconds 01 - ramp speed = approximately 0.2 seconds 10 - ramp speed = approximately 0.3 seconds 11 - ramp speed = approximately 0.65 seconds function: this feature is used in single-ende d applications to reduce pops in the output caused by the dc-blocking capacitor. when in control port mode, the ramp spee d sets the time for the pwm signal to linearly ramp up and down from the bias point (50% pwm duty cycle). refer to section 6.4 . 4.8.2 atapi channel mixi ng and muting (atapi) default = 1001 - hp_a = l, hp_b = r (stereo) function: the cs44l11 implements the channel mixing functions of the atapi cd-rom specification. refer to table 10 and figure 5 for additional information. note: all mixing functions occur prior to the digital volume control. 76543210 reserved reserved rmp_sp1 rmp_sp0 atapi3 atapi2 atapi1 atapi0 00001001 atapi3 atapi2 atapi1 atapi0 hp_a hp_b 0000 mute mute 0001 mute r 0010 mute l 0011 mute [(l+r)/2] 0100 r mute 0101 r r 0110 r l 0111 r [(l+r)/2] 1000 l mute 1001 l r 1010 l l 1011 l [(l+r)/2] 1100[(l+r)/2] mute 1101[(l+r)/2] r 1110[(l+r)/2] l 1111[(l+r)/2][(l+r)/2] table 10. atapi decode
20 ds640pp4 cs44l11 4.9 mode control 2 (address 0ah) 4.9.1 master clock divide enable (mclkdiv) default = 0 function: the mclkdiv bit enables a circuit whic h divides the externally applied mc lk signal by 2 prior to all other internal circuitry. mclkdiv, dbs, clkdiv and frqsft are set per the user?s mclk and lrck require- ments. refer to tables 11 , 12 , 13 , and section 6.2 . 4.9.2 clock di vide (clkdiv) default = 00 function: mclkdiv, dbs, clkdiv and frqsft are set per th e user?s mclk and lrck requirements. refer to tables 11 , 12 , 13 , and section 6.2. 76543210 mclkdiv clkdv1 clkdv0 dbs frqsft1 frqsft0 dem1 dem0 00000000 hp_a hp_b left channel audio data right channel audio data channel b digital volume control eq channel a digital volume control eq & mute & mute figure 5. dynamics control block diagram
ds640pp4 21 cs44l11 4.9.3 double-speed mode (dbs) default = 0 0 - single-speed 1 - double-speed (dbs) function: single-speed supports 8 khz to 50 khz sample rates and double-speed supports 50 khz to 96 khz sam- ple rates. mclkdiv, dbs, clkdiv and frqsft are set per the user?s mclk and lrck requirements. refer to tables 11 , 12 , 13 , and section 6.2 . note: de-emphasis, ramp control, and treble control are not available in double-speed mode. 4.9.4 frequency shift (frqsft) default = 00 function: mclkdiv, dbs, clkdiv and frqsft are set per the user?s mclk and lrck requirements. refer to tables 11 , 12 , 13 , and section 6.2 . dbs = 0 mclkdiv = 0 dbs = 0 mclkdiv = 1 lrck (khz) mclk/ lrck mclk (mhz) mclk/ lrck mclk (mhz) frqsft1 frqsft0 clkdiv1 clkdiv0 pwm switching freq. (khz) 48 256 12.288 512 24.576 0 0 0 0 384 48 512 24.576 1024 49.152 0 0 1 0 44.1 256 11.2896 512 22.5792 0 0 0 0 352.8 44.1 512 22.5792 1024 45.1584 0 0 1 0 32 512 16.384 1024 32.768 0 1 0 0 512 32 1024 32.768 2048 65.536 0 1 1 0 24 512 12.288 1024 24.576 0 1 0 0 384 24 1024 24.576 2048 49.152 0 1 1 0 12 1024 12.288 2048 24.576 1 0 0 0 384 12 2048 24.576 4096 49.152 1 0 1 0 table 11. single-speed clock modes - control port mode lrck (khz) mclk/ lrck mclk (mhz) pwm switching freq. (khz) 48 256 12.288 384 48 512 24.576 44.1 256 11.2896 352.8 44.1 512 22.5792 32 1024 32.768 512 24 1024 24.576 384 12 2048 24.576 table 12. single-speed clock modes - stand-alone mode
22 ds640pp4 cs44l11 4.9.5 de-emphasis control (dem) default = 00 00 - disabled 01 - 44.1 khz 10 - 48 khz 11 - 32 khz function: selects the appropriate digital filter to maintain the standard 15 s/50 s digital de-emphasis filter re- sponse at 32, 44.1 or 48 khz sample rates (see figure 6 ). note: de-emphasis is not available in double-speed mode . dbs = 1 mclkdiv = 0 dbs = 1 mclkdiv = 1 lrck (khz) mclk/ lrck mclk (mhz) mclk/ lrck mclk (mhz) frqsft1 frqsft0 clkdiv1 clkdiv0 pwm switching freq. (khz) 96 128 12.288 256 24.576 0 0 0 0 384 96 256 24.576 512 49.152 0 0 1 0 88.2 128 11.2896 256 22.5792 0 0 0 0 352.8 88.2 256 22.5792 512 45.1584 0 0 1 0 table 13. double-speed clock modes - control port mode gain db -10db 0db frequency t2 = 15 s t1=50 s f1 f2 3.183 khz 10.61 khz figure 6. de-emphasis curve
ds640pp4 23 cs44l11 4.10 mode control 3 (address 0bh) 4.10.1 digital interface formats (dif) default = 00 00 - i2s 01 - right justified, 16 bit 10 - left justified 11 - right justified, 24 bit function: the required relationship between the left/right clock, serial clock and serial data is defined by the digital interface format and the options are detailed in figures 16 through 19 . 4.10.2 channel a volume = channel b volume (a=b) default = 0 0 - disabled 1 - enabled function: the hp_a and hp_b volume levels are independently controlled by the a and the b channel volume control bytes when this function is disabled. the vo lume on both hp_a and hp_b are determined by the a channel volume control byte and the b channel byte is ignored when this function is enabled. 4.10.3 volume control bypass (vcbyp) default = 0 0 - disabled 1 - enabled function: the digital volume control section is bypassed when this function is enabled. this disables the digital vol- ume control, muting, bass boost, treble boost, limiting, and atapi functions. 4.10.4 control port enable (cp_en) default = 0 0 - disabled 1 - enabled function: this bit defaults to 0, allowing t he device to power-up in stand-alone mode. the control port mode can be accessed by setting this bit to 1. this will allow the operat ion of the device to be controlled by the reg- isters and the pin definitions will conf orm to control port mode. refer to section 6.5.2 . 76543210 dif1 dif0 a=b vcbyp cp_en freeze hpsen reserved 00000000
24 ds640pp4 cs44l11 4.10.5 freeze (freeze) default = 0 0 - disabled 1 - enabled function: this function allows modifications to be made to th e registers without the changes being taking effect until the freeze is disabled. to make multiple changes in the control port registers take effect simultaneous- ly, you will first enable the freez e bit, then make all register c hanges, then disable the freeze bit. 4.11 revision indicator (a ddress 0ch)[read only] default = none 0001 - revision a 0010 - revision b 0011 - revision c etc. function: this read-only register indicates the revision level of the device. 76543210 reserved reserved reserved reserved rev3 rev2 rev1 rev0 00000000
ds640pp4 25 cs44l11 5. pin description sdin 1 serial audio data input ( input ) - input for two?s complement serial audio data. lrck 2 left right clock ( input ) - determines which channel, left or right, is currently active on the serial audio data line. the frequency of the left/right clock must be at the audio sample rate, fs. sclk 3 serial clock ( input ) - serial clock for the serial audio interface. mclk 4 master clock ( input ) - clock source for the pwm modulator and digital filters. tables 11 , 12 , 13 and 14 illustrate several standard audio sample rates and required master clock frequencies. vd 5 7 digital power ( input ) - positive power supply for the digital section. refer to "specified operating conditions" for appropriate voltages. gnd 6, 10 & 15 ground ( input ) - ground reference. hp_a hp_b 11 14 headphone outputs ( output ) - pwm headphone outputs. an external lc filter should be added to suppress high frequency switching noise. a dc blocki ng capacitor is also required. refer to typical connection diagrams. va_hpa va_hpb 12 13 headphone amplifier power ( input ) - positive power supply for the headphone amplifier. refer to "specified operating conditions" for appropriate voltages. rst 16 reset ( input ) - the device enters a low power mode and all internal registers are reset to their default settings when low. the control port cannot be accessed when reset is low. see section 6.5 . control port definitions scl 8 serial control port clock ( input ) - serial clock for the serial control port. requires an external pull-up resistor to vd in i2c mode. sda 9 serial control data ( input/output ) - sda is a data i/o line in i2c mode and requires an external pull-up resistor to the logic interface voltage. stand-alone definitions dif0 8 digital interface format (i nput ) - the required relationship between the left/right clock, serial clock and serial data is defined by the digital interface format and the options are detailed below dem 9 de-emphasis control ( input ) - selects the standard 15 s/50 s digital de-emphasis filter response at 44.1 khz sample rates. note: de-emphasis is not available in double- or quad-speed modes. when dem is grounded, de-emphasis is disabled. serial data sdin rst reset left/right clock lrck gnd headphone b ground serial clock sclk hp_b headphone b output master clock mclk va_hpb headphone b power digital power vd va_hpa headphone a power ground gnd hp_a headphone a output digital power vd gnd headphone a ground scl/dif0 scl/dif0 sda/dem sda/dem 1 2 3 4 5 6 7 8 9 10 11 12 13 14 16 15 dif0 description figure 0 i2s, up to 24-bit data 18 1 right justified, 16-bit data 19 table 14. digital interface format (stand-alone mode)
26 ds640pp4 cs44l11 6. applications 6.1 grounding and power supply decoupling as with any switching converter, the cs44l11 requires careful attention to power supply and grounding ar- rangements to optimize performance. figures 3 and 4 show the recommended power arrangement with vd and va_hpx connected to clean supplies. decoupling ca pacitors should be located as close to the device package as possible. if desired, a ll supply pins may be connected to the same supply, but a decoupling ca- pacitor should still be us ed on each supply pin. 6.2 clock modes one of the characteristics of a pwm amplifier is that the frequency content of out-of-band noise generated by the modulator is depe ndent on the pwm switchin g frequency. the systems des igner will specify the ex- ternal filter based on this switching frequency. the obvious implementation in a digital pwm system is to directly lock the pwm switching rate to the incoming data sample rate. however, th is would require a tun- able filter to attenuate the switching frequency acro ss the range of possible samp le rates. to simplify the external filter design and to accommodate sample rates ranging from 8 khz to 96 khz the cs44l11 con- troller uses several clock modes that keep the pwm switching frequency in a small range. in control port mode, for operation at a particular samp le rate the user selects register settings (refer to section 4.9 and tables 11 and 13 ) based on their mclk and mclk/lrck parameters. when using stand-alone mode, refer to tables tables 12 and 14 for available clock modes. 6.3 de-emphasis the cs44l11 includes on-chip digital de-emphasis. figure 6 shows the de-emphasis curve. the frequency response of the de-emphasis curve will scale prop ortionally with changes in sample rate, fs. the de-emphasis feature is include d to accommodate older audio reco rdings that utilize pre-emphasis equalization as a means of noise reduction. 6.4 pwm popguard transient control the cs44l11 uses popguard ? technology to minimize the effects of output transients during power-up and power-down. this technique minimizes the audio transients commonly produced by a single-ended, sin- gle-supply converter when it is impl emented with external dc-blocking c apacitors connected in series with the audio outputs. when the device is initia lly powered-up, the hp_x outputs are clamped to gnd. following a delay each out- put begins to increase the pwm du ty cycle toward the quiescent voltage point. by a speed set by the rmp_sp bit, the hp_x outputs will later reach the bias point (50% pwm duty cycl e), and audio output be- gins. this gradual voltage ramping allows time for th e external dc-blocking capacitor to charge to the qui- escent voltage, minimizing the power-up transient. to prevent transients at power-down, the device must first enter its power-down state. when this occurs, audio output ceases and the pwm duty cycle is decr eased until the hp_x outputs reach gnd. the time required to reach gnd is determined by the rmp_sp bi ts. this allows the dc-bloc king capacitors to slowly discharge. once this charge is di ssipated, the power to the device may be turned off, and the system is ready for the next power-on. to prevent an audio transient at the next power-on, the dc-blocking capacitors mu st fully discharge before turning off the power or exiting the power-down state. if full disc harge does not occur, a transient will occur when the audio outputs are initially clamped to gnd. the time that the device must remain in the pow- er-down state is related to the value of the dc-blo cking capacitance and the output load. for example, with
ds640pp4 27 cs44l11 a 220 f capacitor and a 16 ? load on the headphone outputs, the minimum power-down time will be ap- proximately 0.4 seconds. note that ramp-up and ramp-down period can be set to zero with the rupbyp and rdnbyp bits respec- tively. 6.5 recommended power-up sequence 6.5.1 stand-alone mode 1. hold rst low until the power supply, mast er, and left/right clocks are stab le. in this state, the control port is reset to its default settings and the hp_x lines will remain low. 2. bring rst high. the device will remain in a low power st ate and will initiate t he stand-alone power-up sequence. the control port will be accessible at this time. 6.5.2 control port mode 1. hold rst low until the power supply, mast er, and left/right clocks are stab le. in this state, the control port is reset to its default settings and the hp_x lines will remain low. 2. bring rst high. the device will remain in a low power st ate and will initiate t he stand-alone power-up sequence. the control port will be accessible at this time. 3. on the cs44l11 the control port pins are shared with stand-alone configur ation pins. to enable the control port, the user must set the cp_en bit. this is done by performing an i2c write. once the control port is enabled, these pins ar e dedicated to control port functionality. to prevent audible artifacts, the cp_en bit (see section 4.10.4 ) should be set prior to the completion of the stand-alone power-up sequence (1024/fs: ap proximately 21 ms at fs=48 khz). writing this bit will halt the stand-alone power-up sequence and initialize th e control port to its de fault settings. note, the cp_en bit can be set any time after rst goes high; however, setting this bit after the stand-alone pow- er-up sequence has completed can cause audible artifacts.
28 ds640pp4 cs44l11 7. control port interface the control port is used to load all the internal settings . the operation of the control port may be completely asyn- chronous with the audio sample rate. however, to avoid pote ntial interference problems, the control port pins should remain static if no operation is required. the cs44l11 has map auto incr ement capability, enabled by the incr bi t in the map register, which is the msb. if incr is 0, then the map will stay cons tant for successive writes. if incr is set to 1, then ma p will auto increment after each byte is written, allowing block reads or writes of successive registers. 7.1 i2c format sda is a bidirectional data line. data is clocked into and out of the part by the clock, scl, with a clock to data relationship as shown in figure 7 . the receiving device should send an acknowledge (ack) after each byte received. the chip address is 0010011. note: mclk is required during all i2c transactions. 7.1.1 writing in i2c format to communicate with the cs44l11, initiate a start condition of the bus. next, send the chip address. the eighth bit of the address byte is the r/w bit (low for a write). the next byte is the memory address pointer, map, which selects the register to be read or written. the map is then followed by the data to be written. to write multiple registers, continue providing a clock and data, waiting for the cs44l11 to ac- knowledge between each byte. to end the transaction, send a stop condition. 7.1.2 reading in i2c format to communicate with the cs44l11, initiate a start condition of the bus. next, send the chip address. the eighth bit of the address byte is the r/w bit (high for a read). the cont ents of the register pointed to by the map will be output after the chip address. to read multiple registers, co ntinue providing a clock and issue an ack after each byte. to end the transaction, send a stop condition. 7.2 memory address pointer (map) 7.2.1 incr (auto map increment enable) default = ?0? 0 - disabled 1 - enabled 76543210 incr reserved reserved reserved map3 map2 map1 map0 00000000
ds640pp4 29 cs44l11 7.2.2 map3-0 (memory address pointer) default = ?0000? sda scl r/w start ack data 1-8 ack data 1-8 ack stop note: if operation is a write, this byte contains the memory address pointer, map. note 1 0010011 figure 7. control po rt timing, i2c format -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 fre que ncy (norm alize d to fs ) amplitude (db) -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0. 4 0. 42 0. 44 0. 46 0. 48 0. 5 0. 52 0. 54 0. 56 0. 58 0. 6 frequency (norm alized to fs) amplitude (db) figure 8. single-speed stopband rejection figure 9. single-speed transition band -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55 frequency (norm alized to fs) amplitude (db) -0. 5 -0. 4 -0. 3 -0. 2 -0. 1 0 0. 1 0. 2 0. 3 0. 4 0. 5 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 frequency (norm alized to fs) amplitude (db) figure 10. single-speed transition band (d etail) figure 11. single-speed passband ripple
30 ds640pp4 cs44l11 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 frequency (normalized to fs) amplitude (db) -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0. 4 0. 42 0. 44 0. 46 0. 48 0. 5 0. 52 0. 54 0. 56 0. 58 0. 6 frequency (norm alized to fs) amplitude (db) figure 12. double-speed stopband rejection figure 13. double-speed transition band -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 0. 45 0. 46 0. 47 0. 48 0. 49 0. 5 0. 51 0. 52 0. 53 0. 54 0. 55 frequency (norm alized to fs) amplitude (db) -0.50 -0.40 -0.30 -0.20 -0.10 0.00 0.10 0.20 0.30 0.40 0.50 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 frequency (normalized to fs) figure 14. double-speed transition band (d etail) figure 15. double-speed passband ripple
ds640pp4 31 cs44l11 figure 16. left-justifi ed, up to 24-bit data lrck sclk left channel right channel sdata +3 +2 +1 lsb +5 +4 msb -1 -2 -3 -4 -5 +3 +2 +1 lsb +5 +4 msb -1 -2 -3 -4 figure 17. right-jus tified, 24-bit data lrck sclk left channel sdata 6543210 7 23 22 21 20 19 18 6543210 7 23 22 21 20 19 18 32 clocks 0 right channel lrck sclk left channel right channel sdata +3 +2 +1 lsb +5 +4 msb -1 -2 -3 -4 -5 +3 +2 +1 lsb +5 +4 msb -1 -2 -3 -4 figure 18. i2s, up to 24-bit data figure 19. right-justified, 16-bit data lrck sclk left channel right channel sdata 6543210 987 15 14 13 12 11 10 6543210 987 15 14 13 12 11 10 32 clocks
32 ds640pp4 cs44l11 8. parameter definitions total harmonic distor tion + noise (thd+n) the ratio of the rms value of the signal to the rms su m of all other spectral components over the specified bandwidth (typically 10 hz to 20 khz), including distortion components. expressed in decibels. dynamic range the ratio of the full-scale rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. dynamic range is a signal-to-no ise measurement over the specified bandwidth made with a -60 dbfs signal. 60 db is then added to the resulting measurement to refer the measurement to full scale. this technique ensures that the distortion comp onents are below the noise level and do not effect the measurement. this measurement technique has been accepted by the audio engineering society, aes17-1991, and the electron ic industries associatio n of japan, eiaj cp-307. interchannel isolation a measure of crosstalk between the left and right ch annels. measured for each c hannel at the converter's output with all zeros to the input under test and a full-sca le signal applied to the other channel. units in deci- bels. interchannel gain mismatch the gain difference between left and right channels. units in decibels. 9. references ?the i2c-bus specification: version 2.0? philips semico nductors, december 1998. http://www.semicon ductors.philips.com
ds640pp4 33 cs44l11 10.package dimensions notes: 1. ?d? and ?e1? are reference datums and do not included mold flash or protrusions, but do include mold mis- match and are measured at the parting line, mold flas h or protrusions shall not exceed 0.20 mm per side. 2. dimension ?b? does not include dambar protrusion/intr usion. allowable dambar protrusion shall be 0.13 mm total in excess of ?b? dimension at maximum material condition. dambar intrusion shall not reduce dimen- sion ?b? by more than 0.07 mm at least material condition. 3. these dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips. inches millimeters note dim min nom max min nom max a -- -- 0.043 -- -- 1.10 a1 0.002 0.004 0.006 0.05 -- 0.15 a2 0.03346 0.0354 0.037 0.85 0.90 0.95 b 0.00748 0.0096 0.012 0.19 0.245 0.30 2,3 d 0.193 0.1969 0.201 4.90 5.00 5.10 1 e 0.248 0.2519 0.256 6.30 6.40 6.50 e1 0.169 0.1732 0.177 4.30 4.40 4.50 1 e -- 0.026 bsc -- -- 0.065 bsc -- l 0.020 0.024 0.028 0.50 0.60 0.70 0 4 8 0 4 8 jedec #: mo-153 controlling dimension is millimeters 16l tssop (4.4 mm body) package drawing e n 1 23 e b 2 a1 a2 a d seating plane e1 1 l side view end view top view
34 ds640pp4 cs44l11 11.revision history release date changes pp1 april 2004 initial preliminary release pp2 september 2004 added lead-free device ordering information. pp3 march 2005 -corrected ?features? on page 1 . -corrected table 11, ?single-speed clock modes - control port mode,? on page 21 . -corrected table 12, ?single-speed clock modes - stand-alone mode,? on page 21 . -corrected table 13, ?double-speed clock modes - control port mode,? on page 22 . pp4 july 2005 added last two rows to table 13, ?double-speed clock modes - control port mode,? on page 22 . table 15. revision history contacting cirrus logic support for all product questions and inquiries contact a cirrus logic sales representative. to find the one nearest to you go to www.cirrus.com important notice "preliminary" product information describes products that are in production, but for which full characterization data is not ye t available. cirrus logic, inc. and its sub- sidiaries ("cirrus") believe that the information contained in this document is accurate and reliable. however, the information is subject to change without notice and is provided "as is" without warranty of any kind (express or implied). customers are advised to obtain the latest version of re levant information to verify, before placing orders, that information being relied on is current and complete. all products are sold subject to the terms and condit ions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. no responsibility is assu med by cirrus for the use of this informa- tion, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or ot her rights of third parties. this document is the property of cirrus and by furnishing this information, cirrus grants no license, express or implied under any patents, m ask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. cirrus owns the copyrights associated with the information contained herei n and gives consent for copies to be made of the information only for use within your organization with respect to cirrus integrated circuits or other products of c irrus. this consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resal e. certain applications using semic onductor products may involve potential risks of death, personal in jury, or severe prop- erty or environmental damage (?critical applications?). cirrus pro ducts are not designed, authorized or warranted for use in aircraft systems, military applications, products surgical ly implanted into th e body, automotive safe ty or security de- vices, life support products or other cri tical applications. inclusion of cirrus products in such applications is understood to be fully at the customer?s ri sk and cirrus disclaims and makes no warranty, express, statutory or implied, including the implied warranties of merchantab ility and fitness for particular purpose, with regard to any cirrus product that is used in such a manner. if the customer or cus tomer?s customer us es or permits the use of cirru s products in critical applica- tions, customer agrees, by such use, to fully indemnify cirrus , its officers, directors, employees, distributors and other agents from any and all liability, including attorneys? fees a nd costs, that may result from or arise in connection with these uses. cirrus logic, cirrus, and the cirrus logic logo designs are trademarks of cirrus logic, inc. all other brand and product names in this document may be trademarks or service marks of their respective owners.

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