View T81L0010B-AL_1619044.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

te ch tm preliminary t81l0010b tm technology inc. reserves the right p. 1 publication date: jan. 2006 to change products or specifications without notice. revision:a 8-bit mcu with embedded eeprom 1. features compatible with mcs-51 embedded 8k bytes otp rom embedded 1k bits eeprom 256 x 8-bit internal ram 15 programmable i/o lines 2 16-bit timer/counter & 1 16-bit timer 2 external interrupt input programmable serial uart interface low power idle & power-down modes watch-dog timer on-chip crystal & rc oscillator (selected by bonding option) internal power-on reset and external reset supported 32-pin lqfp package 3.3v operating voltage 2. general description the t81l0010b is 8-bit microcontroller designed and developed with low power and high speed cmos technology. it contains a 8k bytes otp rom, a 256 8 ram, 1k bits eeprom, 15 i/o lines, a watchdog timer, two 16-bit counter/timers, a seven source, two-priority level nested interrupt structure, a full duplex uart, and an on-chip oscillator and clock circuits. in addition, the t81l0010b has two selectable modes of power reduction-idle mode and power-down mode. the idle mode freezes the cpu while allowing the ram, timers, serial port, and interrupt system to continue functioning. the power-down mode saves the ram contents but freezes the oscillator, causing all other chip functions to be inoperative. 3. order information part number oscillator type package T81L0010B-AL rc 32-pin lqfp t81l0010b-bl crystal 32-pin lqfp
te ch tm preliminary t81l0010b tm technology inc. reserves the right p. 2 publication date: jan. 2006 to change products or specifications without notice. revision:a 4. block diagram port 1 drivers ram addr. register ram port 1 latch otp rom b register acc stack pointer tmp2 tmp1 alu psw interrupt, serial port, and timer block timing & control instruction register port 3 latch port 3 drivers program address register buffer pc incrementer program counter dptr p1.0 -p1.7 p3.0 -p3.5, p3.7 rst osc wdt xin xout eeprom interface eeprom
te ch tm preliminary t81l0010b tm technology inc. reserves the right p. 3 publication date: jan. 2006 to change products or specifications without notice. revision:a 5. pin configuration nc nc nc nc nc nc stop (int0)p3.2 p3.7 p1.0 p1.1 p1.2 nc p1.3 nc p1.4 1 8 7 6 5 4 3 2 916 15 14 13 12 11 10 24 23 22 21 20 19 18 17 27 28 25 26 32 31 30 29 (txd)p3.1 oscr p1.5 p1.6 p1.7 vcc rst/vpp (rxd)p3.0 gnd nc (t1)p3.5 nc (t0)p3.4 nc nc (int1)p3.3 lqfp-32 for rc oscillator T81L0010B-AL nc nc nc nc nc xout xin (int0)p3.2 p3.7 p1.0 p1.1 p1.2 nc p1.3 nc p1.4 1 8 7 6 5 4 3 2 916 15 14 13 12 11 10 24 23 22 21 20 19 18 17 27 28 25 26 32 31 30 29 (txd)p3.1 nc p1.5 p1.6 p1.7 vcc rst/vpp (rxd)p3.0 gnd nc (t1)p3.5 nc (t0)p3.4 nc nc (int1)p3.3 lqfp-32 for crystal oscillator t81l0010b-bl
te ch tm preliminary t81l0010b tm technology inc. reserves the right p. 4 publication date: jan. 2006 to change products or specifications without notice. revision:a 6. pin description number (32-pin) name type description 1 nc no connect 2 nc no connect 3 nc no connect 4 nc no connect 5 nc no connect 6(al) nc no connect 6(bl) xout i crystal oscillator output terminal. 7(al) stop o stop rc oscillator network. 7(bl) xin o crystal oscillator input terminal. 8 p3.2/(int0) i/o general-purpose i/o pin (default) or external interrupt source 0. 9 nc no connect 10 p3.3/(int1) i/o general-purpose i/o pin (default) or external interrupt source 1. 11 nc no connect 12 p3.4/(t0) i/o general-purpose i/o pin (default) or timer 0 external input pin. 13 nc no connect 14 p3.5/(t1) i/o general-purpose i/o pin (default) or timer 1 external input pin. 15 nc no connect 16 gnd ground 17 p3.7 i/o general-purpose i/o pin 18 p1.0 i/o general-purpose i/o pin 19 p1.1 i/o general-purpose i/o pin 20 p1.2 i/o general-purpose i/o pin 21 nc no connect 22 p1.3 i/o general-purpose i/o pin 23 nc no connect 24 p1.4 i/o general-purpose i/o pin 25 p1.5 i/o general-purpose i/o pin 26 p1.6 i/o general-purpose i/o pin 27 p1.7 i/o general-purpose i/o pin 28 vcc 3.3v power supply. 29 rst/vpp i reset signal input or programming supply voltage input. 30 p3.0/(rxd) i/o general-purpose i/o pin (default) or serial input port. 31 p3.1/(txd) i/o general-purpose i/o pin (default) or serial output port. 32(al) oscr i rc oscillator external resister connect pin. 32(bl) nc no connect
te ch tm preliminary t81l0010b tm technology inc. reserves the right p. 5 publication date: jan. 2006 to change products or specifications without notice. revision:a 7. temperature limit ratings parameter rating units operating temperature range -40 to +85 c storage temperature range -55 to +125 c 8. electrical characteristics d.c characteristics symbol parameter conditions min typ max units v cc operating voltage 25c 3.0 3.3 3.6 v no load, vcc=2.5v, 4mhz - - 1.6 ma i cc operating current no load, vcc=3.3v, 12mhz - - 6 ma i pd power down current vcc=3.3v - 0.1 1 ua v ih hi-level input voltage v out >=v voh(min.) v out <=v vol(min.) 2.1 - - v v il low-level input voltage v out >=v voh(min.) v out <=v vol(min.) - - 0.6 v i oh =-7ua 2.9 i oh =-45ua 2.4 v oh hi-level output voltage v cc =min. v i =v ih or v il i oh =-70ua 1.9 - - v i ol =12ma 0.2 i ol =25ma 0.4 v ol low-level output voltage v cc =min. v i =v ih or v il i ol =40ma - - 0.6 v a.c characteristics symbol parameter conditions min typ max units f sys1 system clock 1 (crystal osc) v cc =3.3v - 12 24 mhz f sys2 system clock 2 (rc osc) v cc =3.3v - 12 - mhz t res external reset high pulse width - 10 - system cycle power on start up time - 20 - ms
te ch tm preliminary t81l0010b tm technology inc. reserves the right p. 6 publication date: jan. 2006 to change products or specifications without notice. revision:a 9. function description 9.1. special function register f8h f0h b e8h e0h acc d8h d0h psw c8h t2con t2mod tl2 th2 c0h b8h ip b0h p3 a8h ie a0h p2 98h scon sbuf 90h p1 88h tcon tmod tl0 tl1 th0 th1 80h p0* sp dpl dph pcon *note: p0:internal still keeping, but for pad dominate, no external pin assignment accumulator : acc acc is the accumulator register. the mnemonics for accumulator-specific instructions, however, refer to the accumulator simply as a. b register : b the b register is used during multiply and divide operations. for other instructions it can be treated as another scratch pad register. program status word : psw the psw register contains program status information as detailed in cy ac f0 rs1 rs0 ov -- p bit symbol function psw.7 cy carry flag. psw.6 ac auxiliary carry flag. (for bcd operations.) psw.5 f0 flag 0. (available to the user for general purposes.) psw.4 rs1 register bank select control bit 1. set/cleared by software to determine working register bank. (see note. ) psw.3 rs0 register bank select control bit 0. set/cleared by software to determine working register bank. (see note. ) psw.2 ov overflow flag. psw.1 ? user-definable flag. psw.0 p parity flag. set/cleared by hardware each instruction cycle to indicate an odd/even number of ?one? bits in the accumulator, i.e., even parity. note : the contents of (rs1, rs0) enable the working register banks as follows: (0,0)? bank 0 (00h?07h) (0,1)? bank 1 (08h?0fh) (1,0)? bank 2 (10h?17h) (1,1)? bank 3 (18h?17h)
te ch tm preliminary t81l0010b tm technology inc. reserves the right p. 7 publication date: jan. 2006 to change products or specifications without notice. revision:a stack pointer : sp the stack pointer register is 8 bits wide. it is incremented before data is stored during push and call executions. while the stack may reside anywhere in on-chip ram, the stack pointer is initialized to 07h after a reset. this causes the stack to begin at locations 08h. data pointer (dptr) : dph & dpl the data pointer (dptr) consists of a high byte (dph) and a low byte (dpl). its intended function is to hold a 16-bit address. it may be manipulated as a 16-bit register or as two independent 8-bit registers. ports 1.0~1.7 & 3.0~3.5 & 3.7 all ports are the sfr latches, respectively. writing a one to a bit of a port sfr (p1 or p3) causes the corresponding port output pin to switch high. writing a zero causes the port output pin to switch low. when used as an input, the external state of a port pin will be held in the port sfr (i.e., if the external state of a pin is low, the corresponding port sfr bit w ill contain a ?0?; if it is high, the bit will contain a ?1?). serial data buffer : sbuf the serial buffer is actually two separate registers, a transmit buffer and a receive buffer. when data is moved to sbuf, it goes to the transmit buffer and is held for serial transmission. (moving a byte to sbuf is what initiates the transmission.) when data is moved from sbuf, it comes from the receive buffer. timer registers : th0, tl0, th1, tl1,th2,tl2 register pairs (th0, tl0) and (th1, tl1) and (th2, tl2) are 16-bit counting registers for timer/counters 0 and timer1and timer2, respectively. . control register : ip, ie, tmod, tcon, scon, pcon special function registers ip, ie, tmod, tcon, scon, and pcon contain control and status bits for the interrupt system, the timer/counters, and the serial port. they are described in later sections. standard serial interface the serial port is full duplex, meaning it can transmit and receive simultaneously. it is also receive-buffered, meaning it can commence reception of a second byte before a previously received byte has been read from the register. (however, if the first byte still hasn?t been read by the time reception of the second byte is complete, one of the bytes will be lost.) the ser ial port receive and transmit registers are both accessed at special function register sbuf. writing to sbuf loads the transmit register, and reading sbuf accesses a physically separate receive register. the serial port can operate in 4 modes: mode 0: serial data enters and exits through rxd. txd outputs the shift clock. 8 bits are transmitted/received (lsb first). the baud rate is fixed at 1/12 the oscillator frequency. mode 1: 10 bits are transmitted (through txd) or received (through rxd): a start bit (0), 8 data bits (lsb first), and a stop bit (1). on receive, the stop bit goes into rb8 in special function register scon. the baud rate is variable. mode 2: 11 bits are transmitted (through txd) or received (through rxd): start bit (0), 8 data bits (lsb first), a programmable 9th data bit, and a stop bit (1). on transmit, the 9th data bit (tb8 in scon) can be assigned the value of 0 or 1. or, for example, the parity bit (p, in the psw) could be moved into tb8. on receive, the 9th data bit goes into rb8 in special function register scon, while the stop bit is ignored. the baud rate is programmable to either 1/32 or 1/64 the oscillator frequency. mode 3: 11 bits are transmitted (through txd) or received (through rxd): a start bit (0), 8 data bits (lsb first), a programmable 9th data bit, and a stop bit (1). in fact, mode 3 is the same as mode 2 in all respects except baud rate. the baud rate in mode 3 is variable. in all four modes, transmission is initiated by any instruction that uses sbuf as a destinatio n register. reception is initiated in mode 0 by the condition ri = ?0? and ren = ?1?. reception is initiated in the other modes by the incoming start bit if ren = ?1?.
te ch tm preliminary t81l0010b tm technology inc. reserves the right p. 8 publication date: jan. 2006 to change products or specifications without notice. revision:a multiprocessor communications modes 2 and 3 have a special provision for multiprocessor communications. in these modes, 9 data bits are received. the 9 th one goes into rb8. then comes a stop bit. the port can be programmed such that when the stop bit is received, the serial port interrupt will be activated only if rb8 = ?1?. this feature is enabled by setting bit sm2 in scon. a way to use this feature in multiprocessor systems is as follows: when the master processor wants to transmit a block of data to one of several slaves, it first sends out an address byte which identifies the target slave. an address byte differs from a data byte in that the 9th bit is ?1? in an address byte and ?0? in a data byte. with sm2 = ?1?, no slave will be interrupted by a data byte. an address byte, however, will interrupt all slaves, so that each slave can examine the received byte and see if it is being addressed. the addressed slave will clear its sm2 bit and prepare to receive the data bytes that will be coming. the slaves that weren?t being addressed leave their sm2s set and go on about their business, ignoring the coming data bytes. sm2 has no effect in mode 0, in mode 1 can be used to check the validity of the stop bit. in mode 1 reception, if sm2 = ?1?, the receive interrupt will not active unless a valid stop bit is received. serial port control register the serial port control and status register is the special function register scon, shown in figure 11. this register contains not only the mode selection bits, but also the 9th data bit for transmit and receive (tb8 and rb8), and the serial por t interrupt bits (ti and ri). baud rates the baud rate in mode 0 is fixed: mode 0 baud rate = oscillator frequency / 12. the baud rate in mode 2 depends on the value of bit smod in special function register pcon. if smod = ?0? (which is the value on reset), the baud rate is 1/64 the oscillator frequency. if smod = ?1?, the baud rate is 1/32 the oscillator frequency. mode 2 baud rate =2 smod /64* (oscillator frequency) in the t81l0010b, the baud rates in modes 1 and 3 are determined by the timer 1 overflow rate. using timer 1 to generate baud rates when timer 1 is used as the baud rate generator, the baud rates in modes 1 and 3 are determined by the timer 1 overflow rate and the value of smod as follows: mode 1, 3 baud rate =2 smod /32* (timer 1 overflow rate) the timer 1 interrupt should be disabled in this application. the timer 1 itself can be configured for either ?timer? or ?counter? operation, and in any of its 3 running modes. in the most typical applications, it is configured for ?timer? operatio n, in the auto-reload mode (high nibble of tmod = 0010b). in that case the baud rate is given by the formula: mode 1, 3 baud rate =2 smod *(oscillator frequency)/ 32/12 / [256 _ (th1)] one can achieve very low baud rates with timer 1 by leaving the timer 1 interrupt enabled, and configuring the timer to run as a 16-bit timer (high nibble of tmod = 0001b), and using the timer 1 interrupt to do a 16-bit software reload. msb lsb sm0 sm1 sm2 ren tb8 rb8 ti ri where sm0, sm1 specify the serial port mode, as follows: sm0 sm1 mode description baud rate 0 0 0 shift register f osc / 12 0 1 1 8-bit uart variable 1 0 2 9-bit uart uart f osc /64 or f osc /32 1 1 3 9-bit uart variable interrupt enable register : ie msb lsb ea wdt et2 es et1 ex1 et0 ex0 ea ie.7 disables all interrupts. if ea = 0, no interrupt will be acknowledged. if ea = 1, each interrupt source is individually enabled or disabled by setting or clearing its enable bit. wdt ie.6 watchdog timer refresh flag. et2 ie.5 enable or disable the timer 2 overflow interrupt. es ie.4 enable or disable the serial port interrupt. et1 ie.3 enable or disable the timer 1 overflow interrupt. ex1 ie.2 enable or disable external interrupt 1. et0 ie.1 enable or disable the timer 0 overflow interrupt. ex0 ie.0 enable or disable external interrupt 0.
te ch tm preliminary t81l0010b tm technology inc. reserves the right p. 9 publication date: jan. 2006 to change products or specifications without notice. revision:a 9.2. external register table ( for lvr, eeprom, high/ normal driving) register address a15?a5-a0 hex name comments 100? 0010 1011 802bh pwmc2 lvr (low voltage reset)* 100? 0011 0000 8030h port3 hds port3 i/o high driving set** 100? 0011 0010 8032h port1 hds port1 i/o high driving set** 100? 00101000 8028h spicon eeprom control & setup 100? 0010 1001 8029h opcode eeprom opcode 100? 0010 1110 802eh dataw_h eeprom write high byte 100? 0010 1111 802fh dataw_l eeprom write low byte 100? 0010 1100 802ch datar_h eeprom read high byte 100? 0010 1101 802dh datar_l eeprom read low byte note : * lvr (low voltage reset) address : 802bh, read/write msb lsb bit 7 bit 6 bit5 bit 4 bit 3 bit 2 bit1 bit 0 lvr[7] lvr[6] reserved lvr[7] : if lvr[7] write ?1?, low voltage reset function enable. default is ?0?, low voltage reset function disable. lvr[6] : if lvr[6] write ?1?= 2.1v reset. if lvr[6] write ?0?= 2.8v reset. default is ?0?= 2.8v reset. ** port i/o high driving set if write ?0? = set i/o to high driving current mode. if write ?1? = set i/o to normal driving current mode. default is set ?1?. port 3 high driving address : 8030h msb lsb bit 7 bit 6 bit5 bit 4 bit 3 bit 2 bit1 bit 0 port3.7 port3.5 port3.4 port3.3 port3.2 port3.1 port3.0 port 1 high driving address : 8032h msb lsb bit 7 bit 6 bit5 bit 4 bit 3 bit 2 bit1 bit 0 port1.7 port1.6 port1.5 port1.4 port1.3 port1.2 port1.1 port1.0
te ch tm preliminary t81l0010b tm technology inc. reserves the right p. 10 publication date: jan. 2006 to change products or specifications without notice. revision:a 9.3. eeprom interface the eeprom interface timing is fully compatible with 93c46. to access or send data from/to t81l0010b , 6 registers are going to be controlled. eeprom register control default -- -- -- -- -- b2: r/w b1: r/w b0: r/w spicon 00h -- -- -- -- -- epdiv1 epdiv0 epst w opcode 00h - - - - - - - dataw_h dataw_l 00h datar_h dataw_l 00h spicon: msb lsb bit 7 bit 6 bit5 bit 4 bit 3 bit 2 bit1 bit 0 epdiv1 epdiv0 epst epst: start eeprom timing. ?1? to start and will be auto cleared after timing finish. epdiv[1..0]: divide input clock into eeprom system clock. 10: divide by 64 01: divide by 32 else: divide by 16 opcode msb lsb bit 7 bit 6 bit5 bit 4 bit 3 bit 2 bit1 bit 0 op code address instruction set op code address input data read 10 a5-a0 wen (write enable) 00 11xxxx write 01 a5-a0 d15-d0 wrall (write all registers) 00 01xxxx d15-d0 wds (write disable) 00 00xxxx erase 11 a5-a0 eral 00 10xxxx
te ch tm preliminary t81l0010b tm technology inc. reserves the right p. 11 publication date: jan. 2006 to change products or specifications without notice. revision:a 9.4. i/o ports port1 port 1 is an 8-bit bi-directional i/o port with internal pull-ups. port 1 output buffers can sink/source four external ttl device inputs. when port 1 pins are written as 1?s, these pins are pulled high by the internal pull-ups and can be used as inputs. as inputs, port 1 pins that are externally being pulled low will source current because of the internal pull-ups. port 3 port 3 is an 8-bit bi-directional i/o port with internal pull-ups. port 3 output buffers can sink/source four external ttl device inputs. when port 3 pins are written as 1?s, these pins are pulled high by the internal pull-ups and can be used as inputs. as inputs, port 3 pins that are externally being pulled low will source current because of the internal pull-ups. port 3 also serves the functions of various special features, as listed below: p3.0 rxd (serial input port) p3.1 txd (serial output port) p3.2 int0 (external interrupt 0) p3.3 int1 (external interrupt 1) p3.4 t0 (timer 0 external input) p3.5 t1 (timer 1 external input) p3.7 general purpose i/o only
te ch tm preliminary t81l0010b tm technology inc. reserves the right p. 12 publication date: jan. 2006 to change products or specifications without notice. revision:a watchdog timer the watchdog timer is a 16-bit counter that is incremented once every 24 or 384 clock cycles. after an external reset the watchdog timer is disabled and all registers are set to zeros. watchdog timer structure the watchdog consists of 16-bit counter wdt, reload register wdtrel, prescalers by 2 and by 16 and control logic. watchdog block diagram start procedure there are two ways to start the watchdog. one method, called hardware automatic start, is based on examining the level of signal swd during active internal rst signal. when this condition is met, the watchdog will start running automatically with default settings (all registers set to zeros).when this criterion is not met during active internal rst signal, a programmer ca n start the watchdog later. it will occur when signal swd becomes active. once the watchdog is started it cannot be stopped unless internal rst signal becomes active. when wdt registers enters the state 7cffh , asynchronous wdts signal will become active. the signal wdts sets the bit 6 in ip0 register and requests reset state. the wdts is cleared either by rst signal or ch ange of the state of the wdt timer. refreshing the watchdog timer the watchdog timer must be refreshed regularly to prevent reset request signal from becoming active. this requirement imposes obligation on the programmer to issue two followed instructions. the first instruction sets wdt and the second one swdt. the maximum allowed delay between settings of the wdt and swdt is 12 clock cycles. while this period has expired and swdt has not been set, wdt is automatically reset, otherwise the watchdog timer is reloaded with the content of the wdtrel register and wdt is automatically reset. /2 /16 fclk/12 wdtl wdth wdts control logic swd wdt swdt wdtrel 0 7 814 0 76
te ch tm preliminary t81l0010b tm technology inc. reserves the right p. 13 publication date: jan. 2006 to change products or specifications without notice. revision:a special function registers a) interrupt enable 0 register (ien0) the ien0 register (address : a8) msb lsb eal wdt et2 es0 et1 ex1 et0 ex0 the ien0 bit functions bit symbol function ien0.6 wdt watchdog timer refresh flag. set to initiate a refresh of the watchdog timer. must be set directly before swdt is set to prevent an unintentional refresh of the watchdog timer. the wdt is reset by hardware 12 instruction cycles after it has been set. note: other bits are not used to watchdog control the ien0 bit functions b) interrupt enable 1 register (ien1) the ien1 register (address : b8) msb lsb - swdt pt2 ps pt1 px1 pt0 px0 the ien1 bit functions bit symbol function ien1.6 swdt watchdog timer start refresh flag. set to active/refresh the watchdog timer. when directly set after setting wdt, a watchdog timer refresh is performed. bit swdt is reset by hardware 12 instruction cycles after it has been set. pay attention that when write ien1.6, it write the swdt bit, when read ien1.6, we will read out the wdts bit. ie. watch dog timer status flag. set by hardware when the watchdog timer was started. c) watchdog timer reload register (wdtrel) the wdtrel register ( address : 86 ) msb lsb 7 6 5 4 3 2 1 0 the wdtrel bit functions bit symbol function wdtrel.7 7 prescaler select bit. when set, the watchdog is clocked through an additional divide-by-16 prescaler wdtrel.6 t0 wdtrel.0 6-0 seven bit reload value for the high-byte of the watchdog timer. this value is loaded to the wdt when a refresh is triggered by a consecutive setting of bits wdt and swdt the wdtrel register can be loaded and read any time
te ch tm preliminary t81l0010b tm technology inc. reserves the right p. 14 publication date: jan. 2006 to change products or specifications without notice. revision:a wdt reset a high on reset pin or watchdog reset request for two clock cycles while the oscillator is running resets the device. diagram reset timing a) external hardware reset figure external reset timing **note: clk: external clock input tclk: clock period reset: external reset input rst: internally generated reset signal b) watchdog timer reset figure watchdog reset timing **note: clk: external clock input tclk: clock period wdt: watchdog timer registers wdts: watchdog timer status flag reset: external reset input rst: internally generated reset signal wdts_ff reset_ff rst wdts reset clk rst_ff
te ch tm preliminary t81l0010b tm technology inc. reserves the right p. 15 publication date: jan. 2006 to change products or specifications without notice. revision:a 10. timing diagram ale psen po r t0 po r t2 a0-a7 a8-a15 t lh ll t avll t lliv t llpl t pliv t plph t lla x t aviv in s t r in a 0 -a 7 a8-a15 ext ernal program memory read cycl e ale psen po r t0 po r t2 a0-a7 fro m ri or dpl a 8-a 15 fro m dph t lh ll t avll t lld v t avdv dat a in a 0 -a 7 a8-a15 ext ernal dat a memory read cycl e rd t whlh t rlrh t rldv t llw l
te ch tm preliminary t81l0010b tm technology inc. reserves the right p. 16 publication date: jan. 2006 to change products or specifications without notice. revision:a s1.........s6 s1.........s6 s1.........s6 s1.........s6 s1.........s6 s1.........s6 s1.........s6 s1.........s6 s1.........s6 s1.........s6 ale d0 d1 d2 d3 d4 d5 d6 d7 rxd txd d0 d1 d2 d3 d4 d5 d6 d7 rxd txd receive shift write to scon, clear ri ri receive write to sbuf send shift serial port mode 0 transmit ale psen po r t0 po r t2 a0-a7 fro m ri or dpl a 8-a 15 fro m dph t lh ll t avll dat a out a0-a7 a8-a15 ext ernal dat a memory wri t e cycl e wr t whlh t wlwh t avw l t llw l t lla x
te ch tm preliminary t81l0010b tm technology inc. reserves the right p. 17 publication date: jan. 2006 to change products or specifications without notice. revision:a tx d0 d1 d2 d3 d4 d5 d6 d7 txd ti shift ri receive write to sbuf send shift serial port mode 1 transmit stop bit data start bit rx d0 d1 d2 d3 d4 d5 d6 d7 rxd stop bit start bit tx d0 d1 d2 d3 d4 d5 d6 d7 txd ti shift ri receive write to sbuf send shift serial port mode 2 transmit stop bit data start bit rx d0 d1 d2 d3 d4 d5 d6 d7 rxd stop bit start bit tb8 tb8
te ch tm preliminary t81l0010b tm technology inc. reserves the right p. 18 publication date: jan. 2006 to change products or specifications without notice. revision:a package dimensions lqfp-32 package
te ch tm preliminary t81l0010b tm technology inc. reserves the right p. 19 publication date: jan. 2006 to change products or specifications without notice. revision:a

▲Up To Search▲

Price & Availability of T81L0010B-AL

	To Download T81L0010B-AL Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .