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| preliminary product information this document contains information for a new product. cirrus logic reserves the right to modify this product without notice. 1 copyright ? cirrus logic, inc. 2000 (all rights reserved) p.o. box 17847, austin, texas 78760 (512) 445 7222 fax: (512) 445 7581 http://www.cirrus.com CS5451 six-channel delta-sigma analog-to-digital converter features l synchronous sampling l on-chip 1.2 v reference (25 ppm/c typ) l power supply configurations: C va+ = +3 v; va- = -2 v; vd+ = +3 v C supply tolerances 10% l power consumption C 20 mw typical at vd+ = +3 v l simple four-wire serial interface C high-speed dma capability l charge pump driver output generates negative power supply. l ground-referenced bipolar inputs description the CS5451 is a highly integrated delta-sigma ( ds) an- alog-to-digital converter (adc) developed for the power measurement industry. the CS5451 combines six ds adcs, decimation filters, and a serial interface on a sin- gle chip. the CS5451 interfaces directly to a current transformer or shunt to measure current, and resistive divider or transformer to measure voltage. the product features a serial interface for communication with a mi- cro-controller or dsp. the product is initialized and fully functional upon reset, and includes a voltage reference. ordering information: CS5451-bs -40 c to +85 c 28-pin ssop vrefin vrefout iin1+ iin1- vin1+ vin1- vin2+ vin2- vin3+ vin3- iin2+ iin2- iin3+ iin3- va+ vd+ agnd se fso sdo sclk voltage reference serial interface reset 4th order ds modulator 2nd order ds modulator decimation filter decimation filter 4th order ds modulator 2nd order ds modulator decimation filter decimation filter 4th order ds modulator 2nd order ds modulator decimation filter decimation filter x1, 20 x1 x1 x1, 20 x1 x1, 20 x1 gain cpd owrs xin dgnd va- clock pulse output regulator jul 00 ds458pp3
CS5451 2 ds458pp3 table of contents 1. characteristics and specifications ......................................................................... 3 analog characteristics ............................................................................................... 3 analog characterisitcs ............................................................................................... 4 digital characteristics ................................................................................................ 4 recommended operating conditions ...................................................................... 4 absolute maximum ratings .......................................................................................... 5 switching characteristics ......................................................................................... 6 2. general description ........................................................................................................ 7 2.1. theory of operation ...................................................................................................... .... 7 2.2. performing measurements................................................................................................ 7 2.3. high rate digital filters ................................................................................................ .... 8 2.4. serial interface......................................................................................................... ......... 8 2.5. system initialization .................................................................................................... ...... 9 2.6. analog inputs ............................................................................................................ ........ 9 2.7. voltage reference ........................................................................................................ .... 9 2.8. power supply............................................................................................................. ....... 9 3. pin description............................................................................................................ ...... 10 4. package dimensions........................................................................................................ 1 2 list of figures figure 1. serial port timing................................................................................................... .......... 6 figure 2. typical connection diagram ........................................................................................... .7 figure 3. serial port data transfer ............................................................................................ ..... 8 figure 4. generating va- with a charge pump............................................................................... 9 contacting cirrus logic support for a complete listing of direct sales, distributor, and sales representative contacts, visit the cirrus logic web site at: http://www.cirrus.com/corporate/contacts/ preliminary product information describes products which are in production, but for which full characterization data is not yet available. advance product infor- mation describes products which are in development and subject to development changes. cirrus logic, inc. has made best effort s to ensure that the information contained in this document is accurate and reliable. however, the information is subject to change without notice and is provi d ed as is without warranty of any kind (express or implied). no responsibility is assumed by cirrus logic, inc. for the use of this information, nor for inf ringements of patents or other rights of third parties. this document is the property of cirrus logic, inc. and implies no license under patents, copyrights, tradem arks, or trade secrets. no part of this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electron ic, mechanical, photographic, or otherwise) without the prior written consent of cirrus logic, inc. items from any cirrus logic website or disk may be printed for use by the user. however, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form o r by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of cirrus logic, inc.furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of cirrus logic, inc. the names of products of cirrus logic, inc. or ot her vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. a list of cirrus logic, inc. trade- marks and service marks can be found at http://www.cirrus.com. CS5451 ds458pp3 3 1. characteristics and specifications analog characteristics (t a = -40 c to +85 c; +2.7v < va+ < +3.5v; +2.7v < vd+ < +3.5v; va- = -2 v 10%; external vref+ = 1.2 v; xin = 4.000 mhz; agnd, dgnd = 0.0v.)(see notes 1 and 2) notes: 1. specifications guaranteed by design, characterization, and/or test. 2. analog signals are relative to agnd and digital signals to dgnd unless otherwise noted. 3. effective input impedance (eii) varies with clock frequency (xin) and input capacitance (ic) eii = 1/(ic*xin/4) parameter symbol min typ max unit accuracy (all channels) total harmonic distortion thd 74 - - db common mode rejection (dc, 50, 60 hz) cmrr 80 - - db common mode + signal on input va- - va+ v input sampling rate - xin/4 - hz analog inputs (current channels) differential input voltage range gain=20 gain=1 iin -40 -800 - - +40 +800 mv mv bipolar offset gain=20 gain=1 vos vos - - 0.500 10 1 20 mv mv crosstalk to any other channel at full-scale (50, 60 hz) - - -120 db input capacitance gain = 20 gain = 1 ic ic - - - - 20 1 pf pf effective input impedance (note 3) gain=20 gain=1 eii eii 50 - - 500 - 600 k w k w noise (referred to input) 0-60 hz gain=20 gain=1 0-1 khz gain=20 gain=1 0-2 khz gain=20 gain=1 - - - - - - - - - - - - 1 20 2.5 50 3.75 75 v rms v rms v rms v rms v rms v rms analog inputs (voltage channels) differential input voltage range iin -800 +800 mv bipolar offset gain=1 vos - 20 25 mv crosstalk to any other channel at full-scale (50, 60 hz) - - -120 db input capacitance ic - - 0.2 pf effective input impedance (note 3) eii - 3 4 m w noise (referred to input) 0-60 hz 0-1 khz 0-2 khz - - - - - - 20 50 75 v rms v rms v rms dynamic characteristics high rate filter output word rate owrs = 0 owrs = 1 owr owr - - xin/2048 xin/1024 - - hz hz CS5451 4 ds458pp3 analog characterisitcs (continued) notes: 4. all outputs unloaded. all inputs cmos level. digital characteristics (t a = -40 c to +85 c; +2.7v < va+ < +3.5v; +2.7v < vd+ < +3.5v; va- = -2 v 10%; agnd, dgnd = 0.0 v) (see notes 5) notes: 5. all measurements performed under static conditions. recommended operating conditions (agnd, dgnd = 0.0 v) parameter symbol min typ max unit reference output output voltage refout 1.15 - 1.25 v temperature coefficient - 20 50 ppm/c load regulation (output current 1 m a source or sink) d v r - 6 10 mv power supply rejection psrr 60 - - db reference input input voltage range vref+ 1.15 1.2 1.25 v input capacitance - - 10 pf input cvf current - - 1 a power supplies power supply currents i a+ i d+ psca pscd - - - - 3 4 ma ma power consumption (note 4) pc - - 27 mw power supply rejection (50, 60 hz) psrr 60 - - db parameter symbol min typ max unit high-level input voltage v ih 0.6 vd+ - vd+ v low-level input voltage v il 0.0 - 0.8 v high-level output voltage i out = -5.0 ma v oh (vd+) - 1.0 - - v low-level output voltage i out = 5.0 ma v ol --0.4v input leakage current i in -110a 3-state leakage current i oz --10a digital output pin capacitance c out -9-pf parameter symbol min typ max unit dc power supplies positive digital positive analog negative analog vd+ va+ va- 2.7 2.7 -2.2 3.0 3.0 -2.0 3.5 3.5 -1.8 v v v voltage reference input vref+ - 1.2 - v CS5451 ds458pp3 5 absolute maximum ratings (agnd, dgnd = 0.0 v; see note 6.) notes: 6. all voltages with respect to agnd. 7. applies to all pins including continuous over-voltage conditions at the analog input (ain) pins. 8. transient current of up to 100 ma will not cause scr latch-up. maximum input current for a power supply pin is 50 ma. 9. total power dissipation, including all input currents and output currents. warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. parameter symbol min typ max unit dc power supplies positive digital positive analog negative analog vd+ va+ va- -0.3 -0.3 -2.5 - - +3.5 +3.5 -0.3 v v v input current, any pin except supplies (note 7 and 8) i in --10ma output current i out --25ma power dissipation (note 9) pdn - - 500 mw analog input voltage all analog pins v ina va- - 0.3 - (va+) + 0.3 v digital input voltage all digital pins v ind -0.3 - (vd+) + 0.3 v ambient operating temperature t a -40 - 85 c storage temperature t stg -65 - 150 c CS5451 6 ds458pp3 switching characteristics (t a = -40 c to +85 c; va+, vd+ = 3.0 v 10%; va- = -2 v 10%; dgnd = agnd = 0.0 v; logic levels: logic 0 = 0.0 v, logic 1 = vd+; cl = 50pf)) notes: 10. device parameters are specified with a 4.000 mhz clock, owrs = 1. 11. specified using 10% and 90% points on wave-form of interest. output loaded with 50 pf. parameter symbol min typ max unit master clock frequency (note 10) xin 3 4.000 5 mhz master clock duty cycle - 40 - 60 % rise times any digital input (note 11) any digital output t rise - - - 50 1.0 - s ns fall times any digital input (note 11) any digital output t fall - - - 50 1.0 - s ns serial port timing serial clock frequency (note 10) owrs = 0 owrs = 1 sclk sclk - - 500 1000 - - khz khz serial clock pulse width high (note 10) pulse width low (note 10) t 1 t 2 - - 0.5 0.5 - - sclk sclk sclk falling to new data bit t 3 - - 50 ns fso falling to sclk rising delay (note 10) t 4 -0.5-sclk fso pulse width (note 10) t 5 -1-sclk se rising to output enabled t 6 - - 50 ns se falling to output in tri-state t 7 - - 50 ns se 6 t 6 t sdo sclk msb msb - 1 lsb t 2 t 1 t 3 fso 4 t 5 t figure 1. serial port timing CS5451 ds458pp3 7 2. general description the CS5451 is designed for 3-phase power meter applications and interfaces to a current transform- ers or shunt to measure current, and a resistive di- vider or transformer to measure voltage. the CS5451 combines six ds modulators and dec- imation filters, three channels assigned for current input that have programmable input gain amplifi- ers, and three channels assigned for voltage input. the CS5451 includes six decimation filters that output data at a 2000 hz or 4000 hz output word rate (owr). the device outputs data on a serial output port. 2.1 theory of operation the CS5451 is designed to operate from a single +3v supply and provides a 40 mv and 800 mv input range for the current channels and 800 mv range for the voltage channels. the CS5451 is de- signed to accommodate common mode + signal levels from va- to va+. figure 2 illustrates the CS5451 typical inputs and power supply connec- tions.. 2.2 performing measurements the converter outputs are transferred in 16-bit signed data formats as a percentage of full scale. va+ vd+ vin1+, vin2+, or vin3+ vin1-, vin2-, or vin3- iin1+, iin2+, or iin3+ iin1-, iin2-, or iin3- agnd dgnd refin refout optional external reference v phase + i -2 v phase va- +3 v 1.2 v figure 2. typical connection diagram CS5451 8 ds458pp3 2.3 high rate digital filters if the owrs pin is set to logic low, the high-rate filters are implemented as fixed sinc^3 filters with the following transfer function this filter samples the modulator bit stream at xin/8 hz and decimates to xin/2048 hz. if the owrs pin is set to logic high, then the trans- fer function is the above filter samples the modulator bit stream at xin/8 hz and decimates to xin/1024 hz. 2.4 serial interface the CS5451 communicates with a target device via a serial data output port. data is provided on the sdo output synchronous with the sclk output. a third output, fso, is a framing signal used to signal the start of output data. these three outputs will be driven as long as the se (serial enable) input is held high. otherwise, these outputs will be high imped- ance. data out (sdo) changes as a result of sclk fall- ing, and always outputs valid data with sclk ris- ing. when data is being transferred, the sclk frequency is either 1/8 of the xin input frequency (when owrs is held low) or 1/4 of the xin input hz () 1z 256 C C 1z 1 C C --------------------- - ? ? ?? 3 = hz () 1z 128 C C 1z 1 C C --------------------- - ? ? ?? 3 = sclk fso sdo channel 1 v channel 2 i channel 3 i channel 2 v channel 3 v channel 1 i sclk fso sdo 12 15 14 13 0 1 2 3 4 5 6 7 8 9 10 11 15 14 13 12 11 10 9 8 7 65 4321 channel 1 ( i ) channel 1 ( v ) 15 14 13 figure 3. serial port data transfer CS5451 ds458pp3 9 frequency (when owrs is held high). any other time, sclk is held low. the framing signal (fso) output is normally low, but produces a high level pulse lasting one sclk period at the end of every conversion. note: sclk is not active during fso high. for 96 sclk periods after fso falls, sclk is ac- tive and sdo produces valid output. six channels of 16 bit data are output, msb first. voltage and current measurements are output (in that order) for three phases. sclk will then be held low until the next sample period. 2.5 system initialization when power to the CS5451 is applied, the chip must be held in a reset condition using the reset input. a hardware reset is initiated when the reset pin is forced low with a minimum pulse width of 50 ns. 2.6 analog inputs the analog inputs of the CS5451 are bipolar volt- age inputs: three voltage channel inputs vin(1-3) and three current channel inputs iin(1-3). the CS5451 accommodates a full scale range of 40 mv or 800 mv on the current channels and 800 mv on the voltage channels. 2.7 voltage reference the CS5451 is specified for operation with a +1.2 v reference between the vrefin and agnd pins. the converter includes an internal 1.2 v reference (50 ppm/c drift) that can be used by connecting the vrefout pin to the vrefin pin of the de- vice. if higher accuracy/stability is required, an ex- ternal reference can be used. 2.8 power supply charge pump. the low, stable analog power consumption and su- perior supply rejection of the CS5451 allow for the use of a simple charge-pump negative supply gen- erator. the use of a negative supply alleviates the need for level shifting of the analog inputs. the cpd pin and capacitor c1 provide the necessary analog supply current as shown in figure 4. the schottky diodes d1 and d2 are chosen for their low forward voltages and high-speed capabilities. the capacitor c2 provides the required charge storage and bypassing of the negative supply. the cpd output signal provides the charge pump driver sig- nal. the frequency of the charge pump driver sig- nal is synchronous to xin. the nominal average frequency is 1 mhz. the level on the va- pin is fed back internally so that the cpd output will regulate the va- level to -2/3 of va+ level. agnd bat 85 d1 c1 40 nf c2 cpd va- bat 85 1 f d2 figure 4. generating va- with a charge pump CS5451 10 ds458pp3 3. pin description clock generator xin - master clock input control pins and serial data i/o se - serial port enable. when se is low, the output pins of the serial port are 3-stated. sdo - serial port output. data will be at a rate determined by sclk. fso - frame signal output. framing signal output for data transfer from sdo pin. sclk - serial clock output. a clock signal on this pin determines the output rate of data for sdo pin. rate of sclk is determined by xin frequency and state of owrs input pin. reset - reset. when reset is taken low, all internal registers are set to their default states. gain - input gain control. sets input gain for current channels. a logic high sets internal gain to 1, a logic low level sets the gain to 20. if no connection is made to this pin, it will default to logic low level (through internal 200k resistor to dgnd). owrs - output word rate select. when owrs is set to logic low, the output word rate (owr) at sdo pin is xin/2048 (hz). when set to logic high, the owr at sdo pin is xin/1024 (hz). if no connection is made to this pin, then owrs will default to logic low level (through internal 200k resistor to dgnd). 2 3 4 1 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 serial clock sclk vd+ digital supply serial data output sdo dgnd digital ground frame sync fso cpd charge pump drive serial port enable se xin master clock current input gain gain reset reset analog ground agnd owrs output word rate select reference input vrefin vin1+ differential voltage input 1 reference output vrefout vin1- differential voltage input 1 positive analog supply va+ iin1+ differential current input 1 negative analog supply va- iin1- differential current input 1 differential voltage input 3 vin3+ vin2+ differential voltage input 2 differential voltage input 3 vin3- vin2- differential voltage input 2 differential current input 3 iin3+ iin2+ differential current input 2 differential current input 3 iin3- iin2- differential current input 2 CS5451 ds458pp3 11 measurement and reference input iin(1-3) +, iin(1-3) - - differential current inputs. differential analog input pins for current channels. vin(1-3)+, vin(1-3)- - differential voltage inputs. differential analog input pins for voltage channels. vrefout - voltage reference output. the on-chip voltage reference is output from this pin. the voltage reference has a nominal magnitude of 1.2 v and is referenced to the agnd pin on the converter. vrefin - voltage reference input. the voltage input to this pin establishes the voltage reference for the on-chip modulator. power supply connections va+ - positive analog supply. the positive analog supply is nominally +3 v 10% relative to agnd. va- - negative analog supply. the negative analog supply is nominally -2 v 10% relative to agnd. agnd - analog ground. the analog ground pin for input signals. vd+ - positive digital supply. the positive digital supply is nominally +3 v 10% relative to dgnd. dgnd - digital ground. the digital ground is typically at the same level as agnd. cpd - charge pump drive this output pin drives the external charge pump circuitry to create a negative supply voltage. CS5451 12 ds458pp3 4. package dimensions notes: 1. d and e1 are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2. dimension b does not include dambar protrusion/intrusion. allowable dambar protrusion shall be 0.13 mm total in excess of b dimension at maximum material condition. dambar intrusion shall not reduce dimension b by more than 0.07 mm at least material condition. 3. these dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips. inches millimeters note dim min nom max min nom max a -- -- 0.084 -- -- 2.13 a1 0.002 0.006 0.010 0.05 0.13 0.25 a2 0.064 0.069 0.074 1.62 1.75 1.88 b 0.009 -- 0.015 0.22 -- 0.38 2,3 d 0.390 0.4015 0.413 9.90 10.20 10.50 1 e 0.291 0.307 0.323 7.40 7.80 8.20 e1 0.197 0.209 0.220 5.00 5.30 5.60 1 e 0.022 0.026 0.030 0.55 0.65 0.75 l 0.025 0.0354 0.041 0.63 0.90 1.03 0 4 8 0 4 8 jedec #: mo-150 28l ssop package drawing e n 1 23 e b 2 a1 a2 a d seating plane e1 1 l side view end view top view ? notes ? |
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