View COREUART-RC_1938869.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

coreuart v4.2 handbook
actel corporation, mountain view, ca 94043 ? 2010 actel corporation. all rights reserved. printed in the united states of america part number: 50200095-2 release: october 2010 no part of this document may be copied or reproduced in any form or by any means without prior written consent of actel. actel makes no warranties with respect to this documentati on and disclaims any implied warranties of merchantability or fitness for a particular purpose. information in this doc ument is subject to change without notice. actel assumes no responsibility for any errors that may appear in this document. this document contains confidential proprietary informati on that is not to be disclosed to any unauthorized person without prior written cons ent of actel corporation. trademarks actel, actel fusion, igloo, libero, pigeon point, proasic, smartfusion and the associated logos are trademarks or registered trademarks of actel corporatio n. all other trademarks and service marks are the property of their respective owners.
coreuart v4.2 handbook revision 2 3 table of contents introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 core versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 supported families . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1 functional block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 device utilization and performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 programmable options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 tool flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 licensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 smartdesign . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 simulation flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 synthesis in libero ide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 place-and-route in libero ide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3 core interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 core parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 serial transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 serial receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 parity error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 overflow error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 framing error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 framing error in legacy mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 ordering codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 a list of document changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 b product support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 customer service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 actel customer technical support center . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 actel technical support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 website . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 contacting the customer technical support center . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

revision 2 5 introduction general description coreuart is a serial communication controller with a flexible serial data interface that is intended primarily for embedded systems. coreuart can be us ed to interface directly to industry standard uarts. coreuart is intentionally a subset of full uart capability to make th e function cost-effective in a programmable device. figure 1 illustrates the various usages of coreuart. case a in figure 1 represents the interface to an industry standard uart, such as an 8251 or a 16550. in case b, coreuart is transf erring data from the 8 051 to the system moni tor through the rs-232 interface and vice versa. core versions this handbook applies to coreuart v4.2. the rel ease notes provided with the core list known discrepancies between this handbook and the core release associated with the release notes. table 1 ? system block diagram de picting coreuart usage uart actel device industry standard uart tx rx clka clkb case a case b tx rx 8051 transmit 1 transmit 2 receive 1 receive 2 coreuart core429 core429 transceiver rs-232 system monitor
introduction 6 revision 2 supported families ? igloo ? ? iglooe ? igloo plus ? proasic ? 3 ? proasic3e ? proasic3l ? proasic plus ? smartfusion? ?fusion ? axcelerator ? ? rtax-s ? sx-a ? rtsx-s
revision 2 7 1 ? functional block description figure 1-1 shows the block diagram of the coreuart normal mode functionality. figure 1-2 on page 8 shows the block diagram of coreuart with fifo mo de functionality. the baud generator creates a divided down clock enable that correctly pace s the transmit and receive state machines. the function of the receive and transmit state ma chines is affected by the control inputs bit8, parity_en, and odd_n_even. these signals indicate to the state machines how many bits should be transmitted. in addition, the signal s suggest the type of parity and whether parity should be generated or checked. the activity of the state machines is paced by the outputs of the baud generator. to transmit data, it is first loaded into the transmit data buffer in no rmal mode, and into the transmit fifo in fifo mode. data can be loaded into the buffer unt il the txrdy signal is driven inactive. the transmit state machine will immediately begin to transmit data and will continue transmission until the data buffer is empty in normal mode, and until the transmit fifo is empty in fifo mode. the state machine first transmits a start bit, followed by the data (lsb first), then the parity (optional), and finally the stop bit. the data buffer is double-buffered in normal mode, so there is no loading latency. the receive state machine monitors the activity of the rx signal. once a start bit is detected, the receive state machine begins to store the data in t he receive buffer in normal mode and the receive fifo in fifo mode. when the transaction is complete, the rxrdy signal indicates that valid data is available. parity errors are reported on the parity_err signal (if enabled), and data overrun conditions are reported on the overflow signal. framing erro rs are reported on the framing_err signal. a framing error is defined as a missing stop bit detected by the uart receiver. figure 1-1 ? block diagram of coreua rt normal functionality rxdy data_out[7:0] txrdy data_in[7:0] parity_err overflow rx tx baud_val baud generator transmit state machine receive state machine data buffer parity_en bit8 odd_n_even data buffer framing_err
functional block description 8 revision 2 device utilization and performance utilization statistics for tar geted devices are listed in ta b l e 1 -1 and table 1-2 on page 9 . figure 1-2 ? block diagram of coreuart with fifo functionality txrdy data_in[7:0] tx baud_val baud generator transmit state machine receive state machine receive fifo parity_en bit8 odd_n_even transmit fifo rxdy data_out[7:0] parity_err overflow rx framing_err table 1-1 ? coreuart utilizati on in fifo mode family cells or tiles memory blocks utilization performance mhz sequential combinatorial total device total igloo iglooe igloo plus 116 192 308 2 agl600v5 2% 71 proasic3 proasic3e proasic3l 116 192 308 2 a3p600 5% 128 smartfusion 116 192 308 2 a2f500m3f 7% 118 fusion 116 192 308 2 afs600 2% 127 proasic plus 118 281 399 2 apa600 13% 68 axcelerator 171 215 386 2 ax250 9% 194 rtax-s 195 199 394 2 rtax250s 9% 153 sx-a 430 309 739 0 a54sx16a 51% 96 rtsx-s 432 308 740 0 rt54sx32s 26% 62 notes: 1. coreuart supports all standard baud rates, incl uding 110, 300, 1,200, 2,400, 4,800, 9,600, 19,200, 38,400, 57,600, 115, 200, 230,400, 460,800, and 921,600 baud. 2. the depth of the fifo for sx-a and rtsx-s is 16. for the other families, t he depth of the fifo is 256.
coreuart v4.2 handbook revision 2 9 programmable options there are four programmable inputs to coreuart: baud_val (baud rate), bit8 (number of data bits), parity_en (parity enable ), and odd_n_even (odd or even parity). number of data bits the input bit8 is used to define the number of valid data bits in the serial bitstream. the most significant bit is a ?don?t care? fo r the seven-bit case. parity parity is enabled/disabled with the input parity _en. when parity is enabled, the odd_n_even input defines the type of parity. table 1-2 ? coreuart utilization in normal mode family cells or tiles memory blocks utilization performance mhz sequential combinatorial total device total igloo iglooe igloo plus 84 167 251 0 agl600 2% 116 proasic3 proasic3e proasic3l 84 167 251 0 a3p600 4% 198 smartfusion 84 167 251 0 a2f500m3f 6% 200 fusion 84 167 251 0 afs600 2% 197 proasic plus 85 254 339 0 apa600 11% 89 axcelerator 86 108 194 0 ax500 5% 185 rtax-s 86 108 194 0 rtax250s 5% 138 sx-a 82 93 750 0 a54sx16sa 12% 138 rtsx-s 80 92 172 0 rt54sx32s 6% 87 note: coreuart supports all standard baud rates, in cluding 110, 300, 1,200, 2,400, 4,800, 9,600, 19,200, 38,400, 57,600, 115,200, 230,400, 460,800, and 921,600 baud.
functional block description 10 revision 2 baud rate this baud value is a function of the system cl ock and the desired baud rate. the value should be set according to eq 1-1 . eq 1-1 where and eq 1-2 the term baudval must be rounded to the nearest int eger. for example, a system with a 33 mhz system clock and a desired baud rate of 9,600 should have a baud_value of 214 decimal or d6 hex. so, to get the desired baud rate, the user should assign 16#d6 to baud_val input. clk = the frequency of the system clock in hertz baud rate = the desired baud rate baud rate clk baudval 1 + () 16 ------------------------------------------------ = baudval clk 16 baudrate ------------------------------------ 1 ? =
revision 2 11 2 ? tool flows licensing coreuart is licensed in two ways. depending on your license tool flow, functionality may be limited. obfuscated complete rtl code is provided for the core, allowing the core to be instantiated with smartdesign. simulation, synthesis, and lay out can be performed within libero ? integrated design environment (ide). the rtl code for the core is obfuscated 1 and some of the testbench source files are not provided; they are precompiled into the compiled simulation library instead. rtl complete rtl source code is provided for the core and testbenches. smartdesign coreuart is available for download in the smartd esign ip deployment design environment. the core can be configured using the configurati on gui within smartdesign, as shown in figure 2-1 . for more information on using smartdesign to instantiate and generate cores, refer to the using directcore in libero ide user's guide . 1. obfuscated means the rtl source files have had forma tting and comments removed, and all instance and net names have been replaced with random character sequences. figure 2-1 ? smartdesign coreuart configuration window
tool flows 12 revision 2 simulation flows the user testbench for coreuart is included in all releases. to run simulations, select the user te stbench flow within smartdesign and click generate design under the smartdesign menu. the user testbench is sele cted through the core testbench configuration gui. when smartdesign generates the libero ide projec t, it will install the user testbench files. to run the user testbench, set the design root to t he coreuart instantiation in the libero ide design hierarchy pane and click the simulation icon in the libero ide design flow window. this will invoke modelsim ? and automatically run the simulation. user testbench coreuart is provided with a user testbench ( figure 2-1 ) to demonstrate sample uart operation. the testbenches are available in both verilog and vhdl and contain two instances of coreuart connected to each other. the source code is made availabl e with obfuscated and rtl licenses of the core. the testbench contains the tests listed in ta b l e 2 - 1 . figure 2-2 ? verification testbench table 2-1 ? verification tests no. bit parity parity setting parity error over flow error framing error procedure call 1 8 enabled even no no no txrxtest 2 8 enabled odd no no no txrxtest 3 7 enabled even no no no txrxtest 4 7 enabled odd no no no txrxtest 5 8 disabled n/a no no no txrxtest 6 8 disabled n/a no no no txrxtest 7 7 disabled n/a no no no txrxtest 8 7 disabled n/a no no no txrxtest 9 8 enabled even yes no no paritytest 10 8 enabled odd yes no no paritytest 11 7 enabled even yes no no paritytest 12 7 enabled odd yes no no paritytest 13 8 enabled odd no yes no testoverflow 14 8 enabled odd no no yes n/a testbench make_uart1 make_uart2
coreuart v4.2 handbook revision 2 13 the procedure calls txrxtest, paritytest, and testoverfl ow are defined in the file tbpack.vhd. the top-level testbench, testbench.vhd, utilizes these proce dures to perform the corresponding tests listed in table 2-1 . refer to the source directory on the release cd for source code for the testbench. synthesis in libero ide click the synthesis icon in libero ide. the synthesis window appears, displaying the synplify ? project. set synplify to use the verilog 2001 standard if ver ilog is being used. to run synthesis, select the run icon. place-and-route in libero ide click the layout icon in libero ide to invoke designer. coreuart requires no special place-and-route settings.

revision 2 15 3 ? core interfaces signal descriptions for coreuart are given in ta b l e 3 - 1 . table 3-1 ? coreuart signals name 1 type description clk input main system clock reset_n input active lo w asynchronous reset data_in[7:0] input tra nsmit write data bus data_out[7:0] output receive read data bus wen input active low write enable. this signal indicates that the data presented on the data_in[7:0] bus should be registered by the transmit buffer/fifo logic. this signal should only be active for a single clock cycl e per transaction and should only be active when the txrdy signal is active. oen input active low read enable. this signal is us ed to indicate that the data on data_out[7:0] has been read and will reset the rxrdy bit and any error conditions (overflow or parity_err). csn input active low chip select. the csn signal qualifies both the wen and oen signals. for embedded applications, this signal should be tied to logic 0. bit8 input control bit for data bit width for both rece ive and transmit functions. when bit8 is logic 1, the data width is 8 bits; otherwise, the data wid th is 7 bits, data defined by data_in[7] is ignored, and data_out[7] is ?don?t care.? parity_en input control bit to enable parity for both receive and transmit functions. parity is enabled when the bit is set to logic 1. odd_n_even input control bit to define odd or even parity for both rece ive and transmit functions. when the parity_en control bit is set, a 1 on this bit indicates odd parity and a 0 indicates even parity. baud_val[12:0] input 13-bit control bus used to define the baud rate txrdy output status bit; when set to logic 0, indicates that the transmit data buffer/fifo is not available for additional transmit data. rxrdy output status bit; when set to logic 1, indicates that data is available in the receive data buffer/fifo to be read by th e system logic. the data buff er/fifo controller must be notified of the receipt by simultaneous activation of the oen and csn signals to prevent erroneous overflow conditions. parity_err output status bit; when set to logic 1, indicates a parity error during a receive transaction. this bit is synchronously cleared by simultaneo us activation of the oen and csn signals. overflow output status bit; when set to logic 1, indica tes that a receive overflow has occurred. this bit is synchronously cleared by simultaneous activation of the oen and csn signals. rx input serial receive data notes: 1. active low signals are designated with a trailing uppercase n . 2. when rx_fifo is enabled, parity_err is asserted when a parity error occurs, but deasserted before coreuart receives the next byte. it is the user's res ponsibility to monitor the parity_err signal (for example, treat it as an interrupt signal), as it is non-pers istent when rx_fifo = 1. framing_err should be treated similarly, when rx_fifo = 1.
core interfaces 16 revision 2 core parameters coreuart configurable options there are a number of configurable options that apply to coreuart, as shown in ta b l e 3 - 2 . if a configuration other than the default is required, the user should use the configuration dialog box in coreconsole to select appropriate values for the configurable options. tx output serial transmit data framing_err output status bit; when set to logic 1, i ndicates that a framing error (missing stop bit) has occurred. this bit is synchronously cleare d by simultaneous activation of the oen and csn signals. table 3-1 ? coreuart signals (continued) name 1 type description notes: 1. active low signals are designated with a trailing uppercase n . 2. when rx_fifo is enabled, parity_err is asserted when a parity error occurs, but deasserted before coreuart receives the next byte. it is the user's res ponsibility to monitor the parity_err signal (for example, treat it as an interrupt signal), as it is non-pers istent when rx_fifo = 1. framing_err should be treated similarly, when rx_fifo = 1. table 3-2 ? coreuart configurable options configurable options default setting description tx_fifo disabled enables or disables transmit fifo rx_fifo disabled enables or disables receive fifo family proasic3 selects target family. must be set to match the supported fpga family. 8 ? sx-a 9 ? rtsxs 11 ? axcelerator 12 ? rtax-s 14 ? proasic plus 15 ? proasic3 16 ? proasic3e 17 ? fusion 18 ? smartfusion 20 ? igloo 21 ? iglooe 22 ? proasic3l 23 ? igloo plus rx_legacy_mode disabled when di sabled, the rxrdy signal is synchronized with the framing_err output, which occurs after the stop bit. when enabled (legacy mode), the rxrdy signal is asserted after all data bits have been received, but before the stop bit. use_soft_fifo disabled when disabled, the fifo is implemented using a device-specific hard macro. when enabled, a 16-byte fi fo is implemented in fpga logic instead. rtax and rtsx-s devices us e this soft fifo by default.
revision 2 17 4 ? timing diagrams the uart waveforms can be broken down into a few ba sic functions: transmit data, receive data, and errors. figure 4-1 shows serial transmit signals, and figure 4-2 on page 18 shows serial receive signals. figure 4-3 on page 18 and figure 4-4 on page 19 show the parity and overflow error cycles, respectively. the number of clock cycles required is equal to the clock frequen cy divided by the baud rate. all waveforms assume that eight bits of data and parity are enabled. all waveforms, except "framing error" on page 19 , assume legacy mode is enabled. serial transmit notes: 1. a serial transmit is initiated by writing data in to coreuart. this is accomplished by providing valid data and asserting the wen and csn signals. the tx rdy signal will become inactive for one cycle while the data is being transferred from the transmit hold register to the transmit register that begins the serial transfer. 2. the transmission begins with a start bit, followed by data bits 0 through 6, the optional seventh bit, the optional parity bit, and finally the stop bit. 3. because the uart is double-buf fered, data can be queued in the transmit hold register (cycle 7). the txrdy line, when low, indicates that no more data can be transferred to the uart. once the previous serial transfer is complete, the da ta in the transmit hold register is passed to the transmit register, and the transfer begins. the txrdy line is also a sserted, indicating that the next data byte can be loaded. figure 4-1 ? serial transmit baud_clk wen csn oen txrdy tx d0 d1 d2 d3 d4 d5 d6 d7 par start bit start bit stop bit 13 14 15 16 56789101112 1234 17 18 data_in data data
timing diagrams 18 revision 2 serial receive notes: 1. coreuart continuously monitors the rx line, polling for a start bit. once the start bit is detected, coreuart re gisters the data stream. the optional pari ty bit is also registered and checked. a start bit is defined as logic 0-bit va lue on the rx line when the core is idle. 2. the data is then loaded into the receive hold buf fer, and the rxrdy signal is asserted. the rxrdy signal will remain asserted until the data is read ex ternally, indicated by the simultaneous assertion of csn and oen. parity error notes: 1. when a parity error occurs, the parity_err signal is asserted. 2. the error is cleared by the same method used to read the data, simultaneous assertion of csn and oen. figure 4-2 ? serial receive 13 14 15 16 56 789101112 1234 baud_clk rx wen csn data_out oen parity_err overflow rxrdy d0 d1 d2 d3 d4 d5 d6 d7 par stop bit start bit data figure 4-3 ? parity error 16 13 14 15 56 789101112 1234 d0 d1 d2 d3 d4 d5 d6 d7 par stop bit start bit data baud_clk rx wen csn data_out oen parity_err overflow rxrdy
coreuart v4.2 handbook revision 2 19 overflow error notes: 1. when a data overflow error occurs, the overflow signal is asserted. 2. the previous data is held and the new data is lost . the error is cleared by the same method used to read the data, simultaneous assertion of csn and oen. framing error notes: 1. legacy mode is disabled in this timing diagram. 2. in normal (non-legacy) mode, rxrdy and framing_err are synchronized. they are asserted in the same clock cycle. the error is cleared using a read operation ? simultaneous assertion of oen and csn. figure 4-4 ? overflow error 13 14 15 16 56 789101112 1234 baud_clk rx wen csn data_out oen parity_err overflow rxrdy d0 d1 d2 d3 d4 d5 d6 d7 par stop bit start bit previous data figure 4-5 ? framing error baud_clk rx wen csn data_out oen framing_err overflow rxrdy missing stop bit start bit 13 14 15 56 789101112 1234 16 d0 d1 d2 d3 d4 d5 d6 d7 par
timing diagrams 20 revision 2 framing error in legacy mode notes: 1. legacy mode is enabled in this timing diagram. 2. in legacy mode, rxrdy is asserted one cycle before framing_err is asserted. the error is cleared using a read operation: simu ltaneous assertion of oen and csn. figure 4-6 ? framing error in legacy mode 13 14 15 56 789101112 1234 16 d0 d1 d2 d3 d4 d5 d6 d7 par baud_clk rx wen csn data_out oen framing_err overflow rxrdy start bit missing stop bit
revision 2 21 5 ? ordering information ordering codes coreuart can be ordered through your local actel sa les representative. it should be ordered using the following number scheme: coreuart-xx, where xx is listed in ta b l e 5 - 1 . table 5-1 ? ordering codes xx description om rtl for obfuscated rtl ? multiple-use license rm rtl for rtl source ? multiple-use license note: coreuart-om is included free with a libero ide license.

revision 2 23 a ? list of document changes the following table lists critical changes that were made in each revision of the document. revision changes page revision 2 (october 2010) the core version was updated to v4.2. 6 smartfusion and proasic3e were added to the "supported families" section . 6 smartfusion was added to table 1-1 ? coreuart utilization in fifo mode and table 1-2 ? coreuart utilization in normal mode . 8 , 9 eq 1-2 is new. 10 the "tool flows" chapter was rewritten. the ?testbench operation? chapter was deleted because its relevant content was incorporated into the "tool flows" chapter. 11 signal names were made all upper case. the second note for table 3-1 ? coreuart signals was revised to add, "framing_err should be treated similarly, when rx_fifo = 1." 15 smartfusion was added to table 3-2 ? coreuart configurable options . 16 revision 1 (february 2009) added framing error (framing_err signal) support. 7 updated the "tool flows" chapter with smartdesign flow. 11 updated table 3-1 ? coreuart signals to include framing_err signal. 15 updated table 3-2 ? coreuart configurable options with new configurable options. 16 added framing error and framing error in legacy mode timing diagrams. 19 ? 20

revision 2 25 b ? product support actel backs its products with various support services includi ng customer service, a customer technical support center, a web site, an ftp site, electronic mail, and worldwide sales offices. this appendix contains information about contacting actel and using these support services. customer service contact customer service for non-technical product su pport, such as product pricing, product upgrades, update information, order st atus, and authorization. from northeast and north central u.s.a., call 650.318.4480 from southeast and s outhwest u.s.a., call 650. 318.4480 from south central u.s.a., call 650.318.4434 from northwest u.s.a., call 650.318.4434 from canada, call 650.318.4480 from europe, call 650.318.4252 or +44 (0) 1276 401 500 from japan, call 650.318.4743 from the rest of the world, call 650.318.4743 fax, from anywhere in the world 650.318.8044 actel customer technical support center actel staffs its customer technical support center with highly skilled engineers who can help answer your hardware, software, and design questions. the customer technical support center spends a great deal of time creating application notes and answers to faqs. so, before you contact us, please visit our online resources. it is very likely we have already answered your questions. actel technical support visit the actel customer support website ( www.actel.com/support/search/default.aspx ) for more information and support. many answers available on the searchable web resource include diagrams, illustrations, and links to other resources on the actel web site. website you can browse a variety of technical and non -technical information on actel?s home page, at www.actel.com . contacting the customer technical support center highly skilled engineers staff the technical support c enter from 7:00 a.m. to 6:00 p.m., pacific time, monday through friday. several ways of contacting the center follow: email you can communicate your technical questions to ou r email address and receive answers back by email, fax, or phone. also, if you have design problems, y ou can email your design files to receive assistance. we constantly monitor the email account throughout the day. when sending your request to us, please be sure to include your full name, company name, and your contact information for efficient processing of your request.
product support 26 revision 2 the technical support email address is tech@actel.com . phone our technical support center answers all calls. th e center retrieves informa tion, such as your name, company name, phone number and your question, and then issues a case number. the center then forwards the information to a queue where the first available application engineer receives the data and returns your call. the phone hours are from 7:00 a.m. to 6:00 p.m., pacific time, monday through friday. the technical support numbers are: 650.318.4460 800.262.1060 customers needing assistance outside the us time zones can either contact technical support via email (tech@actel.com) or contact a local sales office. sales office listings can be found on the website at www.actel.com/company/contact/default.aspx .
revision 2 27 index a actel electronic mail 25 telephone 26 web-based technical support 25 website 25 b baud generator 7 block diagram 7 fifo mode 8 normal mode 7 buffers receive 7 transmit 7 c configurable options 16 contacting actel customer service 25 electronic mail 25 telephone 26 web-based technical support 25 control inputs 7 core versions 5 customer service 25 d description, general 5 device utilization and performance 8 double-buffering 7 f fifo mode 7 fifos receive 7 transmit 7 g general description 5 i i/o signals 15 n normal mode 7 o ordering code 21 p parity errors 7 product support 26 customer service 25 electronic mail 25 technical support 25 telephone 26 website 25 s signals, i/o 15 state machines receive 7 transmit 7 t technical support 25 testbenches verification 12 timing diagrams framing error 19 framing error in legacy mode 20 overflow error 19 parity error 18 serial receive 18 serial transmit 17 u use cases 5 v verification testbench 12 versions, core 5 w web-based technical support 25
50200095-2/10.10 actel corporation 2061 stierlin court mountain view, ca 94043-4655 usa phone 650.318.4200 fax 650.318.4600 actel europe ltd. river court,meadows business park station approach, blackwater camberley surrey gu17 9ab united kingdom phone +44 (0) 1276 609 300 fax +44 (0) 1276 607 540 actel japan exos ebisu buillding 4f 1-24-14 ebisu shibuya-ku tokyo 150 japan phone +81.03.3445.7671 fax +81.03.3445.7668 http://jp.actel.com actel hong kong room 2107, china resources building 26 harbour road wanchai, hong kong phone +852 2185 6460 fax +852 2185 6488 www.actel.com.cn actel is the leader in low power fpgas and mixed signa l fpgas and offers the most comprehensive portfolio of system and power management solutions. po wer matters. learn more at www.actel.com. ? 2010 actel corporation. all rights reserved. actel, actel fusion, igloo, libero, pigeon point, proasic, smartfusion and the a ssociated logos are trademarks or registered trademarks of actel corporation. all other trademarks and service marks are the property of their resp ective owners.

▲Up To Search▲

Price & Availability of COREUART-RC

	To Download COREUART-RC Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .