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| d a t a sh eet preliminary speci?cation file under integrated circuits, ic02 1999 aug 05 integrated circuits SAA7712H sound effects dsp
1999 aug 05 2 philips semiconductors preliminary speci?cation sound effects dsp SAA7712H contents 1 features 1.1 hardware features 1.2 software features 2 applications 3 general description 4 quick reference data 5 ordering information 6 block diagram 7 pinning information 8 functional description 8.1 analog outputs 8.1.1 analog output circuit 8.1.2 dac frequency 8.1.3 dacs 8.1.4 upsample filter 8.1.5 performance 8.1.6 power-on mute (pom) 8.1.7 power-off plop suppression 8.1.8 pin vrefda 8.1.9 internal dac current reference 8.1.10 supply of the analog outputs 8.2 i 2 s-bus inputs and outputs 8.2.1 digital data stream formats 8.2.2 slave i 2 s-bus inputs 8.2.3 master i 2 s-bus inputs and outputs 8.3 equalizer accelerator 8.3.1 introduction 8.3.2 configuration of equalizer sections 8.3.3 overflow detection 8.4 clock circuit and oscillator 8.4.1 general description 8.4.2 supply of the crystal oscillator 8.5 programmable phase-locked loop circuit 8.6 i 2 c-bus control 8.6.1 introduction 8.6.2 characteristics of the i 2 c-bus 8.6.3 bit transfer 8.6.4 start and stop conditions 8.6.5 data transfer 8.6.6 acknowledge 8.6.7 state of the i 2 c-bus interface during and after power-on reset 8.7 external control pins 8.8 reset pin 8.9 power supply connection and emc 8.10 test mode connections 9i 2 c-bus format 9.1 addressing 9.2 slave address (pin a0) 9.3 write cycles 9.4 read cycles 9.5 i 2 c-bus memory map summary 9.6 i 2 c-bus memory map details 10 limiting values 11 thermal characteristics 12 dc characteristics 13 analog outputs characteristics 14 oscillator characteristics 15 i 2 s-bus timing characteristics 16 i 2 c-bus timing characteristics 17 application information 18 package outline 19 soldering 19.1 introduction to soldering surface mount packages 19.2 reflow soldering 19.3 wave soldering 19.4 manual soldering 19.5 suitability of surface mount ic packages for wave and reflow soldering methods 20 definitions 21 life support applications 22 purchase of philips i 2 c components 1999 aug 05 3 philips semiconductors preliminary speci?cation sound effects dsp SAA7712H 1 features 1.1 hardware features digital signal processor (dsp) core: C 18 bits data width, 12 bits coefficient width C separate x, y and p memories (both 384 bytes word xram and yram, 3 kbytes word prom) C 1 kbytes delay line memory suited for dolby pro logic surround. inputs: C 2 slave 18-bit digital stereo inputs: i 2 s-bus and lsb-justified serial formats C 2 master 18-bit digital stereo inputs: i 2 s-bus and lsb-justified serial formats. outputs: C 4 dacs with 4-times oversampling and noise shaping, fed to 4 output pins and configurable from the dsp program, as left, right, front and surround channels of a dolby pro logic surround system C 2 master 18-bit digital stereo outputs: i 2 s-bus and lsb-justified serial formats. 4-channel 5-band or 2-channel 10-band i 2 c-bus controlled parametric equalizer i 2 c-bus microcontroller interface for: C access to full x and y memory space C control of hardware settings: selectors, programmable clock generations, etc. controllable phase-locked loop (pll) to generate the high frequency dsp clock from common fundamental oscillator crystal 3.3 v process with 3.3 or 5 v digital periphery: C 3.3 or 5 v i 2 s-bus and i 2 c-bus microcontroller interfacing. operating temperature range from 0 to 70 c. 1.2 software features dolby pro logic surround/dolby 3 stereo: trademark of dolby laboratories licensing corporation noise generation: a pink noise generator is included for installation of the dolby pro logic/dolby 3 stereo mode hall/matrix surround: when no dolby pro logic surround source material is available then this mode can be used to produce a signal in the surround channel incredible surround (222-is): this algorithm expands the stereo width (stereo expander). this is intended to be used when the 2 speakers are placed close together (tv set and midi set). robust incredible surround (222-ris): same as incredible surround only an alternative algorithm 3d surround (422) or incredible virtual surround: dolby pro logic surround reproduced by 2 speakers (l and r) is-3d surround (422-is): same as 3d surround (422) only with extra stereo width expander on left and right ris-3d surround (422-ris): same as is-3d surround (422) with alternative algorithm 3d surround (423) or incredible virtual surround: dolby pro logic surround reproduced by 3 speakers (l, c and r) is-3d surround (423-is): same as 3d surround (423) only with extra stereo width expander on left and right ris-3d surround (423-ris): same as is-3d surround (423-is) with alternative algorithm 1999 aug 05 4 philips semiconductors preliminary speci?cation sound effects dsp SAA7712H voice cancelling (karaoke): rejects voice out of source material, mainly intended to be used with karaoke. several karaoke modes available in stereo mode and in dolby pro logic mode, such as (auto) voice cancel, (auto) centre voice cancel, (auto) multi left and (auto) multi right. microphone mix modes (karaoke): mono microphone mixed to left, right and centre channel spectrum analysis: 3-band spectrum analyser is provided dolby b: both a dolby b encoder as well as a dolby b decoder is implemented 2 room solution: in all modes not requiring more than 2 output channels (stereo and karaoke incredible surround) it is also possible to feed the source signal to the other 2 output channels (with same processed or not processed signal) dynamic bass enhancement (dbe): dynamic bass enhancement generates a sub-woofer channel, which is either a separate output or is added to the front channels volume processing: independent volume processing of all 4 output channels ac-3/mpeg-2: inputs available intended to be used with an ac-3/mpeg-2 co-processor. in this mode the SAA7712H can be used as post-processor. output redirection: several output configurations are possible (normal 4 channel, special 4 + 2 channel, record 2 + 2 channel, 6 or 6 + 2 channel). depending on the sample frequency several combinations of the above mentioned features are possible. 2 applications the SAA7712H can be used in tv sets with: dolby pro logic surround, incredible surround, 3d surround and advanced acoustics processing multi-channel sound decoding (ac-3 and mpeg-2) on a co-processor. the SAA7712H can be used for post-processing. 3 general description the SAA7712H provides for digital signal processing power in tv systems and home theatre systems. a dsp core is equipped with digital inputs and outputs, a 5-band parametric equalizer accelerator, a digital co-processor interface and a delay line memory. this architecture accommodates on-chip standard sound processing, incredible surround, dolby pro logic surround and other surround sound processing algorithms. the architecture also supports co-processing, e.g. to add to the processing power of the internal dsp core or for multi-channel surround decoding. all settings and parameters are controlled by an i 2 c-bus interface. the available interfaces support a high application flexibility. the dsp core communicates over 32 dedicated registers. the selected digital input is master for the data rate of the dsp core. this input can be selected among 2 slave i 2 s-bus inputs. the 4 outputs from the core are passed through 4 dacs and then routed to 4 output pins. two master i 2 s-bus outputs and two master i 2 s-bus inputs can serve as an i 2 s-bus co-processor interface. eight of the remaining registers are used for communication with the hardware equalizer, and eight for communication with the delay line memory. all i 2 s-bus inputs and outputs support the philips i 2 s-bus format as well as 16, 18 and 20-bit lsb-justified formats. 1999 aug 05 5 philips semiconductors preliminary speci?cation sound effects dsp SAA7712H 4 quick reference data 5 ordering information symbol parameter condition min. typ. max. unit v dd3v supply voltage 3.3 v analog and digital with respect to v ss 3 3.3 3.6 v v dd5v supply voltage 5 v periphery with respect to v ss 3 3.3 or 5 5.5 v i ddd3v dc supply current of the 3.3 v digital core part at f dsp18 ; maximum activity of the dsp -- 80 ma i ddd5v dc supply current of the 5 v digital periphery part at f dsp18 ; maximum activity of the dsp; v dd5 =5v -- 5ma at f dsp18 ; maximum activity of the dsp; v dd5 = 3.3 v -- 5ma i dda dc supply current of the analog part at zero input and output signal -- 10 ma p tot total power dissipation at f dsp18 ; maximum activity of the dsp -- 0.4 w (thd + n)/s dac total harmonic distortion-plus-noise to output signal r l >5k w; f = 1 khz; a-weighted -- 75 - 60 dba dr dac dac dynamic range f = 1 khz; - 60 db; a-weighted 90 96 - dba ds dac dac digital silence f = 20 hz to 17 khz; a-weighted -- 107 - 102 dba f xtal crystal frequency 10.000 - 19.456 mhz f dsp16 dsp clock frequency f xtal = 16.384 mhz -- 32.256 mhz f dsp18 dsp clock frequency f xtal = 18.432 mhz -- 32.544 mhz type number package name description version SAA7712H qfp80 plastic quad ?at package; 80 leads (lead length 1.95 mm); body 14 20 2.7 mm; high stand-off height sot318-1 1999 aug 05 6 philips semiconductors preliminary speci?cation sound effects dsp SAA7712H this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... 6 block diagram h andbook, full pagewidth mgs206 surround channel delay 2-channel 10-band equalizer 3d surround 27 i 2 s_in1_ws 29 i 2 s_in1_bck 28 i 2 s_in1_data 24 i 2 s_in2_ws 26 i 2 s_in2_bck 25 i 2 s_in2_data 21 sys_clk is-3d surround ris-3d surround volume processing quad dac sda scl incredible surround (is, ris) dolby pro logic or dolby 3 stereo or hall/matrix centre voice cancelling 4-channel 5-band equalizer i 2 c-bus interface oscillator and pll i 2 s-bus input switch from audio source 2 from audio source 1 out0_i 8 15 pom vrefda 18 out0_v 19 out1_i 17 out1_v 16 out2_i 11 out2_v 12 out3_i 10 out3_v 45 46 host i/o 37 36 30 32 63 62 33 31 48 47 test 58 59 60 77 76 57 39 38 41 40 20 9 a0 44 SAA7712H eqov i 2 s_io_bck i 2 s_io_in1 i 2 s_io_in2 i 2 s_io_ws i 2 s_io_out1 i 2 s_io_out2 dsp_in1 dsp_in2 dsp_out1 test2 test1 dsp_out2 tscan shtcb rtcb dsp_reset osc_out osc_in vdacn1 vdacp1 fig.1 block diagram. 1999 aug 05 7 philips semiconductors preliminary speci?cation sound effects dsp SAA7712H 7 pinning information symbol pin description pin type n.c. 1 not connected n.c. 2 not connected n.c. 3 not connected n.c. 4 not connected n.c. 5 not connected n.c. 6 not connected n.c. 7 not connected pom 8 power-on mute; timing determined by external capacitor ap2d out3_v 9 analog voltage output 3 ap2d out3_i 10 analog current output 3 ap2d out2_i 11 analog current output 2 ap2d out2_v 12 analog voltage output 2 ap2d v ssa2 13 analog ground supply 2 apvss v dda2 14 analog supply voltage 2 (3 v) apvdd vrefda 15 voltage reference of the analog part ap2d out1_v 16 analog voltage output 1 ap2d out1_i 17 analog current output 1 ap2d out0_i 18 analog current output 0 ap2d out0_v 19 analog voltage output 0 ap2d eqov 20 equalizer over?ow line output b4cr sys_clk 21 test pin output bt4cr v ddd5v1 22 digital supply voltage 1; peripheral cells only (3 or 5 v) vdd5 v ssd5v1 23 digital ground supply 1; peripheral cells only (3 or 5 v) vss5 i 2 s_in2_ws 24 i 2 s-bus or lsb-justi?ed format word select input from a digital audio source 2 ibufd i 2 s_in2_data 25 i 2 s-bus or lsb-justi?ed format left-right data input from a digital audio source 2 ibufd i 2 s_in2_bck 26 i 2 s-bus clock or lsb-justi?ed format input from a digital audio source 2 ibufd i 2 s_in1_ws 27 i 2 s-bus or lsb-justi?ed format word select input from a digital audio source 1 ibufd i 2 s_in1_data 28 i 2 s-bus or lsb-justi?ed format left-right data input from a digital audio source 1 ibufd i 2 s_in1_bck 29 i 2 s-bus clock or lsb-justi?ed format input from a digital audio source 1 ibufd i 2 s_io_bck 30 i 2 s-bus bit clock output for interface with dsp co-processor chip bt4cr i 2 s_io_in1 31 i 2 s-bus input data channel 1 from dsp co-processor chip ibufd i 2 s_io_in2 32 i 2 s-bus input data channel 2 from dsp co-processor chip ibufd i 2 s_io_ws 33 i 2 s-bus word select output for interface with dsp co-processor chip bt4cr v ddd5v2 34 digital supply voltage 2; peripheral cells only (3 or 5 v) vdd5 v ssd5v2 35 digital ground supply 2; peripheral cells only (3 or 5 v) vss5 i 2 s_io_out1 36 i 2 s-bus output data channel 1 to dsp co-processor chip bt4cr i 2 s_io_out2 37 i 2 s-bus output data channel 2 to dsp co-processor chip bt4cr dsp_in1 38 digital input 1 of the dsp core (f0 of the status register) ibufd 1999 aug 05 8 philips semiconductors preliminary speci?cation sound effects dsp SAA7712H dsp_in2 39 digital input 2 of the dsp-core (f1 of the status register) ibufd dsp_out1 40 digital output 1 of the dsp-core (f2 of the status register) b4cr dsp_out2 41 digital output 2 of the dsp-core (f3 of the status register) b4cr v ddd5v3 42 digital supply voltage 3; peripheral cells only (3 or 5 v) vdd5 v ssd5v3 43 digital ground supply 3; peripheral cells only (3 or 5 v) vss5 a0 44 i 2 c-bus slave subaddress selection input ibufd scl 45 i 2 c-bus serial clock input schmitcd sda 46 i 2 c-bus serial data input/output bd4sci4 test1 47 test pin 1 bd4cr test2 48 test pin 2 bt4cr v ssd3v1 49 digital ground supply 1 of 3 v core only vss3s v ssd3v2 50 digital ground supply 2 of 3 v core only vss3s v ssd3v3 51 digital ground supply 3 of 3 v core only vss3s v ddd3v1 52 digital supply voltage 1 of 3 v core only vdd3 v ddd3v2 53 digital supply voltage 2 of 3 v core only vdd3 v ssd3v4 54 digital ground supply 4 of 3 v core only vss3s v ssd3v5 55 digital ground supply 5 of 3 v core only vss3s v ssd3v6 56 digital ground supply 6 of 3 v core only vss3s dsp_reset 57 reset (active low) ibufu r tcb 58 asynchronous reset test control block (active low) ibufd shtcb 59 shift clock test control block ibufd tscan 60 scan control ibufd v ss_osc 61 ground supply crystal oscillator circuit vss3s osc_in 62 crystal oscillator input; crystal oscillator sense for gain control or forced input in slave mode osc osc_out 63 crystal oscillator output; drive output to 11.2896 mhz crystal osc v dd_osc 64 3 v supply voltage crystal oscillator circuit vdd3 n.c. 65 not connected n.c. 66 not connected n.c. 67 not connected n.c. 68 not connected n.c. 69 not connected n.c. 70 not connected n.c. 71 not connected n.c. 72 not connected n.c. 73 not connected n.c. 74 not connected n.c. 75 not connected vdacp1 76 not used vdacn1 77 not used symbol pin description pin type 1999 aug 05 9 philips semiconductors preliminary speci?cation sound effects dsp SAA7712H table 1 pin types n.c. 78 not connected n.c. 79 not connected n.c. 80 not connected pin name pin description b4cr 4 ma slew rate controlled digital output bd4cr 4 ma slew rate controlled digital i/o bd4crd 4 ma slew rate controlled digital i/o with pull-down resistor bt4cr 4 ma slew rate controlled 3-state digital output ibuf digital input ibufu digital input with pull-up resistor ibufd digital input with pull-down resistor bd4sci4 i 2 c-bus input/output with open-drain nmos 4 ma output schmitcd schmitt trigger input ap2d analog input/output osc analog input/output vdd5 5 v v dd internal vdd3 3 v v dd internal vss3s 3 or 5 v v ss internal substrate vss5 5 v v ss external apvdd analog v dd apvss analog v ss symbol pin description pin type 1999 aug 05 10 philips semiconductors preliminary speci?cation sound effects dsp SAA7712H fig.2 pin configuration. handbook, full pagewidth SAA7712H mgs207 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 64 63 62 61 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 tscan shtcb rtcb dsp_reset v ssd3v6 v dd_osc osc_out osc_in v ss_osc v ssd3v5 v ssd3v4 v ddd3v2 v ddd3v1 v ssd3v3 v ssd3v2 v ssd3v1 test2 test1 sda scl a0 v ssd5v3 v ddd5v3 dsp_out2 n.c. n.c. n.c. pom out3_v n.c. n.c. n.c. n.c. out3_i out2_i out2_v v ssa2 v dda2 vrefda out1_v out1_i out0_i out0_v eqov sys_clk v ddd5v1 v ssd5v1 i 2 s_in2_ws 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 i 2 s_in2_data i 2 s_in2_bck i 2 s_in1_ws i 2 s_in1_data i 2 s_in1_bck i 2 s_io_bck i 2 s_io_in1 i 2 s_io_in2 i 2 s_io_ws v ddd5v2 v ssd5v2 i 2 s_io_out1 i 2 s_io_out2 dsp_in1 dsp_in2 dsp_out1 n.c. n.c. n.c. vdacn1 vdacp1 n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 1999 aug 05 11 philips semiconductors preliminary speci?cation sound effects dsp SAA7712H 8 functional description 8.1 analog outputs 8.1.1 a nalog output circuit depending on the configuration of the equalizer sections, the SAA7712H has 2 or 4 analog outputs which are supplied by the same power supply. each of these outputs has a voltage and a current pin (see fig.3). the signals are available on 2 outputs (out0 and out1), or 4 outputs (out0, out1, out2 and out3). 8.1.2 dac frequency the sample rate (f s ) of the selected source is the frame rate of the dsp. the word clock for the upsample filter and the clock for the dacs, at 4f s , are derived internally from the word select of the selected audio source. fig.3 analog output circuit. handbook, halfpage mgs208 bit 0 to 13 msb v ref dac out0_v (out1_v) out0_i (out1_i) 8.1.3 dac s each of the four low noise high dynamic range dacs consists of a signed-magnitude dac with current output, followed by a buffer operational amplifier. 8.1.4 u psample filter to reduce spectral components above the audio band, a fixed 4 times oversampling and interpolating digital filter is used. the filters give an out-of-audio-band attenuation of at least 29 db. the filter is followed by a first-order noise shaper to expand the dynamic range to more than 105 db. the band around multiples of the sample frequency of the dac (4f s ) is not affected by the digital filter. a capacitor must be added in parallel with the dac output amplifier to attenuate this out-of-band noise further to an acceptable level. in fig.4 the overall frequency spectrum at the dac audio output without external capacitor or low-pass filter for the audio sampling frequencies of 38 khz is shown. in fig.5 the detailed spectrum around f s is shown for an f s of 38, 44.1 and 48 khz. the pass band bandwidth ( - 3 db) is 1 2 f s . 1999 aug 05 12 philips semiconductors preliminary speci?cation sound effects dsp SAA7712H fig.4 overall frequency spectrum audio output. handbook, full pagewidth 500 0 - 10 - 60 0 100 mgs209 300 400 200 - 50 - 40 - 30 - 20 a (db) f (khz) f s = 38000 hz fig.5 detailed frequency spectrum audio output. handbook, full pagewidth 0 0 10000 30000 mgs210 20000 - 10 - 50 - 40 - 30 - 20 f (hz) f s = 38000 hz 0 11605 34816 23211 f s = 44100 hz 0 12632 37895 25263 f s = 48000 hz a (db) 1999 aug 05 13 philips semiconductors preliminary speci?cation sound effects dsp SAA7712H 8.1.5 p erformance the signed-magnitude noise-shaped dac has a dynamic range in excess of 100 db. the signal-to-noise ratio of the audio output at full-scale is determined by the word length of the converter. the noise at low outputs is fully determined by the noise performance of the dac. since it is a signed-magnitude type, the noise at digital silence is also low. as a disadvantage, the total thd is higher than conventional dacs. the typical total harmonic distortion-plus-noise to signal ratio as a function of the output level is shown in fig.6. fig.6 typical (thd + n)/s curve as a function of the output level. handbook, halfpage - 80 - 60 - 40 0 mgs211 - 20 - 60 - 80 - 40 - 20 (thd + n)/s (db) output level (db) 8.1.6 p ower -o n m ute (pom) to avoid any uncontrolled noise at the audio outputs after power-on of the ic, the reference current source of the dac is switched off. the capacitor on pin pom determines the time after which this current has a soft switch-on. so at power-on the current audio signal outputs are always muted. the loading of the external capacitor is done in two stages via two different current sources. the loading starts at a current level that is 9 times lower than the current loading after the voltage on pin pom has passed the 1 v level. this results in an almost db linear behaviour. 8.1.7 p ower - off plop suppression power should still be provided to the analog part of the dac, while the digital part is switching off. as a result, the output voltage will decrease gradually allowing the power amplifier some extra time to switch-off without audible plops. if a 5 v power supply is present, the supply voltage of the analog part of the dac can be fed from the 5 v power supply via a 1.8 v zener diode. a capacitor, connected to the 3.3 v power supply, provides power to the analog part when the 5 v power supply is switching off fast. 1999 aug 05 14 philips semiconductors preliminary speci?cation sound effects dsp SAA7712H 8.1.8 p in vrefda with two internal resistors half the supply voltage (v dda2 ) is obtained and coupled to an internal buffer. this reference voltage is used as dc voltage for the output operational amplifiers and as reference for the dac. in order to obtain the lowest noise and to have the best ripple rejection, a filter capacitor has to be added between this pin and ground. 8.1.9 i nternal dac current reference as a reference for the internal dac current and for the dac current source output, a current is drawn from the level on pin vrefda to pin v ssa2 (ground) via an internal resistor. the absolute value of this resistor also determines the absolute current of the dac. this means that the absolute value of the current is not that fixed due to the spread of the current reference resistor value. this, however, does not influence the absolute output voltages because these voltages are also derived from a conversion of the dac current to the actual output voltage via internal resistors. 8.1.10 s upply of the analog outputs all the analog circuitry of the dacs and the operational amplifiers are fed by 2 supply pins, v dda2 and v ssa2 . pin v dda2 must have sufficient decoupling to prevent thd degradation and to ensure a good power supply rejection ratio. the digital part of the dac is fully supplied from the chip core supply. 8.2 i 2 s-bus inputs and outputs 8.2.1 d igital data stream formats for communication with external digital sources a serial 3-line bus is used. this i 2 s-bus has one line for data, one line for clock and one line for the word select. see fig.7 for the general waveform formats of the four possible formats. the serial digital inputs (and outputs) of the SAA7712H are capable of handling multiple formats: philips i 2 s-bus and lsb-justified formats of 16, 18 and 20 bits word sizes. in philips i 2 s-bus format, the number of bit clock (bck) pulses may vary in the application. when the transmitter word length is smaller than the receiver word length, the receiver will fill in zeroes at the lsb side. when the transmitter word length exceeds the receiver word length, the lsbs are skipped. for correct operation of the dacs, there should be a minimum of 16 bit clocks per word select. in the lsb-justified formats, the transmitter and receiver must be set to the same format. be aware that a format switch between 20, 18 and 16 bits lsb-justified formats is done by changing the relative timing of the word select edges. the data bits remain unchanged. in the 20 bits format, the 2 lsbs are zeroes. in the 16 bits format, the 2 data bits following the word select edge are not zero, but undefined. in fact, these are the lsbs of the 18-bit word. the timing specification for the waveforms of the serial digital inputs and outputs are given in fig.17. 1999 aug 05 15 philips semiconductors preliminary speci?cation sound effects dsp SAA7712H this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... handbook, full pagewidth lsb-justified format 16 bits lsb-justified format 18 bits lsb-justified format 20 bits input format i 2 s-bus ws left left left left right right right right 3 2 2 2 15 16 17 18 1 15 16 1 1 3 2 1 msb b2 msb msb b2 msb lsb b2 msb b2 b3 b4 b15 lsb b17 2 15 16 17 18 1 msb b2 b3 b4 lsb b17 2 15 16 17 18 19 20 1 msb b2 b3 b4 b5 b6 lsb b19 mgs212 2 15 16 17 18 19 20 1 msb b2 b3 b4 b5 b6 lsb b19 2 15 16 1 msb lsb b2 b15 bck data ws bck data ws bck data ws bck data fig.7 all serial data i/o formats. 1999 aug 05 16 philips semiconductors preliminary speci?cation sound effects dsp SAA7712H 8.2.2 s lave i 2 s- bus inputs the SAA7712H has two slave i 2 s-bus inputs, i 2 s_in1 and i 2 s_in2 with respective data lines i 2 s_in1_data and i 2 s_in2_data, word select lines i 2 s_in1_ws and i 2 s_in2_ws and bit clock lines i 2 s_in1_bck and i 2 s_in2_bck. the external source is master and supplies the bit clock and word select. the i 2 c-bus bits audio_format(2 to 0) allow for selection of the desired i 2 s-bus format (see table 13). the bits, needed for selecting a certain format, are explained in table 2. the input circuitry is limited in handling the number of bck pulses per ws period. if the word rate of the selected digital input source is f s , the bit clock must be a continuous clock in the range of 16f s f bit(clk) 256f s . the minimum limit of the audio sample frequency is determined by 1 18 f scl . the maximum limit of the audio sample frequency is determined by dsp_clock/481 hz. table 2 i 2 c-bus audio_format mode bits (0ff9h, see table 13) the selection of the dsp input among the decimated analog input and the i 2 s-bus inputs i 2 s_in1 and i 2 s_in2 is controlled with i 2 c-bus bit audio_source (see table 13). the meaning of this bit can be found in table 3. audio_format output bit 9 bit 8 bit 7 0 0 0 internal format (for test purposes only) - 0 1 lsb-justi?ed, 16 bits - 1 0 lsb-justi?ed, 18 bits - 1 1 lsb-justi?ed, 20 bits 1 0 0 standard i 2 s-bus (default) table 3 i 2 c-bus audio_source mode bit (0ff9h, see table 13) 8.2.3 m aster i 2 s- bus inputs and outputs for the co-processor i/o interface, the SAA7712H acts as a master. the SAA7712H supplies both the bit clock and word select. the i 2 c-bus bits host_io_format(1 and 0) allow for selection of the desired i 2 s-bus format (see table 13). the bits needed for selecting a certain format are given in table 4. all i 2 s-bus output lines, i 2 s_io_ws, i 2 s_io_bck, i 2 s_io_out1 and i 2 s_io_out2, can be 3-stated with i 2 c-bus bit en_host_io (see table 13). the word select and bit clock of the co-processor i/o interface are derived from the word select and bit clock of the audio source selected according to table 3. the incoming bit clock can be divided by 1, 2, 4 or 8 depending on the needs of an external connected co-processor. these selections can be done with i 2 c-bus bits cloop_mode(2 to 0) (see table 13). the meaning of these bits is shown in table 5. audio_source output bit 5 0i 2 s_in1 (default) 1i 2 s_in2 1999 aug 05 17 philips semiconductors preliminary speci?cation sound effects dsp SAA7712H table 4 i 2 c-bus host_io_format bits (0ff9h, see table 13) table 5 i 2 c-bus cloop_mode bits (0ff9h, see table 13) host_io_format output bit 11 bit 10 0 0 standard i 2 s-bus (default) 0 1 lsb-justi?ed format, 16 bits 1 0 lsb-justi?ed format, 18 bits 1 1 lsb-justi?ed format, 20 bits cloop_mode output bit 15 bit 14 bit 13 0 -- bypass ws (default) 1 -- ws 50% duty factor - 0 0 bypass bclk (default) - 0 1 divide bclk by 2 - 1 0 divide bclk by 4 - 1 1 divide bclk by 8 8.3 equalizer accelerator 8.3.1 i ntroduction the equalizer accelerator is a hardware accelerator to the dsp core. both its inputs and outputs are stored in registers of the dsp core. the equalizer cannot be used and cannot be programmed if no word select and bit clock signal are present on a selected digital source input; see audio_source bit in table 3 (i 2 s_in1 or i 2 s_in2). the minimum required dsp_clock is 481f s . the equalizer accelerator contains one second-order filter data path that is 20 times multiplexed. with this circuit, a 2-channel equalizer of 10 second-order sections per channel or a 4-channel equalizer of 5 second-order sections per channel can be realised. the centre frequency, gain and q-factor of all 20 second-order sections can be set independently from each other. every section is followed by a selectable attenuation of 0 or 6 db. per section, 4 bytes of the i 2 c-bus register are needed to store the settings. the equalizer settings can be updated during normal operation. an application program supports the programming of the equalizer. if the gain setting causes the audio signal to exceed the maximum level in one of the filter sections, the signal will be clipped and the equalizer overflow output (pin eqov) will be set high until the end of the next audio sample period. 8.3.2 c onfiguration of equalizer sections the equalizer accelerator can make a 2-channel equalizer of 10 second-order sections per channel or a 4-channel equalizer of 5 second-order sections per channel. the sections of one channel can be chained one after the other. depending on the i 2 c-bus control bit two_four (see table 11), the 20 filter sections are combined for the appropriate configuration, as illustrated in fig.8. 1999 aug 05 18 philips semiconductors preliminary speci?cation sound effects dsp SAA7712H fig.8 configurations of the equalizer sections. handbook, full pagewidth mgs213 out0 in0 2 channel 2 channel 1 a 2 3 4 5 out1 in1 b out2 in2 c out3 in3 d 8.3.3 o verflow detection the equalizer has an overflow flag. this flag is fed to output pin eqov. if an overflow is detected in one of the filter sections, the signal is clipped to the maximum allowed level. the overflow flag is immediately set. it remains at a high-level during the remaining part of the current audio sample period and for the whole next sample period. if no overflow is detected during this next sample period, the overflow flag goes to a low-level at the beginning of the sample period after that. otherwise, the overflow flag remains at a high-level for at least one other audio sample period. 8.4 clock circuit and oscillator 8.4.1 g eneral description the chip has a crystal clock oscillator. it can use a crystal at either f xtal = 16.384 mhz = 512 32 khz or f xtal = 18.432 mhz = 576 32 khz in fundamental mode. the block diagram of this pierce oscillator is shown in fig.9. the active element needed to compensate for the loss resistance of the crystal is the block gm. this block is placed between the external pins osc_in and osc_out. the gain of the oscillator is internally controlled by the agc block. a sine wave with a peak-to-peak voltage close to the oscillator power supply voltage is generated. the agc block prevents clipping of the sine wave and therefore the higher harmonics are as low as possible. at the same time, the voltage of the sine wave is as high as possible so reducing the jitter going from sine wave to clock signal. the sinusoidal output is converted into a cmos compatible clock by the comparator. the second mode of operation shown in fig.10, is the slave mode which is driven by a master clock directly. the signal to pin osc_in can be driven to the power supply voltages v dd_osc and v ss_osc . 8.4.2 s upply of the crystal oscillator the power supply connections of the oscillator are separate from the other supply lines. this is to minimize the feedback from the ground bounce of the chip to the oscillator circuit. pin v ss_osc is used as the ground supply and pin v dd_osc as the positive supply. 1999 aug 05 19 philips semiconductors preliminary speci?cation sound effects dsp SAA7712H fig.9 block diagram of the crystal oscillator circuit. handbook, full pagewidth mgs214 clock out osc_out r bias 100 k w v dd_osc 0.5v dd_osc v ss_osc off chip on chip 61 64 63 osc_in c1 10 pf c2 10 pf 62 gm agc fig.10 block diagram of the oscillator in slave mode. handbook, full pagewidth mgs215 clock out osc_out r bias 100 k w v dd_osc 0.5v dd_osc v ss_osc off chip slave input on chip 61 64 63 osc_in c1 10 pf c3 5 pf c2 10 pf 62 gm agc 1999 aug 05 20 philips semiconductors preliminary speci?cation sound effects dsp SAA7712H 8.5 programmable phase-locked loop circuit the clock of the dsp is generated with a programmable pll. to select the required dsp clock see table 6. the n factor (ranging from 93 to 181) can be selected with i 2 c-bus bits pll_div(14 to 11), see table 10. depending on the crystal and the required dsp clock the i 2 c-bus bits pll_fs_sel and bits dsp_turbo must be set. the maximum limit of the audio sample frequency is determined by dsp_clock/481 hz. table 6 i 2 c-bus bits pll_div and dividing factors n of the programmable dsp clock notes 1. f xtal = 16.384 mhz; pll_fs_sel = 1 and dsp_turbo = 1, see table 11. 2. f xtal = 18.432 mhz; pll_fs_sel = 1 and dsp_turbo = 1, see table 11. 3. usable frequency. pll_div(14 to 11) n dsp clock frequency (mhz) tda9875 (1) msp3410d (2) 0000 93 (default) 23.808 (3) 26.784 0001 99 25.344 (3) 28.512 0010 106 27.136 30.528 0011 113 28.928 32.544 0100 121 30.976 34.848 (3) 0101 126 32.256 36.288 (3) 0110 132 33.792 (3) 38.016 (3) 0111 137 35.072 (3) 39.456 (3) 1000 143 36.608 (3) 41.184 (3) 1001 148 37.888 (3) 42.624 (3) 1010 154 39.424 (3) 44.352 (3) 1011 159 40.704 (3) 45.792 (3) 1100 165 42.240 (3) 47.520 (3) 1101 170 43.520 (3) 48.960 (3) 1110 176 45.056 (3) 50.688 (3) 1111 181 46.336 (3) 52.128 (3) 1999 aug 05 21 philips semiconductors preliminary speci?cation sound effects dsp SAA7712H 8.6 i 2 c-bus control 8.6.1 i ntroduction a general description of the i 2 c-bus format can be obtained from philips semiconductors, international marketing and sales communications (imsc). for the external control of the SAA7712H a fast i 2 c-bus is implemented. this is a 400 khz bus which is downward compatible with the standard 100 khz bus. there are different types of control instructions: instructions to control the dsp program, program the coefficient ram and read the values of parameters instructions to control the equalizer, program the equalizer coefficient ram to be able to change the centre frequency, gain and q-factor of the equalizer sections instructions to control the source selection and programmable parts, e.g. pll clock speed. the detailed description of the i 2 c-bus and commands is given in the following sections. the description of the different bits in the memory map is given in section 9.6. the equalizer cannot be used and cannot be programmed if there is no word select and bit clock signal present on a selected digital source input; see audio_source bit in table 3 (i 2 s_in1 and i 2 s_in2). the minimum limit of the audio sample frequency is determined by 1 18 f scl . 8.6.2 c haracteristics of the i 2 c- bus the i 2 c-bus is for 2-way, 2-line communication between different ics or modules. the two lines are a serial data line (sda) and a serial clock line (scl). both lines must be connected to v dd via a pull-up resistor when connected to the output stages of a microcontroller. for a 400 khz i 2 c-bus the recommendation from philips semiconductors must be followed (e.g. up to loads of 200 pf on the bus a pull-up resistor can be used, between 200 to 400 pf a current source or switched resistor must be used). data transfer can only be initiated when the bus is not busy. 8.6.3 b it transfer one data bit is transferred during each clock pulse. the data on the sda line must remain stable during the high period of the clock pulse as changes in the data line at this time will be interpreted as control signals (see fig.11). the maximum clock frequency is 400 khz. to be able to run on this high frequency all the inputs and outputs connected to this bus must be designed for this high speed i 2 c-bus according to the philips specification. fig.11 bit transfer on the i 2 c-bus. handbook, full pagewidth mgs216 sda scl data line stable; data valid change of data allowed 1999 aug 05 22 philips semiconductors preliminary speci?cation sound effects dsp SAA7712H 8.6.4 s tart and stop conditions both data and clock lines will remain high when the bus is not busy. a high-to-low transition of the data line, while the clock is high, is defined as a start condition (s). a low-to-high transition of the data line while the clock is high is defined as a stop condition (p) (see fig.12). fig.12 start and stop conditions. handbook, full pagewidth mgs217 sda scl s p start condition stop condition 8.6.5 d ata transfer a device generating a message is a transmitter and a device receiving a message is the receiver. the device that controls the message is the master and the devices which are controlled by the master are the slaves. fig.13 data transfer on the i 2 c-bus. handbook, full pagewidth mgs218 sda scl s start condition 1 2 7 8 9 1 2 3 to 8 9 msb ack ack acknowledgement signal from receiver byte complete interrupt within receiver clock line held low while interrupts are serviced acknowledgement signal from receiver 1999 aug 05 23 philips semiconductors preliminary speci?cation sound effects dsp SAA7712H 8.6.6 a cknowledge the number of data bits transferred between the start and stop conditions from the transmitter to the receiver is not limited. each byte of eight bits is followed by one acknowledge bit (see fig.13). the acknowledge bit is a high-level left on the bus by the transmitter whereas the master generates an extra acknowledge related clock pulse. a slave receiver which is addressed must generate an acknowledge after the reception of each byte. also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. the device that acknowledges has to pull down the sda line (left high by the transmitter) during the acknowledge clock pulse, so that the sda line is stable low during the high period of the acknowledge related clock pulse. set-up and hold times must be taken into account. a master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. in this event the transmitter must leave the data line high to enable the master to generate a stop condition (see fig.14). 8.6.7 s tate of the i 2 c- bus interface during and after p ower - on reset during reset (see section 8.8), the internal sda line is kept high and pin sda is therefore high-impedance. the sda line remains high until a master pulls it down to initiate communication. fig.14 acknowledge on the i 2 c-bus. handbook, full pagewidth mgs219 s start condition 12 789 data output by receiver scl from master clock pulse for acknowledgement data output by transmitter acknowledge not acknowledge 1999 aug 05 24 philips semiconductors preliminary speci?cation sound effects dsp SAA7712H 8.7 external control pins for external control two input pins are implemented. the status of these pins can be changed by applying a logic level. the status of these pins is recorded in the internal status register. the function of each input pin is determined by the dsp software. pin dsp_in1: logic 0 or left open-circuit means volume coefficients updates are possible (default) logic 1 means no updates of volume coefficients are possible. pin dsp_in2: if the 3-band spectrum analyser is used: C logic 1 will reset the band registers of the analyser C logic 0 or left open-circuit means no reset of the band registers will be done (default). if the 3-band spectrum analyser is not used: C the state of pin dsp_in2 can be read via an i 2 c-bus command. to control external devices two output pins are implemented. the status of these pins is controlled by the dsp program. the functions of these pins are determined by the dsp software. pin dsp_out1: to drive pin dsp_out1 via an i 2 c-bus command. pin dsp_out2: to drive pin dsp_out2 via an i 2 c-bus command. 8.8 reset pin the reset signal on pin dsp_reset is active low and has an internal pull-up resistor. between this pin and ground a capacitor should be connected to allow a proper switch-on of the supply voltage. the capacitor value is such that the chip is in the reset state as long as the power supply is not stabilized. a more or less fixed relationship between the dsp_reset time constant and the pom time constant is obligatory. the voltage on pin pom determines the current flowing in the dacs. for 0 v on pin pom, the dac currents are zero and so also the dacs output voltages. when a 3 v supply voltage (v dda2 ) is supplied to pin pom, the dac currents are at their nominal (maximum) value. long before the dac outputs get their nominal output voltages, the dsp must be in normal operating mode to reset the output register. therefore, the time constant of dsp_reset must be shorter than the time constant of pom. for advised capacitors see the application diagram. the reset has the following function: all i 2 c-bus registers are reset to their default values the dsp algorithm is re-started the external control output pins are reset (see section 8.7) pin sda is high-impedance. when the level on the reset pin is high, the dsp algorithm starts to run. in addition to the reset pin, there is also a software reset; bit pc_reset (bit 15, 0ffdh, see table 11). this reset has the following function: the dsp algorithm is re-started the external control output pins are reset (see section 8.7). 1999 aug 05 25 philips semiconductors preliminary speci?cation sound effects dsp SAA7712H 8.9 power supply connection and emc the digital part of the chip has in total 5 positive supply line connections and 8 ground connections. to minimise radiation the chip should be put on a double layer pcb with a large ground plane on one side. the ground supply lines should have a short connection to this ground plane. a coil and capacitor network in the positive supply line can be used as high frequency filter. 8.10 test mode connections pins tscan, rtcb and shtcb are used to put the chip in test mode and to test the internal connections. each pin has an internal pull-down resistor to ground. in the application these pins can be left open-circuit or connected to ground. 9i 2 c-bus format 9.1 addressing before any data is transmitted on the i 2 c-bus, the device which should respond is addressed first. the addressing is always done with the first byte transmitted after the start procedure. 9.2 slave address (pin a0) the SAA7712H acts as a slave receiver or a slave transmitter. therefore, the clock signal scl is only an input signal. the data signal sda is a bidirectional line. the slave address is shown in table 7. table 7 slave address the subaddress bit a0 corresponds to the hardware address pin a0 which allows the device to have two addresses. this allows the control of two SAA7712Hs via the same i 2 c-bus. msb lsb 0 0 1 1 1 1 a0 r/ w 9.3 write cycles the i 2 c-bus configuration for a write cycle is shown in fig.15. the write cycle is used to write the bytes to control the pll for the dsp clock generation, the format of the i 2 s-bus and some other settings. more details can be found in the i 2 c-bus memory map (see table 8). the data length is 2 or 3 bytes, depending on the accessed memory. the slave receiver detects the address and adjusts the number of bytes accordingly. for xram, the data word length is 18 bits and 3 bytes are sent over the i 2 c-bus. the upper 6 bits (i.e. bit 7 to bit 2) of the first byte data h are dont care. for yram, the data word length is 12 bits and 2 bytes are sent over the i 2 c-bus. the left nibble (i.e. bit 7 to bit 4) of the first byte data h is dont care. 9.4 read cycles the i 2 c-bus configuration for a read cycle is shown in fig.16. the read cycle is used to read the data values from xram or yram. the master starts with a start condition (s), the SAA7712H address 0011110 and a logic 0 (write) for the read/write bit. this is followed by an acknowledge of the SAA7712H. the master then writes the memory high address and memory low address where the reading of the memory content of the SAA7712H must start. the SAA7712H acknowledges these addresses both. the master than generates a repeated start and again the SAA7712H address 0011110 but this time followed by a logic 1 (read) of the read/write bit. from this moment on, the SAA7712H will send the memory content in groups of 2 (yram) or 3 (xram) bytes to the i 2 c-bus, each time acknowledged by the master. the master stops this cycle by generating a negative acknowledge, then the SAA7712H frees the i 2 c-bus and the master can generate a stop condition (p). 1999 aug 05 26 philips semiconductors preliminary speci?cation sound effects dsp SAA7712H this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... 0111000 a c k a c k a c k a c k a c k address s 0 addr h addr l data h data m r/w mgd568 auto increment if repeated n-groups of 3 (2) bytes p a c k data l fig.15 master transmitter writes to the dsp registers. s = start condition. ack = acknowledge from dsp (sda low). addr h and addr l = address dsp register. data h, data m and data l = data of xram or registers. data h and data m = data of yram. p = stop condition. 0111000 a c k a c k a c k a c k a c k address s 0 011 1 100 s 0 addr h addr l data h r/w mga808 - 1 auto increment if repeated n-groups of 3 (2) bytes p a c k a c k data m data l r/w fig.16 master transmitter reads from the dsp registers. s = start condition. ack = acknowledge from dsp (sda low). addr h and addr l = address dsp register. data h, data m and data l = data of xram or registers. data h and data m = data of yram. p = stop condition. 1999 aug 05 27 philips semiconductors preliminary speci?cation sound effects dsp SAA7712H 9.5 i 2 c-bus memory map summary the i 2 c-bus memory map contains all defined i 2 c-bus bits. the map is split into two different sections: hardware memory registers and the ram definitions. the preliminary memory map is given in table 8. table 8 i 2 c-bus memory map table 9 i 2 c-bus memory map: overview of various settings 9.6 i 2 c-bus memory map details table 10 i 2 c_dcs_ctr register (0fffh) subaddresses function size 0ff9h to 0fffh various settings (see table 9 ) 4 16 bits 0f80h to 0fa7h equalizer 40 16 bits 0800h to 097fh yram 384 12 bits 0000h to 017fh xram 384 18 bits register name subaddress i 2 c_dcs_ctr 0fffh (see table 10) i 2 c_adda 0ffdh (see table 11) i 2 c_sel 0ffah (see table 12) i 2 c_host 0ff9h (see table 13) name size (bits) description default bit position - 10 reserved 9 to 0 loopo_on_off 1 pin sys_clk output enable: on (logic 1) or off (logic 0) off 10 pll_div 4 pll clock division factor for dsp_clock (see table 6) 93 14 to 11 - 1 reserved 15 1999 aug 05 28 philips semiconductors preliminary speci?cation sound effects dsp SAA7712H table 11 i 2 c_adda register (0ffdh) table 12 i 2 c_sel register (0ffah) table 13 i 2 c_host register (0ff9h) name size (bits) description default bit position - 10 reserved 9 to 0 pll_fs_sel 1 divide oscillator by 2 (logic 1) division 10 dsp_turbo 1 double dsp_clock (logic 1) doubling 11 two_four 1 2-channel 10-band (logic 1) or 4-channel 5-band (logic 0) equalizer con?guration 4-channel 5-band 12 - 2 reserved 14 and 13 pc_reset 1 re-start dsp algorithm (logic 1) or dsp running (logic 0) dsp running 15 name size (bits) description default bit position - 8 reserved 7 to 0 bypass_pll 1 bypass pll used for dsp_clock (logic 1) or use pll for dsp_clock (logic 0) use pll 8 - 4 reserved 12 to 9 inv_host_ws 1 inverting (logic 1) or non-inverting (logic 0) word select non-inverting 13 - 2 reserved 15 and 14 name size (bits) description default bit position - 5 reserved 4 to 0 audio_source 1 input source is i 2 s_in1 or i 2 s_in2 (see table 3) i 2 s_in1 5 - 1 reserved 6 audio_format 3 format of selected input source (see table 2) standard i 2 s-bus 9 to 7 host_io_format 2 host input/output data format (see table 4) standard i 2 s-bus 11 and 10 en_host_io 1 enable (logic 1) or disable (logic 0) co-processor i 2 s-bus disable 12 cloop_mode 3 cloop mode (see table 5) bypass ws 15 to 13 1999 aug 05 29 philips semiconductors preliminary speci?cation sound effects dsp SAA7712H 10 limiting values in accordance with the absolute maximum ratings system (iec 134). notes 1. human body model: equivalent to discharging a 100 pf capacitor through a 1.5 k w resistor. 2. machine model: equivalent to discharging a 200 pf capacitor through a 2.5 m h inductance and a 0 w series resistor. 11 thermal characteristics note 1. printed-circuit board mounting. symbol parameter condition min. max. unit v dd3v supply voltage 3.3 v analog and digital - 0.5 +5 v v dd5v supply voltage 5 v periphery only valid for the voltages in connection with the 5 v i/os - 0.5 +6.5 v d v dd voltage difference between two v ddx pins - 550 mv ? i ik ? input clamping diode current v i < - 0.5 v or v i >v dd + 0.5 v - 10 ma ? i o(sink/source) ? output sink or source current, output type 4 ma - 0.5v 1999 aug 05 31 philips semiconductors preliminary speci?cation sound effects dsp SAA7712H r pd internal pull-down resistance to v ssd on pins 24 to 29, 38, 39, 44, 58 to 60 23 50 80 k w t i(r) , t i(f) input rise and fall times v ddd5v = 5.5 v - 6 200 ns v ddd5v = 3.6 v - 6 200 ns t lh5 output rise time on pins 20, 21, 30, 33, 36, 37, 40, 41, 47, 48 v ddd5v = 5.5 v; v ddd3v = 3.6 v; t j = - 40 c ; c l =60pf 5 -- ns v ddd5v = 4.5 v; v ddd3v =3v; t j = 125 c ; c l =60pf -- 25 ns t lh3 output rise time on pins 20, 21, 30, 33, 36, 37, 40, 41, 47, 48 v ddd5v = 3.6 v; v ddd3v = 3.6 v; t j = - 40 c ; c l =60pf 7.5 -- ns v ddd5v = 3.0 v; v ddd3v =3v; t j = 125 c ; c l =60pf -- 30 ns t lh(i2c5) output rise time on pin 46 (sda) c l and r pu are application speci?c --- ns t lh(i2c3) output rise time on pin 46 (sda) c l and r pu are application speci?c --- ns t hl5 output fall time on pins 20, 21, 30, 33, 36, 37, 40, 41, 47, 48 v ddd5v = 5.5 v; v ddd3v = 3.6 v; t j = - 40 c ; c l =60pf 5 -- ns v ddd5v = 4.5 v; v ddd3v =3v; t j = 125 c ; c l =60pf -- 25 ns t hl3 output fall time on pins 20, 21, 30, 33, 36, 37, 40, 41, 47, 48 v ddd5v = 3.6 v; v ddd3v = 3.6 v; t j = - 40 c ; c l =60pf 7.5 -- ns v ddd5v = 3.0 v; v ddd3v =3v; t j = 125 c ; c l =60pf -- 30 ns t hl(i2c5) output fall time on pin 46 (sda) v ddd5v = 5.5 v; v ddd3v = 3.6 v; t j = - 40 c ; c l = 200 pf 30 -- ns v ddd5v = 4.5 v; v ddd3v =3v; t j = 125 c ; c l = 200 pf -- 300 ns t hl(i2c3) output fall time on pin 46 (sda) v ddd5v = 3.6 v; v ddd3v = 3.6 v; t j = - 40 c ; c l = 200 pf 40 -- ns v ddd5v = 3.0 v; v ddd3v =3v; t j = 125 c ; c l = 200 pf -- 400 ns symbol parameter conditions min. typ. max. unit 1999 aug 05 32 philips semiconductors preliminary speci?cation sound effects dsp SAA7712H 13 analog outputs characteristics t amb =25 c; v dda2 = 3.3 v; unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit v vrefda voltage on pin vrefda with respect to v dda2 - v ssa2 47 50 53 % z vrefda impedance on pin vrefda with respect to v dda2 - 37 - k w with respect to v ssa2 - 37 - k w v o(rms) ac output voltage of operational ampli?ers (rms value) maximum i 2 s-bus signal; r l >5k w 0.62 0.7 0.82 v v o(av) average dc output voltage of operational ampli?ers r l >5k w 1.5 1.65 1.8 v i pu(poml) low pull-up current to v dda2 on pin pom voltage on pin pom < 0.6 v 3.3 - 5 m a i pu(pomh) high pull-up current to v dda2 on pin pom voltage on pin pom > 0.8 v 50 - 75 m a psrr dac power supply ripple rejection dacs (input via i 2 s-bus) f ripple = 1 khz; v ripple = 100 mv (peak value); c vrefda =22 m f 45 60 - db ?d i o(max) ? maximum deviation in output level (plus or minus) of the 4 dac current outputs with respect to the average of the 4 outputs; full-scale output -- 0.38 db a ct crosstalk between all outputs in the audio band one output digital silence, other three maximum volume --- 69 db i o(sc) output short-circuit current output short-circuited to ground -- 20 ma res dac dac resolution 18 bits (thd + n)/s total harmonic distortion-plus-noise to signal ratio f = 1 khz; v o(ref) = 0.72 v (rms); a-weighted -- 75 - 60 dba dr dac dynamic range of dac v o(ref) = 0.72 v (rms); f = 1 khz; - 60 db; a-weighted 90 96 - dba ds dac digital silence of dac f = 20 hz - 17 khz; v o(ref) = 0.72 v (rms); a-weighted -- 107 - 102 dba v n(o)(rms) digital silence noise level at output (rms value) a-weighted - 38 m v d intermodulation distortion/comparator f = 60 hz and 7 khz, rati o4:1 -- 70 - 55 db f s(max) maximum sample frequency 48 -- khz b dac bandwidth dac at - 3db - 1 2 f s - khz c l(dac) load capacitance on dac outputs -- 2.5 nf r l(dac) load resistance on dac voltage outputs dc decoupled 5 -- k w 1999 aug 05 33 philips semiconductors preliminary speci?cation sound effects dsp SAA7712H 14 oscillator characteristics note 1. c p is the parasitic parallel capacitance of the crystal. symbol parameter conditions min. typ. max. unit f xtal crystal frequency 10.000 - 19.456 mhz d f xtal(adj) crystal frequency variation with adjustment t amb =25 c - 30 - +30 ppm d f xtal(t) crystal frequency variation with temperature - 30 - +30 ppm a f spurious frequency attenuation 20 -- db v xtal(m) voltage across the crystal (absolute peak value) 1.6 2.6 3.6 v g m(start) transconductance at start-up 10.5 19 32 ms g m(oper) transconductance when operating 3.6 - 38 ms c l capacitive load of clock output - 15 - pf n cy(start) number of cycles during start-up depends on quality of the external crystal - 1000 - cycles i xtal supply current at start-up - 715ma at oscillation - 0.6 2 ma in slave mode - 0.65 0.9 ma p xtal drive level at oscillation - 0.4 0.5 mw v i(clk) external clock input voltage in slave mode 3 3.3 3.6 v r xtal allowed loss resistance of the crystal c p =5pf (1) ; c1 = 10 pf; c2 = 10 pf; see fig.9 - 20 100 w r o output resistance at start-up; f xtal = 18.432 mhz; v dd_osc = 3.3 v 750 1300 2800 w 1999 aug 05 34 philips semiconductors preliminary speci?cation sound effects dsp SAA7712H 15 i 2 s-bus timing characteristics timing of the serial digital data inputs and outputs (see fig.17). symbol parameter min. max. unit t cy bit clock cycle time 70 - ns t su(d) data set-up time (host) 32 - ns data set-up time (i 2 s-bus) 10 - ns t h(d) data hold time (host) 5 - ns data hold time (i 2 s-bus) 10 - ns t su(ws) word select set-up time (i 2 s-bus) 10 - ns t h(ws) word select hold time (i 2 s-bus) 10 - ns t d(d) data delay time (host) - 20 ns t d(ws) word select delay time (host) - 15 ns fig.17 timing definitions of the serial digital inputs and outputs. handbook, full pagewidth mgs220 ws in data in lsb msb bck right left t h(ws) t r t bck(h) t f t bck(l) t cy t su(ws) t d(ws) t d(d) t su(d) t h(d) ws out data out 1999 aug 05 35 philips semiconductors preliminary speci?cation sound effects dsp SAA7712H 16 i 2 c-bus timing characteristics timing of the i 2 c-bus (see fig.18); all values referred to v ih and v il (see section 12). note 1. c b is the bus line capacitance in pf. symbol parameter conditions min. max. unit f scl scl clock frequency 0 400 khz t buf bus free time between a stop and start condition 1.3 -m s t hd;sta hold time (repeated) start condition; after this period, the ?rst clock pulse is generated 0.6 -m s t low low period of the scl clock 1.3 -m s t high high period of the scl clock 0.6 -m s t su;sta set-up time for a repeated start condition 0.6 -m s t hd;dat data hold time 0 0.9 m s t su;dat data set-up time for standard mode i 2 c-bus system t su;dat > 250 ns 100 - ns t r rise time of both sda and scl signals f scl = 400 khz 20 + 0.1c b (1) 300 ns f scl = 100 khz 20 + 0.1c b (1) 1000 ns t f fall time of both sda and scl signals 20 + 0.1c b (1) 300 ns t su;sto set-up time for stop condition 0.6 -m s c b capacitive load for each bus line - 400 pf t sp maximum pulse width for spike suppression - 50 ns 1999 aug 05 36 philips semiconductors preliminary speci?cation sound effects dsp SAA7712H this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... handbook, full pagewidth mbc611 p s sr p t su;sto t sp t hd;sta t su;sta t su;dat t f t high t r t hd;dat t low t hd;sta t buf sda scl fig.18 timing definition of the i 2 c-bus. 1999 aug 05 37 philips semiconductors preliminary speci?cation sound effects dsp SAA7712H 17 application information the application diagram (see fig.19) must be considered as one of the examples of a (limited) application of the chip e.g. in this case the i 2 s-bus inputs are not used. for the real application set-up the information of the application report and application support by philips are necessary on issues such as emc, kappa reduction of the package, dsp programming, etc. fig.19 application diagram. handbook, full pagewidth mgs222 27 29 28 24 26 25 i 2 s_in1_ws i 2 s_in1_bck i 2 s_in1_data i 2 s_in2_ws i 2 s_in2_bck i 2 s_in2_data dsp quad dac equalizer i 2 c-bus interface oscillator pll 2 i 2 s-bus input switch out0_i 18 v ddd5v1 22 + 5 v out0_v 19 out1_i 17 out1_v 16 out2_i 11 out2_v 12 out3_i 10 out3_v host i/o 33 32 30 36 63 62 31 37 48 47 13 23 35 56 9 SAA7712H i 2 s_io_bck i 2 s_io_in1 i 2 s_io_out1 i 2 s_io_ws i 2 s_io_in2 i 2 s_io_out2 v ssd5v2 42 22 nf blm32a07 22 nf 22 nf 22 nf v ddd5v3 + 5 v 34 v ddd5v2 52 v ddd3v1 53 v ddd3v2 + 3 v + 3 v + 3 v 14 v dda2 v ssd5v1 test2 test1 v ssd3v6 44 45 46 sda 57 dsp_reset scl a0 v ssa2 osc_out osc_in 100 w 1.8 nf out0 100 w 1.8 nf out1 10 nf 10 nf + 5 v 100 w 1.8 nf out2 100 w 1.8 nf out3 vrefda 15 10 nf 10 nf 22 m f 1 m f pom 8 4.7 m f 43 49 50 51 v ssd3v2 v ssd3v1 v ssd3v3 v ssd5v3 54 55 v ssd3v5 v ssd3v4 dsp_in2 39 dsp_out1 40 dsp_out2 41 eqov 20 58 rtcb 59 shtcb 64 61 60 tscan 4.7 k w 4.7 k w dsp_in1 38 100 nf 10 pf 10 pf 11.2896 mhz + 5 v 21 sys_clk v dd_osc v ss_osc blm32a07 1999 aug 05 38 philips semiconductors preliminary speci?cation sound effects dsp SAA7712H 18 package outline unit a 1 a 2 a 3 b p ce (1) eh e ll p z y w v q references outline version european projection issue date iec jedec eiaj mm 0.36 0.10 2.87 2.57 0.25 0.45 0.30 0.25 0.13 14.1 13.9 0.8 18.2 17.6 1.2 0.8 7 0 o o 0.2 0.1 0.2 1.95 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 1.0 0.6 sot318-1 95-02-04 97-08-01 d (1) (1) (1) 20.1 19.9 h d 24.2 23.6 e z 1.0 0.6 d b p e q e a 1 a l p detail x l (a ) 3 b 24 c b p e h a 2 d h v m b d z d a z e e v m a 1 80 65 64 41 40 25 pin 1 index x y w m w m 0 5 10 mm scale 80 leads (lead length 1.95 mm); body 14 x 20 x 2.7 mm; high stand-off height qfp80: plastic quad flat package; sot318-1 a max. 3.3 1999 aug 05 39 philips semiconductors preliminary speci?cation sound effects dsp SAA7712H 19 soldering 19.1 introduction to soldering surface mount packages this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all surface mount ic packages. wave soldering is not always suitable for surface mount ics, or for printed-circuit boards with high population densities. in these situations reflow soldering is often used. 19.2 re?ow soldering reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. typical reflow peak temperatures range from 215 to 250 c. the top-surface temperature of the packages should preferable be kept below 230 c. 19.3 wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was specifically developed. if wave soldering is used the following conditions must be observed for optimal results: use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 19.4 manual soldering fix the component by first soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c. 1999 aug 05 40 philips semiconductors preliminary speci?cation sound effects dsp SAA7712H 19.5 suitability of surface mount ic packages for wave and re?ow soldering methods notes 1. all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . 2. these packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. 4. wave soldering is only suitable for lqfp, tqfp and qfp packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. wave soldering is only suitable for ssop and tssop packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. package soldering method wave reflow (1) bga, sqfp not suitable suitable hlqfp, hsqfp, hsop, htssop, sms not suitable (2) suitable plcc (3) , so, soj suitable suitable lqfp, qfp, tqfp not recommended (3)(4) suitable ssop, tssop, vso not recommended (5) suitable 1999 aug 05 41 philips semiconductors preliminary speci?cation sound effects dsp SAA7712H 20 definitions 21 life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. 22 purchase of philips i 2 c components data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation. purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011. 1999 aug 05 42 philips semiconductors preliminary speci?cation sound effects dsp SAA7712H notes 1999 aug 05 43 philips semiconductors preliminary speci?cation sound effects dsp SAA7712H notes ? philips electronics n.v. sca all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. internet: http://www.semiconductors.philips.com 1999 67 philips semiconductors C a worldwide company for all other countries apply to: philips semiconductors, international marketing & sales communications, building be-p, p.o. box 218, 5600 md eindhoven, the netherlands, fax. +31 40 27 24825 argentina: see south america australia: 3 figtree drive, homebush, nsw 2140, tel. +61 2 9704 8141, fax. +61 2 9704 8139 austria: computerstr. 6, a-1101 wien, p.o. box 213, tel. +43 1 60 101 1248, fax. +43 1 60 101 1210 belarus: hotel minsk business center, bld. 3, r. 1211, volodarski str. 6, 220050 minsk, tel. +375 172 20 0733, fax. +375 172 20 0773 belgium: see the netherlands brazil: see south america bulgaria: philips bulgaria ltd., energoproject, 15th floor, 51 james bourchier blvd., 1407 sofia, tel. +359 2 68 9211, fax. +359 2 68 9102 canada: philips semiconductors/components, tel. +1 800 234 7381, fax. +1 800 943 0087 china/hong kong: 501 hong kong industrial technology centre, 72 tat chee avenue, kowloon tong, hong kong, tel. +852 2319 7888, fax. +852 2319 7700 colombia: see south america czech republic: see austria denmark: sydhavnsgade 23, 1780 copenhagen v, tel. +45 33 29 3333, fax. +45 33 29 3905 finland: sinikalliontie 3, fin-02630 espoo, tel. +358 9 615 800, fax. +358 9 6158 0920 france: 51 rue carnot, bp317, 92156 suresnes cedex, tel. +33 1 4099 6161, fax. +33 1 4099 6427 germany: hammerbrookstra?e 69, d-20097 hamburg, tel. +49 40 2353 60, fax. +49 40 2353 6300 hungary: see austria india: philips india ltd, band box building, 2nd floor, 254-d, dr. annie besant road, worli, mumbai 400 025, tel. +91 22 493 8541, fax. +91 22 493 0966 indonesia: pt philips development corporation, semiconductors division, gedung philips, jl. buncit raya kav.99-100, jakarta 12510, tel. +62 21 794 0040 ext. 2501, fax. +62 21 794 0080 ireland: newstead, clonskeagh, dublin 14, tel. +353 1 7640 000, fax. +353 1 7640 200 israel: rapac electronics, 7 kehilat saloniki st, po box 18053, tel aviv 61180, tel. +972 3 645 0444, fax. +972 3 649 1007 italy: philips semiconductors, via casati, 23 - 20052 monza (mi), tel. +39 039 203 6838, fax +39 039 203 6800 japan: philips bldg 13-37, kohnan 2-chome, minato-ku, tokyo 108-8507, tel. +81 3 3740 5130, fax. +81 3 3740 5057 korea: philips house, 260-199 itaewon-dong, yongsan-ku, seoul, tel. +82 2 709 1412, fax. +82 2 709 1415 malaysia: no. 76 jalan universiti, 46200 petaling jaya, selangor, tel. +60 3 750 5214, fax. +60 3 757 4880 mexico: 5900 gateway east, suite 200, el paso, texas 79905, tel. +9-5 800 234 7381, fax +9-5 800 943 0087 middle east: see italy netherlands: postbus 90050, 5600 pb eindhoven, bldg. vb, tel. +31 40 27 82785, fax. +31 40 27 88399 new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. +64 9 849 4160, fax. +64 9 849 7811 norway: box 1, manglerud 0612, oslo, tel. +47 22 74 8000, fax. +47 22 74 8341 pakistan: see singapore philippines: philips semiconductors philippines inc., 106 valero st. salcedo village, p.o. box 2108 mcc, makati, metro manila, tel. +63 2 816 6380, fax. +63 2 817 3474 poland: ul. lukiska 10, pl 04-123 warszawa, tel. +48 22 612 2831, fax. +48 22 612 2327 portugal: see spain romania: see italy russia: philips russia, ul. usatcheva 35a, 119048 moscow, tel. +7 095 755 6918, fax. +7 095 755 6919 singapore: lorong 1, toa payoh, singapore 319762, tel. +65 350 2538, fax. +65 251 6500 slovakia: see austria slovenia: see italy south africa: s.a. philips pty ltd., 195-215 main road martindale, 2092 johannesburg, p.o. box 58088 newville 2114, tel. +27 11 471 5401, fax. +27 11 471 5398 south america: al. vicente pinzon, 173, 6th floor, 04547-130 s?o paulo, sp, brazil, tel. +55 11 821 2333, fax. +55 11 821 2382 spain: balmes 22, 08007 barcelona, tel. +34 93 301 6312, fax. +34 93 301 4107 sweden: kottbygatan 7, akalla, s-16485 stockholm, tel. +46 8 5985 2000, fax. +46 8 5985 2745 switzerland: allmendstrasse 140, ch-8027 zrich, tel. +41 1 488 2741 fax. +41 1 488 3263 taiwan: philips semiconductors, 6f, no. 96, chien kuo n. rd., sec. 1, taipei, taiwan tel. +886 2 2134 2886, fax. +886 2 2134 2874 thailand: philips electronics (thailand) ltd., 209/2 sanpavuth-bangna road prakanong, bangkok 10260, tel. +66 2 745 4090, fax. +66 2 398 0793 turkey: yukari dudullu, org. san. blg., 2.cad. nr. 28 81260 umraniye, istanbul, tel. +90 216 522 1500, fax. +90 216 522 1813 ukraine : philips ukraine, 4 patrice lumumba str., building b, floor 7, 252042 kiev, tel. +380 44 264 2776, fax. +380 44 268 0461 united kingdom: philips semiconductors ltd., 276 bath road, hayes, middlesex ub3 5bx, tel. +44 208 730 5000, fax. +44 208 754 8421 united states: 811 east arques avenue, sunnyvale, ca 94088-3409, tel. +1 800 234 7381, fax. +1 800 943 0087 uruguay: see south america vietnam: see singapore yugoslavia: philips, trg n. pasica 5/v, 11000 beograd, tel. +381 11 62 5344, fax.+381 11 63 5777 printed in the netherlands 545004/25/01/pp 44 date of release: 1999 aug 05 document order number: 9397 750 04868 |
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