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etrontech em66932a etron technology, inc. no. 6, technology rd. v, science-based industrial park, hsinchu, taiwan 30077, r.o.c tel: (886)-3-5782345 fax: (886)-3-5778671 etron technology, inc., reserves the right to make changes to its products and specifications without notice. 4m x 32 hand-held low power sdram (lpsdram) preliminary (rev 0.1 june/2003) features ? clock rate: 133/125/100 mhz ? fully synchronous operation ? internal pipelined architecture ? four internal banks (1m x 32bit x 4bank) ? programmable mode - cas# latency: 1, 2 & 3 - burst length: 1, 2, 4, 8, or full page - burst type: sequential & interleave - burst-read-single-write - driving strenght : full & half - pasr (partial array self refresh) - tcsr (temperature compensated self refresh) ? burst stop function ? individual byte controlled by dqm0-3 ? auto refresh and self refresh pin assignment : top view ? 4096 refresh cycles/64ms ? single 3.0v, or 3.3v power supply ? interface: lvttl ? package : 90 ball-fbga, 11x13mm, lead free ordering information part number frequency package em66932abg-7.5g 133mhz 11x13 bga em66932abg-8g 125mhz 11x13 bga em66932abg-1h/lg 100mhz 11x13 bga 8 7 6 5 4 3 2 1 m l k j h g f e d c b a dq26 dq24 dq28 vddq vssq dq27 vssq dq29 vdd dq23 vddq vssq dq22 dq20 dq17 vdd1q vddq dq31 vss dqm3 a4 a5 a7 a8 dq18 vssq nc dq16 dqm2 vdd a2 a1 clk cke dqm1 nc vddq dq8 vssq dq10 a10 a0 nc a11 cas# ba1 dqm0 we# vssq dq7 vssq dq12 vddq vddq dq6 dq5 dq11 vddq dq13 dq15 n p r dq21 dq19 vddq ba0 cs# ras# dq1 dq3 vddq vdd vssq dq4 vdd dq0 dq2 vss vssq dq25 dq30 nc a3 a6 nc a9 nc vss dq9 dq14 vssq vss 9
etrontech 4m x 32 hh lpsdram em66932a preliminary 2 rev 0.1 june 2003 overview the em66932a hand-held lpsdram is a 128m bits high-speed cmos synchronous dram with low power consumption organized as 1,048,576 words by 32 bits by 4 banks. the hand-held functions are new features of the size of the memory array and the refresh period during self-refresh to be programmable by which the self refresh current is drastically reduced. high data transfer rate is achieved by the pipeline architecture with a synchronous interface, burst oriented read and write accesse, muti banks operation and programmable burst lengths. the em66932a provides read or write burst lengths of 1, 2, 4, 8, or full page, with a burst termination option. through the programming burst type, burst length, cas latency, and driving strength in mode register and extended mode register, a variety with high performance is fulfilled and useful in a variety of wide bandwidth, high performance and low power application. block diagram refresh coun ter co lu mn coun ter address buffer a0 a9 a10 a11 ba0 ba1 co ntrol signal ge n er a t or dqm0~3 clo ck buffer co mmand decoder column decoder sense amplifier row decoder 4096 x 256 x 32 cell array (bank #0) sense amplifier column decoder row decoder 4096 x 256 x 32 cell array (bank #3) mode register cl k cke cs # ra s# ca s# we# a10/ap dq 0 dq31 sense amplifier column decoder row decoder 4096x 256 x 32 cell array (bank #1) sense amplifier column decoder row decoder 4096 x 256 x 32 cell array (bank #2) dq buffer
etrontech 4m x 32 hh lpsdram em66932a preliminary 3 rev 0.1 june 2003 pin descriptions table 1. pin details of 4mx32 hh lpsdram symbol type description clk input clock: clk is driven by the system clock. all sdram input signals are sampled on the positive edge of clk. clk also increments the internal burst counter and controls the output registers. cke input clock enable: cke activates(high) and deactivates(low) the clk signal. if cke goes low synchronously with clock(set- up and hold time same as other inputs), the internal clock is suspended from the next clock cycle and the state of output and burst address is frozen as long as the cke remains low. when all banks are in the idle state, deactivating the clock controls the entry to the power down and self refresh modes. cke is synchronous except after the device enters power down and self refresh modes, where cke becomes asynchronous until exiting the same mode. the input buffers, including clk, are disabled during power down and self refresh modes, providing low standby power. ba0, ba1 input bank select: ba0 and ba1 defines to which bank the bank activate, read, write, or bankprecharge command is being applied. the bank address ba0 and ba1 is used latched in mode register set. a0-a11 input address i nputs: a0-a11 are sampled during the bankactivate command (row address a0- a11) and read/write command (column address a0- a7 with a10 defining auto precharge) to select one location out of the 1m available in the respective bank. during a precharge command, a10 is sampled to determine if all banks are to be precharged (a10 = high). the address inputs also provide the op- code during a mode register set or special mode register set command. cs# input chip select: cs# enables (sampled low) and disables (sampled high) the command decoder. all commands are masked when cs# is sampled high. cs# provides for ext ernal bank selection on systems with multiple banks. it is considered part of the command code. ras# input row address strobe: the ras# signal defines the operation commands in conjunction with the cas# and we# signals and is latched at the positive edges of clk. when ras# and cs# are asserted "low" and cas# is asserted "high," either the bankactivate command or the precharge command is selected by the we# signal. when the we# is asserted "high," the bankactivate command is selected and the bank designated by bs is turned on to the active state. when the we# is asserted "low," the precharge command is selected and the bank designated by bs is switched to the idle state after the precharge operation. cas# input column address strobe: the cas# signal defines the operation commands in conjunction with the ras# and we# signals and is latched at the positive edges of clk. when ras# is held "high" and cs# is asserted "low," the column access is started by asserting cas# "low." then, the read or write command is s elected by asserting we# "low" or "high." we# input write enable: the we# signal defines the operation commands in conjunction with the ras# and cas# signals and is latched at the positive edges of clk. the we# input is used to select the bankactivate or precharge command and read or write command. dqm0 - dqm3 input data input/output mask: data input mask: dm0- dm3 are byte specific. input data is masked when dm is sampled high during a write cycle. dm3 masks dq31- dq24, dm2 masks dq23-dq16, dm1 masks dq15-dq8, and dm0 masks dq7-dq0. dq0- dq31 input/ output data i/o: the dq0- 31 input and output data are synchronized with the positive edges of clk. the i/os are byte-maskable during r eads and writes. nc - no connect: these pins should be left unconnected. v ddq supply dq power: provide isolated power to dqs for improved noise immunity.
etrontech 4m x 32 hh lpsdram em66932a preliminary 4 rev 0.1 june 2003 v ssq supply dq ground: provide isolated ground to dqs for improved noise immunity. v dd supply power supply: +3.0v 0.3v, or +3.3v 0.3v v ss supply ground
etrontech 4m x 32 hh lpsdram em66932a preliminary 5 rev 0.1 june 2003 operation mode fully synchronous operations are performed to latch the commands at the positive edges of clk. table 2 shows the truth table for the operation commands. table 2. truth table (note (1), (2) ) command state cke n-1 cke n dqm (6) bs 0,1 a 10 a 11 , a 9-0 cs# ras# cas# we# bankactivate idle (3) h x x v row address l l h h bankprecharge any h x x v l x l l h l prechargeall any h x x x h x l l h l write active (3) h x x v l l h l l w rite and autoprecharge active (3) h x x v h column address (a0 ~ a7) l h l l read active (3) h x x v l l h l h read and autoprecharge active (3) h x x v h column address (a0 ~ a7) l h l h mode register set idle h x x op code l l l l no-operation any h x x x x x l h h h burst stop active (4) h x x x x x l h h l device deselect any h x x x x x h x x x autorefresh idle h h x x x x l l l h selfrefresh entry idle h l x x x x l l l h selfrefresh exit idle l h x x x x h x x x (selfrefresh) l h h h clock suspend mode entry active h l x x x x h x x x l h h h power down mode entry any (5) h l x x x x h x x x l h h h clock suspend mode exit active l h x x x x x x x x power down mode exit any l h x x x x h x x x (powerdown) l h h h data write/output enable active h x l x x x x x x x data mask/output disable active h x h x x x x x x x note: 1. v = valid, x = don't care, l = logic low, h = logic high 2. cke n signal is input level when commands are provided. cke n-1 signal is input level one clock cycl e before the commands are provided. 3. these are states of bank designated by ba signal. 4. device state is 1, 2, 4, 8, and full page burst operation. 5. power down mode can not enter in the burst operation. when this command is asserted in the burst cycle, devic e state is clock suspend mode. 6. dqm0-3
etrontech 4m x 32 hh lpsdram em66932a preliminary 6 rev 0.1 june 2003 commands 1 bankactivate (ras# = "l", cas# = "h", we# = "h", ba 0,1= bank, a0-a11 = row address) the bankactivate command activates the idle bank designated by the ba0,1 (bank select) signal. by latching the row address on a0 to a11 at the time of this command, the selected row access is initiated. the read or write operation in the same bank can occur after a time delay of t rcd (min.) from the time of bank activation. a subsequent bankactivate command to a different row in the same bank can only be issued after the previous active row has been precharged (refer to the following figure). the minimum time interval between successive bankactivate commands to the same bank is defined by t rc (min.). the sdram has four internal banks on the same chip and shares part of the internal circuitry to reduce chip area; therefore it restricts the back-to-back activation of the four banks. t rrd (min.) specifies the minimum time required between activating different banks. after this command is used, the write command and the block write command perform the no mask write operation. clk address t0 t 1 t2 t3 tn+3 tn+4 tn+5 tn+6 .............. command .............. .............. nop nop nop nop ras# - cas# delay ( t rcd ) ras# - ras# delay time ( t rrd ) ras# cycle time ( t rc ) bank a row addr. bank a col addr. bank b row addr. bank a row addr. bank a activate r/w a with autoprecharge bank b activate bank a activate autoprecharge begin : "h" or "l" bankactivate command cycle (burst length = n, cas# latency = 3) 2 bankprecharge command (ras# = "l", cas# = "h", we# = "l", ba0,1 = bank, a10 = "l", a0-a9, a11 = don't care) the bankprecharge command precharges the bank disignated by ba0,1 signal. the precharged bank is switched from the active state to the idle state. this command can be asserted anytime after t ras (min.) is satisfied from the bankactivate command in the desired bank. the maximum time any bank can be active is specified by t ras (max.). therefore, the precharge function must be performed in any active bank within t ras (max.). at the end of precharge, the precharged bank is st ill in the idle state and is ready to be activated again. 3 prechargeall command (ras# = "l", cas# = "h", we# = "l", ba0,1 = don?t care, a10 = "h", a0-a9, a11 = don't care) the prechargeall command precharges all the four banks simultaneously and can be issued even if all banks are not in the active state. all banks are then switched to the idle state. 4 read command (ras# = "h", cas# = "l", we# = "h", ba0,1 = bank, a10 = "l", a0-a7 = column address) the read command is used to read a burst of data on consecutive clock cycles from an active row in an active bank. the bank must be active for at least t rcd (min.) before the read command is issued. during read bursts, the valid data-out element from the starting column address will be available following the cas# latency after the issue of the read command. each subsequent data- out element will be valid by the next positive clock edge (refer to the following figure). the dqs go into high-impedance at the end of the burst unless other command is initiated. the burst length, burst sequence, and cas# latency are determined by the mode register which is already programmed. a full-page burst will continue until terminated (at the end of the page it will wrap to column 0 and continue).
etrontech 4m x 32 hh lpsdram em66932a preliminary 7 rev 0.1 june 2003 cl k command cas# latency=2 t ck2 , dq's cas# latency=3 t ck3 , dq's t0 t 1 t2 t3 t4 t5 t6 t7 t8 read a nop nop nop nop nop nop nop nop dout a 0 dout a 1 dout a 2 dout a 3 dout a 0 dout a 1 dout a 2 dout a 3 burst read operation(burst length = 4, cas# latency = 2, 3) the read data appears on the dqs subject to the values on the dqm inputs two clocks earlier (i.e. dqm latency is two clocks for output buffers). a read burst without the auto precharge function may be interrupted by a subsequent read or write command to the same bank or the other active bank before the end of the burst length. it may be interrupted by a bankprecharge/ prechargeall command to the same bank too. the interrupt coming from the read command can occur on any clock cycle following a prev ious read command (refer to the following figure). clk command cas# latency=2 t ck2 , dq's cas# latency=3 t ck3 , dq's t0t 1t2t3t4t5t6t7t8 read a read b nop nop nop nop nop nop nop dout a 0 dout b 0 dout b 1 dout b 2 dout b 3 dout a 0 dout b 0 dout b 1 dout b 2 dout b 3 read interrupted by a read (burst length = 4, cas# latency = 2, 3) the dqm inputs are used to avoid i/o contention on the dq pins when the interrupt comes from a write command. the dqms must be asserted (high) at least two clocks prior to the write command to suppress data-out on the dq pins. to guarantee the dq pins against i/o contention, a single cycle with high-impedance on the dq pins must occur between the last read data and the write command (refer to the following three figures). if the data output of the burst read occurs at the second clock of the burst write, the dqms must be asserted (high) at least one clock prior to the write command to avoid internal bus contention.
etrontech 4m x 32 hh lpsdram em66932a preliminary 8 rev 0.1 june 2003 read a nop nop nop nop w rite b nop nop clk dqm command dq's t0t 1t2t3t4t5 t6t7 t8 nop dout a 0 dinb 0 dinb 1 dinb 2 must be hi-z before the write command : "h" or "l" read to write interval (burst length R 4, cas# latency = 3) clk dqm command t0t 1 t2t3 t4t5 t6t7 t8 nop nop nop nop nop nop banka activate din a 0 din a 1 din a 2 din a 3 1 clk interval cas# latency=2 t ck2 , dq's read a write a : "h" or "l" read to write interval (burst length 4, cas# latency = 2) clk dqm command t0 t 1 t2 t3 t4 t5 t6 t7 t8 nop read a nop write b nop nop nop din b 0 din b 1 din b 2 din b 3 cas# latency=2 t ck2 , dq's nop nop : "h" or "l" read to write interval (burst length 4, cas# latency = 2) a read burst without the auto precharge function may be interrupted by a bankprecharge/ prechargeall command to the same bank. the following figure shows the optimum time that bankprecharge/ prechargeall command is issued in different cas# latency.
etrontech 4m x 32 hh lpsdram em66932a preliminary 9 rev 0.1 june 2003 cl k command cas# latency=2 t ck2 , dq's t0t 1 t2t3 t4t5 t6t7 t8 read a nop nop nop nop activate nop nop precharge cas# latency=3 t ck3 , dq's dout a 0 dout a 1 dout a 2 dout a 3 dout a 0 dout a 1 dout a 2 dout a 3 address t rp bank, col a bank(s) bank, row read to precharge (cas# latency = 2, 3) 5 read and autoprecharge command (ras# = "h", cas# = "l", we# = "h", bs = bank, a10 = "h", a0-a7 = column address) the read and autoprecharge command automatically performs the precharge operation after the read operation. once this command is given, any subsequent command cannot occur within a time delay of {t rp (min.) + burst length}. at full-page burst, only the read operation is performed in this command and the auto precharge function is ignored. 6 write command (ras# = "h", cas# = "l", we# = "l", bs = bank, a10 = "l", a0-a7 = column address) the write command is used to write a burst of data on consecutive clock cycles from an active row in an active bank. the bank must be active for at least t rcd (min.) before the write command is issued. during write bursts, the first valid data-in element will be registered coincident with the write command. subsequent data elements will be registered on each successive positive clock edge (refer to the following figure). the dqs remain with high-impedance at the end of the burst unless another command is initiated. the burst length and burst sequence are determined by the mode register, which is already programmed. a full-page burst w ill conti nue until terminated (at the end of the page it w ill wrap to column 0 and continue). clk command t0t 1t2t3t4t5 t6t7 t8 din a 3 nop w rite a nop nop nop nop nop nop nop din a 0 din a 1 din a 2 dq0 - dq3 the first data element and the write are registered on the same clock edge. extra data is masked. don't care burst write operation (burst length = 4, cas# latency = 1, 2, 3) a write burst without the autoprecharge function may be interrupted by a subsequent write, bankprecharge/prechargeall, or read command before the end of the burst length. an interrupt coming from write command can occur on any clock cycle following the previous write command (refer to the following figure).
etrontech 4m x 32 hh lpsdram em66932a preliminary 10 rev 0.1 june 2003 clk command t0t 1 t2t3 t4t5 t6t7 t8 din b 2 nop w r i te a nop nop nop nop nop write b nop din a 0 din b 0 din b 1 dq's din b 3 1 clk interval write interrupted by a write (burst length = 4, cas# latency = 1, 2, 3) the read command that interrupts a write burst without auto precharge function should be issued one cycle after the clock edge in which the last data-in element is registered. in order to avoid data contention, input data must be removed from the dqs at least one clock cycle before the first read data appears on the outputs (refer to the following figure). once the read command is registered, the data inputs w ill be i gnored and writes w ill not be executed. clk command t0t 1 t2t3 t4t5 t6t7 t8 nop write a nop nop nop nop nop read b nop din a 0 don't care dout b 2 dout b 0 dout b 1 dout b 3 din a 0 don't care don't care dout b 2 dout b 0 dout b 1 dout b 3 in pu t data for the write is m asked. input data must be removed from the dq's at least one clock cycle before the read data appears on the outputs to avoid data contention. cas# latency=2 t ck2 , dq's cas# latency=3 t ck3 , dq's write interrupted by a read (burst length = 4, cas# latency = 2, 3) the bankprecharge/prechargeall command that interrupts a write burst without the auto precharge function should be issued m cycles after the clo ck edge in which the la st data-in element is registered, where m equals t wr /t ck rounded up to the next whole number. in addition, the dqm signals must be used to mask input data, starting with the clock edge following the last data-in element and ending with the clock edge on which the bankprecharge/prechargeall command is entered (refer to the following figure). clk t0t 1t2t3t4t5 t6 write command bank (s) row nop nop precharge nop nop activate bank co l n din n din n + 1 dqm address dq t wr t rp : don't care note: the dqms can remain low in this example if the length of the write burst is 1 or 2. write to precharge
etrontech 4m x 32 hh lpsdram em66932a preliminary 11 rev 0.1 june 2003 7 write and autoprecharge command (refer to the following figure) (ras# = "h", cas# = "l", we# = "l", bs = bank, a10 = "h", a0-a7 = column address) the write and autoprecharge command performs the precharge operation automatically after the write operation. once this command is given, any subsequent command can not occur within a time delay of {(burst length -1) + t wr + t rp (min.)}. at full-page burst, only the write operation is performed in this command and the auto precharge function is ignored. 8 mode register set command (ras# = "l", cas# = "l", we# = "l", bs0,1 and a11-a0 = register data) the mode register stores the data for controlling the various operating modes of sdram. the mode register set command programs the values of cas# latency, addressing mode and burst length in the mode register to make sdram useful for a variety of different applications. the default values of the mode register after power-up are undefined; therefore this command must be issued at the power-up sequence. the state of pins ba0,1 and a11~a0 in the same cycle is the data written to the mode register. one clock cycle is required to complete the write in the mode register (refer to the following figure). the contents of the mode register can be changed using the same command and the clock cycle require ments during operation as long as a ll banks are in the idle state. ras# t0 t 1 t2 t3 t4t5 t6t7 t8t9 t10 clk cke cs# cas# we# addr. dqm dq t ck2 clock min. address key t rp hi-z prechargeall mode register set command any command mode register set cycle (cas# latency = 2, 3)
etrontech 4m x 32 hh lpsdram em66932a preliminary 12 rev 0.1 june 2003 mode resistor bitmap ba1 ba0 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0 0 0 0 w.b.l tm cas latency bt burst length a9 length a8 a7 mode a3 type 0 burst 0 0 normal 0 sequential 1 single bit 1 0 reserved 1 interleave 0 1 reserved a6 a5 a4 cas latency a2 a1 a0 burst length 0 0 0 reserved 0 0 0 1 0 0 1 1 clock 0 0 1 2 0 1 0 2 clocks 0 1 0 4 0 1 1 3 clocks 0 1 1 8 1 0 1 reserved 1 1 1 full page (sequential) all other reserved all other reserved burst definition, addressing sequence of sequential and interleave mode start address burst length a2 a1 a0 sequential interleave x x 0 0, 1 0, 1 2 x x 1 1, 0 1, 0 x 0 0 0, 1, 2, 3 0, 1, 2, 3 x 0 1 1, 2, 3, 0 1, 0, 3, 2 x 1 0 2, 3, 0, 1 2, 3, 0, 1 4 x 1 1 3, 0, 1, 2 3, 2, 1, 0 0 0 0 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 0 0 1 1, 2, 3, 4, 5, 6, 7, 0 1, 0, 3, 2, 5, 4, 7, 6 0 1 0 2, 3, 4, 5, 6, 7, 0, 1 2, 3, 0, 1, 6, 7, 4, 5 0 1 1 3, 4, 5, 6, 7, 0, 1, 2 3, 2, 1, 0, 7, 6, 5, 4 1 0 0 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 1 0 1 5, 6, 7, 0, 1, 2, 3, 4 5, 4, 7, 6, 1, 0, 3, 2 1 1 0 6, 7, 0, 1, 2, 3, 4, 5 6, 7, 4, 5, 2, 3, 0, 1 8 1 1 1 7, 0, 1, 2, 3, 4, 5, 6 7, 6, 5, 4, 3, 2, 1, 0
etrontech 4m x 32 hh lpsdram em66932a preliminary 13 rev 0.1 june 2003 extended mode resistor bitmap ba1 ba0 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 1 0 0 0 0 0 0 ds tcsr pasr note : 1 rfu: reserved for furture use 2 64m partial refresh, 2banks(ba1=0) is selected. 3 32m partial refresh, 1bank(ba1=ba0=0) is selected. 4 16m partial refresh, 1/2bank(ba1=ba0=0, a11=0) is selected. 5 8m partial refresh, 1/4bank(ba1=ba0=0, a11=a10=0) is selected. self refresh currency of pasr and tcsr idd 6 (ua) max temperature all banks 2 banks 1 bank 1/2 bank 1/4 bank 85 1200 920 710 545 420 70 800 575 415 276 200 45 455 345 230 185 160 15 265 155 115 95 90 a6 a5 strength a2 a1 a0 0 0 full drive strenght 0 0 0 all banks 0 1 half drive strenght 0 0 1 2 banks 2 1 0 rfu 1 0 1 0 1 bank 3 drive strength 1 1 rfu 1 0 1 1 rfu 1 1 0 0 rfu 1 1 0 1 1/2 bank 4 1 1 0 1/4 bank 5 patial array self refresh 1 1 1 rfu a4 a3 max temperature 0 0 70 0 1 45 1 0 15 temperature compensated self refresh 1 1 85
etrontech 4m x 32 hh lpsdram em66932a preliminary 14 rev 0.1 june 2003 9 no-operation command (ras# = "h", cas# = "h", we# = "h") the no-operation command is used to perform a nop to the sdram which is selected (cs# is low). this prevents unwanted commands from being registered during idle or wait states. 10 burst stop command (ras# = "h", cas# = "h", we# = "l") the burst stop command is used to terminate either fixed-length or full-page bursts. this command is only effective in a read/write burst without the auto precharge function. the terminated read burst ends after a delay equal to the cas# latency (refer to the following figure). the termination of a write burst is shown in the following figure. clk command t0t 1t2t3 t4t5 t6t7 t8 read a nop nop nop nop nop nop nop burst stop cas# latency=2 t ck2 , dq's cas# latency=3 t ck3 , dq's dout a 0 dout a 1 dout a 2 dout a 3 dout a 0 dout a 1 dout a 2 dout a 3 the burst ends after a delay equal to the cas# latency. termination of a burst read operation (burst length 4, cas# latency = 2, 3) clk command t0t 1t2t3t4t5t6t7t8 nop write a nop nop nop nop nop nop burst stop cas# la tency= 2, 3 dq's din a 0 din a 1 din a 2 don't care input data for the write is masked. termination of a burst write operation (burst length = x, cas# latency = 1, 2, 3)
etrontech 4m x 32 hh lpsdram em66932a preliminary 15 rev 0.1 june 2003 11 device deselect command (cs# = "h") the device deselect command disables the command decoder so that the ras#, cas#, we# and address inputs are ignored, regardless of whether the clk is enabled. this command is similar to the no operation command. 12 autorefresh command (ras# = "l", cas# = "l", we# = "h",cke = "h", ba0,1 = ?don?t care, a0-a11 = don't care) the autorefresh command is used during normal operation of the sdram and is analogous to cas#-before-ras# (cbr) refresh in conventional drams. this command is non-persistent, so it must be issued each time a refresh is required. the addressing is generated by the internal refresh controller. this makes the address bits a "don't care" during an autorefresh command. the internal refresh counter increments automatically on every aut o refresh cycl e to all of the rows. the refresh operation must be performed 4096 times within 64ms. the time required to complete the auto refresh operation is specified by t rc (min.). to provide the autorefresh command, all banks need to be in the idle state and the device must not be in power down mode (cke is high in the previous cycle). this command must be follow ed by nops until the auto refresh operation is completed. the precharge time requirement, t rp (min), must be met before successive auto refresh operations are performed. 13 selfrefresh entry command (ras# = "l", cas# = "l", we# = "h", cke = "l", a0-a11 = don't care) the selfrefresh is another refresh mode available in the sdram. it is the preferred refresh mode for data retention and low power operation. once the selfrefresh command is registered, all the inputs to the sdram become "don't care" with the exception of cke, which must remain low. the refresh addressing and timing is internally generated to reduce power consumption. the sdram may remain in selfrefresh mode for an indefinite period. the selfrefresh mode is exited by restarting the external clock and then asserting high on cke (selfrefresh exit command). 14 selfrefresh exit command (cke = "h", cs# = "h" or cke = "h", ras# = "h", cas# = "h", we# = "h") this command is used to exit from the selfrefresh mode. once this command is registered, nop or device deselect commands must be issued for t rc (min.) because time is required for the completion of any bank currently being internally refreshed. if auto refr esh cycles in bursts are performed during normal operation, a burst of 4096 auto refres h cycles should be completed just prior to entering and just after exiting the selfrefresh mode. 15 clock suspend mode entry / powerdown mode entry command (cke = "l") when the sdram is operating the burst cycle, the internal clk is suspended(masked) from the subsequent cycle by issuing this command (asserting cke "low"). the device operation is held intact while clk is suspended. on the other hand, when all banks are in the idle state, this command performs entry into the powerdown mode. all input and output buffers (except the cke buffer) are turned off in the powerdown mode. the device may not remain in the clock suspend or powerdown state longer than the refresh period (64ms) since the command does not perform any refresh operations. 16 clock suspend mode exit / powerdown mode exit command when the internal clk has been suspended, the operation of the internal clk is reinitiated from the subsequent cycle by providing this command (asserting cke "high"). when the device is in the powerdown mode, the device exits this mode and all disabled buffers are turned on to the active state. t pde (min.) is required when the device exits from the powerdown mode. any subsequent commands can be issued after one clock cycle from t he end of this command. 17 data write / output enable, data mask / output disable command (dqm = "l", "h") during a write cycle, the dqm signal functions as a data mask and can control every word of the input data. during a read cycle, the dqm functi ons as the controller of output buffers. dqm is also used for device selection, byte selection and bus control in a memory system.
etrontech 4m x 32 hh lpsdram em66932a preliminary 16 rev 0.1 june 2003 absolute maximum rating symbol item rating unit v in , v out input, output voltage - 1.0 ~ +4.6 v v dd , v ddq power supply voltage -1.0 ~ +4.6 v t opr operating temperature -25 ~ +85 c t stg storage temperature - 55~ +150 c t solder soldering temperature (10s) 260 c p d power dissipation 1.0 w i out short circuit output current 50 ma note: stress greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. recommended d.c. operating conditions (ta = -25~85c) parameter/ condition symbol min typ max unit note dram core supply voltage v dd 2.7 3.0 3.6 v 1 i/o s upply voltage v ddq 2.7 3.0 3.6 v 1 input high (logic 1) voltage v ih 2.0 2.5 v ddq +0.3 v 1 input low (logic 0) voltage v il -0.3 0 0.8 v 1 data output high (logic 1) voltage v oh 2.4 - - v 1,2,4 data output low (logic 0) voltage v ol - - 0.4 v 1,3,5 input leakage current ( 0v Q v in Q v dd , all other pins not under test = 0v ) i il -1.5 1.5 a note: 1 all voltages are referenced to v ss . 2 iout = - 2.0ma 3 iout = + 2.0ma 4 vih (max) = 5.6v ac. the overshoot voltage duration is Q 5ns. 5 vil (min) =-2.0v ac. the undershoot voltage duration is Q 5ns. capacitance (v dd = 2.5v, f = 1mhz, ta = 25c) symbol parameter min. max. unit c i input capacitance 4 5 pf c i/o input/output c apacitance 6 8 pf note: these parameters are periodically sampled and are not 100% tested.
etrontech 4m x 32 hh lpsdram em66932a preliminary 17 rev 0.1 june 2003 d.c. characteristics (ta = -25~85c) - 75/8/1h/1l description/test c ondition symbol max. unit operating current t rc t rc (min), outputs open, input signal one transit ion per one cycle 1 bank operation i cc1 150/145/140/130 precharge standby current in power down mode t ck = 15ns, cke v il (max) i cc2p 2 precharge standby current in power down mode t ck = , cke v il (max) i cc2ps 2 precharge standby current in non-power down mode t ck = 15ns, cs# v ih (min), cke v ih input signals are changed once during 30ns. i cc2n 30 precharge standby current in non-power down mode t ck = , clk v il (max), cke v ih i cc2ns 12 active standby current in power down mode cke v il (max), t ck = 15ns i cc3p 6 ma active standby current in power down mode cke & clk v il (max), t ck = i cc3ps 6 active standby current in non-power down mode cke v ih (min), cs# v ih (min), t ck = 15ns i cc3n 60 active standby current in non-power down mode cke v ih (min), clk v il (max), t ck = i cc3ns 50 operating current (burst mode) t ck =t ck (min), outputs open, multi-bank interleave i cc4 220/210/180/170 refresh current t rc t rc (min) i cc5 250/240/220/210 bank 4 2 1 1/2 1/4 85 1200 920 710 545 420 70 800 575 415 276 200 45 455 345 230 185 160 self refresh current cke 0.2v i cc6 15 265 155 115 95 90 ua
etrontech 4m x 32 hh lpsdram em66932a preliminary 18 rev 0.1 june 2003 electrical characteristics and recommended a.c. operating conditions (v dd = 2.7v~3.6v, ta = -25~85c) (note: 1, 2, 3, 4) - 75/8/1h/1l symbol a.c. parameter min. max. unit note t rc row cycle time( same bank ) 65/66/70/84 5 t rcd ras# to cas# delay (same bank) 20/20/20/24 5 t rp precharge to refresh / row activate command (same bank) 20/20/20/24 5 t rrd row activate to row active delay (different banks) 15/16/20/20 5 t ras row activate to percharge time (same bank) 45/46/50/60 100,000 ns 5 t rdl last data in to row precharge 10 ns 5 t ck1 cl* = 1 - /- /- /25 t ck2 cl* = 2 10/10/10/12 t ck3 clock cycle time cl* = 3 7.5/8/10/10 t ch clock high time 2.5/2.7/3/3 t cl clock low time 2.5/2.7/3/3 6 t ac1 cl* = 1 - /- / -/18 t ac2 cl* = 2 6/6/6/6 t ac3 access time from clk (positive edge) cl* = 3 5.5/5.6/6/6 ns 5 t ccd cas# to cas# delay time 1 clk 5 t oh data output hold time 2 5 t lz data output low impedance 1 5 t hz1 cl* = 1 -/- /-/18 t hz2 cl* = 2 6/6/6/6 t hz3 data output high impedance cl* = 3 5.5/5.6/6/6 4 t is data/address/control input set-up time 2.5/2.7/3/3 ns 6 t ih data/address/control input hold time 1 ns 6 *cl is cas# latency.
etrontech 4m x 32 hh lpsdram em66932a preliminary 19 rev 0.1 june 2003 note: 1 power-up sequence is described in note 7. 2 a.c. test conditions lvttl interface reference level of output signals 1.4v/1.4v output load reference to the under output load (b) input signal levels (v ih /v il ) 2.4v/0.4v transition time (rise and fall) of input signals 1ns reference level of input signals 1.4v 1.4v 50 ? output 30pf 50 ? z0= lvttl d.c. test load (a) lvttl a.c. test load (b) 3. transition times are measured between v ih and v il . transition(rise and fall) of input signals are in a fixed slope (1 ns). 4. t hz defines the time in which the outputs achieve the open circuit condition and are not at reference levels. 5. if clock rising time is longer than 1 ns, ( t r / 2 -0.5) ns should be added to the parameter. 6. assumed input rise and fall time t t ( t r & t f ) = 1 ns if t r or t f is longer than 1 ns, transient time compensation should be considered, i.e., [(tr + tf)/2 - 1] ns should be added to the parameter. 7. power up sequence power up must be performed in the following sequence. 1) power must be applied to v dd and v ddq (simultaneously) when all input signals are held "nop" state and both cke = "h" and dqm = "h." the clk signals must be started at the same time. 2) after power-up, a pause of 200 seconds minimum is required. then, it is recommended that dqm is held "high" (v dd levels) to ensure dq output is in high impedance. 3) all banks must be precharged. 4) mode register set command must be asserted to initialize the mode register. 5) a minimum of 2 auto-refresh dummy cycles must be required to stabilize the internal circuitry of the device. 30pf 3.0v 1.2k 870 output
etrontech 4m x 32 hh lpsdram em66932a preliminary 20 rev 0.1 june 2003 features of the low-power sdram package: 90-fbga, 11mm x 13mm plastic package 9x15 ball array with 3 depopulated rows in center 0.8mm ball pitch low-profile, 1.2mm max height 0.35 1. 4 0 max 5.50 3.20 11.00 5.60 11.20 6.50 0.80 6.40 0.80 13.00 all dime msions are in mm. (ball-side view)

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