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1. general description the PCA85132 is a peripheral device which interfaces to almost any liquid crystal display (lcd) 1 with low multiplex rates. it generates the drive signals for any static or multiplexed lcd containing up to four backplanes and up to 160 segments. it can be easily cascaded for larger lcd applications. the pca851 32 is compatible with most microprocessors or microcontrollers and communicates via a two-line bidirectional i 2 c-bus. communication overheads are minimized by a display ram with auto-incremented addressing, by hardware subaddressing, and by display memory switching (static and duplex drive modes). aec-q100 compliant for automotive applications. 2. features and benefits ? single-chip lcd controller and driver for up to 640 elements ? selectable backplane drive configuration: st atic, 2, 3, or 4 backplane multiplexing ? 160 segment drives: ? up to eighty 7-segment numeric characters ? up to forty 14-segment alphanumeric characters ? any graphics of up to 640 elements ? may be cascaded for large lcd applications (up to 5120 elements possible) ? 160 4-bit ram for display data storage ? software programmable frame frequency in steps of 5 hz in the range of 60 hz to 90 hz; factory calibrated ? wide lcd supply range: from 1.8 v for low threshold lcds and up to 8.0 v for guest-host lcds and high threshold (automobile) twisted nematic lcds ? internal lcd bias generation with voltage-follower buffers ? selectable display bias configuration: static, 1 ? 2 ,or 1 ? 3 ? wide power supply range: from 1.8 v to 5.5 v ? lcd and logic supplies may be separated ? low power consumption, typical: i dd = 4 a, i dd(lcd) = 30 a ? 400 khz i 2 c-bus interface ? auto-incremental display data loading across device subaddress boundaries ? versatile blinking modes ? compatible with chip-o n-glass (cog) technology ? no external components ? two sets of backplane outputs for optima l cog configurations of the application PCA85132 lcd driver for lo w multiplex rates rev. 01 ? 6 may 2010 product data sheet 1. the definition of the abbreviations and acronyms used in this data sheet can be found in section 15 .
PCA85132_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 6 may 2010 2 of 53 nxp semiconductors PCA85132 lcd driver for low multiplex rates 3. ordering information [1] bump hardness see table 25 . 4. marking table 1. ordering information type number package name description delivery form [1] version PCA85132u/2da/q1 PCA85132u bare die; 197 bumps; 6.5 1.16 0.40 mm chips with hard bumps in tray PCA85132u PCA85132u/2db/q1 PCA85132u bare die; 197 bumps; 6.5 1.16 0.40 mm chips with soft bumps in tray PCA85132u table 2. marking codes type number marking code PCA85132u/2da/q1 pc85132/232-1 PCA85132u/2db/q1 pc85132/232-1
PCA85132_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 6 may 2010 3 of 53 nxp semiconductors PCA85132 lcd driver for low multiplex rates 5. block diagram fig 1. block diagram of PCA85132 013aaa059 lcd voltage selector clock select and timing blinker timebase oscillator input filters i 2 c-bus controller power-on reset clk sync osc scl sda backplane outputs display control bp0 bp1 bp2 bp3 display segment outputs display register output bank select and blink control 160 s0 to s159 sa0 v dd a0 a1 PCA85132 lcd bias generator v ss v lcd command decode write data control display ram data pointer and auto increment subaddress counter sdaack t1 t2 t3
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx PCA85132_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 6 may 2010 4 of 53 nxp semiconductors PCA85132 lcd driver for low multiplex rates 6. pinning information 6.1 pinning viewed from active side. for mechanical details, see figure 31 . fig 2. pinning diagram of PCA85132 013aaa06 0 112 0 0 sdaack 61 60 30 1 197 167 166 PCA85132 sda scl v dd v ss v lcd t3 osc t1 t2 a0 a1 sa0 clk s159 d4 s130 d3 s29 bp3 s80 s79 bp1 bp2 bp0 s131 d1 bp3 bp1 d2 s28 s0 bp2 bp0 sync +x +y
PCA85132_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 6 may 2010 5 of 53 nxp semiconductors PCA85132 lcd driver for low multiplex rates 6.2 pin description [1] for most applications sda and sdaack are shorted together (see section 12.2 ). [2] the substrate (rear side of the die) is wired to v ss but should not be electrically contacted. table 3. pin description symbol pin description sdaack [1] 1 to 3 i 2 c-bus acknowledge output sda [1] 4 to 6 i 2 c-bus serial data input scl 7 to 9 i 2 c-bus serial clock input clk 10 clock input and output v dd 11 to 13 supply voltage sync 14 cascade synchronization input and output osc 15 selection of internal or external clock t1, t2 and t3 16, 17 and 18 to 20 dedicated testing pins; to be tied to v ss in application mode a0 and a1 21, 22 subaddress inputs sa0 23 i 2 c-bus slave address input v ss [2] 24 to 26 ground supply voltage v lcd 27 to 29 lcd supply voltage bp2 and bp0 30, 31 lcd backplane outputs s0 to s79 32 to 111 lcd segment outputs bp0, bp2, bp1, and bp3 112 to 115 lcd backplane outputs s80 to s159 116 to 195 lcd segment outputs bp3 and bp1 196, 197 lcd backplane outputs
PCA85132_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 6 may 2010 6 of 53 nxp semiconductors PCA85132 lcd driver for low multiplex rates 7. functional description the PCA85132 is a versatile peripheral de vice designed to interface between any microprocessor or microcontroller to a wide variet y of lcd segment or dot matrix displays (see figure 3 ). it can directly drive any static or multiplexed lcd containing up to four backplanes and up to 160 segments. the display configurations possible with the PCA85132 depend on the required number of active backplane outputs. a selection of display configurations is given in ta b l e 4 . all of the display configurations given in ta b l e 4 can be implemented in a typical system as shown in figure 4 . fig 3. example of displa ys suitable for PCA85132 table 4. selection of possi ble display configurations number of backplanes icons digits/characters dot matrix/ elements 7-segment 14-segment 4 640 80 40 640 dots (4 160) 3 480 60 30 480 dots (3 160) 2 320 40 20 320 dots (2 160) 1 160 20 10 160 dots (1 160) 7-segment with dot 14-segment with dot and accent 013aaa312 dot matrix
PCA85132_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 6 may 2010 7 of 53 nxp semiconductors PCA85132 lcd driver for low multiplex rates the host microprocessor or microcontroller maintains the 2-line i 2 c-bus communication channel with the PCA85132. biasing voltages for the multiplexed lcd wa veforms are generated internally, removing the need for an external bias generator. the internal oscillator is selected by connecting pin osc to v ss . the only other connections required to complete the system are the power supplies (v dd , v ss ,andv lcd ) and the lcd panel selected for the application. 7.1 power-on reset (por) at power-on the PCA85132 resets to the following starting conditions: ? all backplane and segment outputs are set to v lcd ? the selected drive mode is 1:4 multiplex with 1 ? 3 bias ? blinking is switched off ? input and output bank selectors are reset ? the i 2 c-bus interface is initialized ? the data pointer and the subaddress counter are cleared (set to logic 0) ? the display is disabled ? if internal oscillator is sele cted (pin osc connected to v ss ), then there is no clock signal on pin clk remark: do not transfer data on the i 2 c-bus for at least 1 ms after a power-on to allow the reset action to complete. 7.2 lcd bias generator fractional lcd biasing voltages are obtained from an internal voltage divider of the three series resistors connected between v lcd and v ss . the center resistor is bypassed by switch if the 1 ? 2 bias voltage level for the 1:2 mult iplex configuration is selected. fig 4. typical system configuration host micro- processor/ micro- controller r t r 2c b sda sdaack scl osc 160 segment drives 4 backplanes lcd panel (up to 640 elements) PCA85132 a0 a1 sa0 v dd v ss v ss v dd v lcd 013aaa06 1
PCA85132_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 6 may 2010 8 of 53 nxp semiconductors PCA85132 lcd driver for low multiplex rates 7.3 lcd voltage selector the lcd voltage selector coordinates the mult iplexing of the lcd in accordance with the selected lcd drive configuration. the operation of the voltage selector is controlled by the mode-set command from the command decoder. the biasing configurations that apply to the preferred modes of operatio n, together with the biasing characteristics as functions of v lcd and the resulting discrimina tion ratios (d) are given in ta b l e 5 . a practical value for v lcd is determined by equating v off(rms) with a defined lcd threshold voltage (v th ), typically when the lcd exhibits approximately 10 % contrast. in the static drive mode a suitable choice is v lcd >3v th . multiplex drive modes of 1:3 and 1:4 with 1 ? 2 bias are possible but the discrimination and hence the contrast ratios are smaller. bias is calculated by , where the values for a are a = 1 for 1 ? 2 bias a = 2 for 1 ? 3 bias the rms on-state voltage (v on(rms) ) for the lcd is calculated with equation 1 : (1) where the values for n are n = 1 for static drive mode n = 2 for 1:2 multiplex drive mode n = 3 for 1:3 multiplex drive mode n = 4 for 1:4 multiplex drive mode the rms off-state voltage (v off(rms) ) for the lcd is calculated with equation 2 : (2) discrimination is the ratio of v on(rms) to v off(rms) and is determined from equation 3 : (3) table 5. biasing characteristics lcd drive mode number of: lcd bias configuration backplanes levels static 1 2 static 0 1 1:2 multiplex 2 3 1 ? 2 0.354 0.791 2.236 1:2 multiplex 2 4 1 ? 3 0.333 0.745 2.236 1:3 multiplex 3 4 1 ? 3 0.333 0.638 1.915 1:4 multiplex 4 4 1 ? 3 0.333 0.577 1.732 v off rms () v lcd ------------------------ - v on rms () v lcd ----------------------- - d v on rms () v off rms () ------------------------ - = 1 1a + ------------ - v on rms () a 2 2a n ++ n 1a + () 2 ----------------------------- - v lcd = v off rms () a 2 2a ? n + n 1a + () 2 ----------------------------- - v lcd = d v on rms () v off rms () ---------------------- - a1 + () 2 n 1 ? () + a1 ? () 2 n 1 ? () + ------------------------------------------- - ==
PCA85132_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 6 may 2010 9 of 53 nxp semiconductors PCA85132 lcd driver for low multiplex rates using equation 3 , the discrimination for an lcd drive mode of 1:3 multiplex with 1 ? 2 bias is and the discrimination for an lcd drive mode of 1:4 multiplex with 1 ? 2 bias is . the advantage of these lcd drive modes is a reduction of the lcd full scale voltage v lcd as follows: ? 1:3 multiplex ( 1 ? 2 bias): ? 1:4 multiplex ( 1 ? 2 bias): these compare with when 1 ? 3 bias is used. it should be noted that v lcd is sometimes referred as the lcd operating voltage. 3 1.732 = 21 3 ---------- 1.528 = v lcd 6v off rms () 2.449v off rms () == v lcd 43 () 3 --------------------- - 2.309v off rms () == v lcd 3v off rms () =
PCA85132_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 6 may 2010 10 of 53 nxp semiconductors PCA85132 lcd driver for low multiplex rates 7.4 lcd drive mode waveforms 7.4.1 static drive mode the static lcd drive mode is used when a single backplane is provided in the lcd. backplane and segment drive waveforms for this mode are shown in figure 5 . v state1 (t) = v sn (t) ? v bp0 (t). v on(rms) = v lcd . v state2 (t) = v (sn+1) (t) ? v bp0 (t). v off(rms) = 0 v. fig 5. static driv e mode waveforms 013aaa207 v ss v lcd v ss v lcd v ss v lcd v lcd ? v lcd ? v lcd v lcd state 1 0 v bp0 sn sn+1 state 2 0 v (a) waveforms at driver. (b) resultant waveforms at lcd segment. lcd segments state 1 (on) state 2 (off) t fr
PCA85132_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 6 may 2010 11 of 53 nxp semiconductors PCA85132 lcd driver for low multiplex rates 7.4.2 1:2 multiplex drive mode when two backplanes are provided in the lcd, the 1:2 multiplex mode applies. the PCA85132 allows the use of 1 ? 2 bias or 1 ? 3 bias in this mode as shown in figure 6 and figure 7 . v state1 (t) = v sn (t) ? v bp0 (t). v on(rms) = 0.791v lcd . v state2 (t) = v sn (t) ? v bp1 (t). v off(rms) = 0.354v lcd . fig 6. waveforms for the 1:2 multiplex drive mode with 1 ? 2 bias 013aaa208 state 1 bp0 (a) waveforms at driver. (b) resultant waveforms at lcd segment. lcd segments state 2 bp1 state 2 state 1 v ss v lcd v lcd /2 v ss v ss v lcd v lcd v ss v lcd v lcd v lcd 0 v 0 v v lcd /2 v lcd /2 v lcd /2 ? v lcd ? v lcd ? v lcd /2 ? v lcd /2 sn sn+1 t fr
PCA85132_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 6 may 2010 12 of 53 nxp semiconductors PCA85132 lcd driver for low multiplex rates v state1 (t) = v sn (t) ? v bp0 (t). v on(rms) = 0.745v lcd . v state2 (t) = v sn (t) ? v bp1 (t). v off(rms) = 0.333v lcd . fig 7. waveforms for the 1:2 multiplex drive mode with 1 ? 3 bias 013aaa209 state 1 bp0 (a) waveforms at driver. (b) resultant waveforms at lcd segment. lcd segments state 2 bp1 state 1 state 2 v ss v lcd 2v lcd /3 v lcd /3 v ss v lcd 2v lcd /3 v lcd /3 v ss v lcd 2v lcd /3 v lcd /3 0 v v lcd 2v lcd /3 ? 2v lcd /3 v lcd /3 ? v lcd /3 ? v lcd ? v lcd 0 v v lcd 2v lcd /3 ? 2v lcd /3 v lcd /3 ? v lcd /3 s n s n+1 t fr v ss v lcd 2v lcd /3 v lcd /3
PCA85132_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 6 may 2010 13 of 53 nxp semiconductors PCA85132 lcd driver for low multiplex rates 7.4.3 1:3 multiplex drive mode when three backplanes are provided in the l cd, the 1:3 multiplex dr ive mode applies as shown in figure 8 . v state1 (t) = v sn (t) ? v bp0 (t). v on(rms) = 0.638v lcd . v state2 (t) = v sn (t) ? v bp1 (t). v off(rms) = 0.333v lcd . fig 8. waveforms for the 1:3 multiplex drive mode with 1 ? 3 bias 013aaa210 state 1 bp0 (b) resultant waveforms at lcd segment. lcd segments state 2 bp1 state 1 state 2 (a) waveforms at driver. bp2 sn sn+1 sn+2 t fr v ss v lcd 2v lcd /3 v lcd /3 v ss v lcd 2v lcd /3 v lcd /3 v ss v lcd 2v lcd /3 v lcd /3 v ss v lcd 2v lcd /3 v lcd /3 v ss v lcd 2v lcd /3 v lcd /3 0 v v lcd 2v lcd /3 ? 2v lcd /3 v lcd /3 ? v lcd /3 ? v lcd 0 v v lcd 2v lcd /3 ? 2v lcd /3 v lcd /3 ? v lcd /3 ? v lcd v ss v lcd 2v lcd /3 v lcd /3
PCA85132_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 6 may 2010 14 of 53 nxp semiconductors PCA85132 lcd driver for low multiplex rates 7.4.4 1:4 multiplex drive mode when four backplanes are provided in the lcd, the 1:4 multiplex drive mode applies as shown in figure 9 . v state1 (t) = v sn (t) ? v bp0 (t). v on(rms) = 0.577v lcd . v state2 (t) = v sn (t) ? v bp1 (t). v off(rms) = 0.333v lcd . fig 9. waveforms for the 1:4 multiplex drive mode with 1 ? 3 bias 013aaa211 state 1 bp0 (b) resultant waveforms at lcd segment. lcd segments state 2 bp1 state 1 state 2 bp2 (a) waveforms at driver. bp3 sn sn+1 sn+2 sn+3 t fr v ss v lcd 2v lcd /3 v lcd /3 v ss v lcd 2v lcd /3 v lcd /3 v ss v lcd 2v lcd /3 v lcd /3 v ss v lcd 2v lcd /3 v lcd /3 v ss v lcd 2v lcd /3 v lcd /3 v ss v lcd 2v lcd /3 v lcd /3 v ss v lcd 2v lcd /3 v lcd /3 0 v v lcd 2v lcd /3 ? 2v lcd /3 v lcd /3 ? v lcd /3 ? v lcd 0 v v lcd 2v lcd /3 ? 2v lcd /3 v lcd /3 ? v lcd /3 ? v lcd v ss v lcd 2v lcd /3 v lcd /3
PCA85132_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 6 may 2010 15 of 53 nxp semiconductors PCA85132 lcd driver for low multiplex rates 7.5 oscillator the internal logic and the lcd drive signals of the PCA85132 are timed by a frequency f clk which either is derived from the built-in oscillator frequency f osc : (4) or equals an external clock frequency f clk(ext) : (5) remark: a clock signal must always be supplied to the device; removing the clock may freeze the lcd in a dc state, which is not suitable for the liquid crystal. 7.5.1 internal clock the internal oscillator is enab led by connecting pin osc to v ss . in this case the output from pin clk provides the clock signal fo r cascaded PCA85132 in the system. however, the clock signal is only available at pin clk, if the display is enabled. the display is enabled using the display enable bit (see ta b l e 1 0 ). the output clock frequency is like specified in ta b l e 1 9 with parameter f clk . 7.5.2 external clock connecting pin osc to v dd enables an external clock source. pin clk then becomes the external clock input. 7.6 timing and frame frequency the timing of the PCA85132 organizes the intern al data flow of the device. this includes the transfer of display data from the display ram to the display segment outputs. in cascaded applications, the sy nchronization signal (sync ) maintains the correct timing relationship between the PCA85132 in the system. when the internal clock is used, the clock frequency can be programmed by software such that the frame frequency can be chosen in steps of 5 hz in the range of 60 hz to 90 hz (see ta b l e 1 6 ). the internal oscillator is calibrated within an accuracy of 3.9 % (at v dd =5.0v; t amb =30 c). the timing also generates the lcd frame freq uency derived from an integer division of f clk (see table 16 ). 7.7 display register the display register holds the display data while the corresponding multiplex signals are generated. f clk f osc 64 -------- = f clk f clk ext () =
PCA85132_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 6 may 2010 16 of 53 nxp semiconductors PCA85132 lcd driver for low multiplex rates 7.8 segment outputs the lcd drive section includes 160 segment outputs (s0 to s159) which must be connected directly to the lcd. the segment output signals are generated in accordance with the multiplexed backplane signals and with data resident in the display register. when less than 160 segment outputs are required the unused segment outputs must be left open-circuit. 7.9 backplane outputs the lcd drive section includes four backplane outputs: bp0 to bp3. the backplane output signals are generated in accord ance with the selected lcd drive mode. ? in the 1:4 multiplex drive mode bp0 to bp3 must be connected directly to the lcd. if less than four backplane outputs are required the unused outputs can be left open-circuit. ? in 1:3 multiplex drive mode bp3 carries the same signal as bp1, therefore these two adjacent outputs can be tied togethe r to give enhanced drive capabilities. ? in 1:2 multiplex drive mode bp0 and bp2, bp1 and bp3 respectively carry the same signals and may also be paired to increase the drive capabilities. ? in static drive mode the same signal is ca rried by all four backplane outputs and they can be connected in parallel for very high drive requirements. the pins for the four backplanes bp0 to bp3 are available on both pin bars of the chip. in applications it is poss ible to use either the pins for the backplanes ? on the top pin bar ? on the bottom pin bar ? or both of them to increase the driving strength of the device. when using all backplanes available they may be connected to the respective sibling (bp0 on the top pin bar with bp0 on the bottom pin bar and so on). 7.10 display ram the display ram is a static 160 4 bit ram which stores lcd data. there is a one-to-one correspondence between ? the bits in the ram bitmap and the lcd elements ? the ram columns and the segment outputs ? the ram rows and the backplane outputs. a logic 1 in the ram bitmap indicates the on-state of the corresponding lcd element; similarly, a logic 0 indicates the off-state. the display ram bit map, figure 10 , shows the rows 0 to 3 which correspond with the backplane outputs bp0 to bp3, and the co lumns 0 to 159 which correspond with the segment outputs s0 to s159. in multiplexed lcd applications the segment data of the first, second, third, and fourth row of th e display ram are time-multiplexed with bp0, bp1, bp2, and bp3 respectively.
PCA85132_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 6 may 2010 17 of 53 nxp semiconductors PCA85132 lcd driver for low multiplex rates when display data is transmitted to the pc a85132 the received display bytes are stored in the display ram in accordance with the se lected lcd drive mode. the data is stored as it arrives and does not wait for the ackno wledge cycle as with the commands. depending on the current multiplex drive mode, data is stored singularly, in pairs, triples, or quadruples. to illustrate the filling order, an example of a 7-segment numeric display showing all drive modes is given in figure 11 ; the ram filling organization depicted applies equally to other lcd types. the following applies to figure 11 : ? in static drive mode the eight transmitted data bits are placed in row 0 as one byte. ? in 1:2 multiplex drive mode the eight transmitted data bits are placed in pairs into row 0 and 1 as two successive 4-bit ram words. ? in 1:3 multiplex drive mode the eight bits are placed in triples into row 0, 1, and 2 as three successive 3-bit ram words, with bit 3 of the third address left unchanged. it is not recommended to use this bit in a displa y because of the difficult addressing. this last bit may, if necessary, be controlled by an additional transfer to this address but care should be taken to avoid overwriting adjacent data because always full bytes are transmitted. ? in 1:4 multiplex drive mode, the eight transm itted data bits are placed in quadruples into row 0, 1, 2, and 3 as two successive 4-bit ram words. the display ram bitmap shows the direct relationship between the display ram addresses and the segment outputs; and between the bits in a ram word and the backplane outputs. fig 10. display ram bitmap 0 0 1 2 3 1234 155156157158159 display ram addresses/segment outputs (s) display ram rows/ backplane outputs (bp) 013aaa2 20 columns rows
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx PCA85132_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 6 may 2010 18 of 53 nxp semiconductors PCA85132 lcd driver for low multiplex rates x = data bit unchanged fig 11. relationships between lcd layout, drive mode, display ram filling order, and display data transmitted over the i 2 c-bus 001aaj64 6 acbdpf egd msb lsb bdpcadgfe msb lsb abfgecddp msb lsb cba f geddp msb lsb drive mode static 1:2 multiplex 1:3 multiplex 1:4 multiplex lcd segments lcd backplanes display ram filling order transmitted display byte bp0 bp0 bp1 bp0 bp1 bp2 bp1 bp2 bp3 bp0 n c x x x 0 1 2 3 b x x x a x x x f x x x g x x x e x x x d x x x dp x x x n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7 rows display ram rows/backplane outputs (bp) byte1 columns display ram address/segment outputs (s) n a b x x 0 1 2 3 f g x x e c x x d dp x x n + 1 n + 2 n + 3 byte1 byte2 rows display ram rows/backplane outputs (bp) columns display ram address/segment outputs (s) n b dp c x 0 1 2 3 a d g x f e x x n + 1 n + 2 byte1 byte2 byte3 rows display ram rows/backplane outputs (bp) columns display ram address/segment outputs (s) n + 1 n a c b dp 0 1 2 3 f e g d byte1 byte2 byte3 byte4 byte5 rows display ram rows/backplane outputs (bp) columns display ram address/segment outputs (s) s n+2 s n+3 s n+1 s n dp a f b g e c d s n+2 s n+1 s n+7 s n s n+3 s n+5 s n+6 s n+4 dp a f b g e c d s n s n+1 s n+2 dp a f b g e c d s n+1 s n dp a f b g e c d
PCA85132_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 6 may 2010 19 of 53 nxp semiconductors PCA85132 lcd driver for low multiplex rates 7.11 data pointer the addressing mechanism for the display ram is realized using the data pointer. this allows the loading of an individual display data byte, or a series of display data bytes, into any location of the display ram. the sequen ce commences with the initialization of the data pointer by the load-data-pointer command (see ta b l e 8 ). following this command, an arriving data byte is stored at the display ram address indicated by the data pointer. the filling order is shown in figure 11 . after each byte is stored, the content of the da ta pointer is automatically incremented by a value dependent on the selected lcd drive mode: ? in static drive mode by eight ? in 1:2 multiplex drive mode by four ? in 1:3 multiplex drive mode by three ? in 1:4 multiplex drive mode by two if an i 2 c-bus data access is terminated early then the state of the data pointer is unknown. the data pointer should be re-written prior to further ram accesses. 7.12 subaddress counter the storage of display data is conditioned by the content of the subaddress counter. storage is allowed only when the content of the subaddress counter matches with the hardware subaddress applied to a0 and a1. the subaddress counter value is defined by the device-select command (see ta b l e 1 3 ). if the content of the subaddress counter and the hardware subaddress do not match then data storage is inhibited but the data pointer is incremented as if data storage had take n place. the subaddress counter is also incremented when the data pointer overflows. the storage arrangements described lead to ex tremely efficient data loading in cascaded applications. when a series of display byte s are sent to the display ram, automatic wrap-over to the next PCA85132 occurs when the last ram address is exceeded. subaddressing across device boundaries is successful even if the change to the next device in the cascade occurs within a tr ansmitted character (such as during the 27 th display data byte transmit ted in 1:3 multiplex mode). the hardware subaddress must not be change d whilst the device is being accessed on the i 2 c-bus interface. 7.13 output bank selector the output bank selector (see ta b l e 1 4 ) selects one of the four rows per display ram address for transfer to the display register. the actual row selected depends on the particular lcd drive mode in operation and on the instant in the multiplex sequence. ? in 1:4 multiplex mode, all ram addresses of row 0 are selected, these are followed by the contents of row 1, row 2, and then row 3 ? in 1:3 multiplex mode, rows 0, 1, and 2 are selected sequentially ? in 1:2 multiplex mode, rows 0 and 1 are selected ? in static mode, row 0 is selected
PCA85132_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 6 may 2010 20 of 53 nxp semiconductors PCA85132 lcd driver for low multiplex rates the PCA85132 includes a ram bank switching feature in the static and 1:2 multiplex drive modes. in the static drive mode, the bank-select command may request the contents of row 2 to be selected for display instead of the contents of row 0. in the 1:2 multiplex mode, the contents of rows 2 and 3 may be selected instead of rows 0 and 1. this gives the provision for preparing display information in an alternative bank and to be able to switch to it once it is assembled. 7.14 input bank selector the input bank selector loads display data into the display ram in accordance with the selected lcd drive configuration. display data can be loaded in row 2 in static drive mode or in rows 2 and 3 in 1:2 multiplex drive mode by using the bank-select command (see ta b l e 1 4 ). the input bank selector functions inde pendently to the output bank selector. 7.15 blinker the display blinking capabilitie s of the PCA85132 are very versatile. the whole display can blink at frequencie s selected by the blink-select command (see table 15 ). the blink frequencies are fractions of the clock freque ncy. the ratios between the clock and blink frequencies depend on the blink mode in which the device is operating (see ta b l e 6 ). an additional feature is for an arbitrary select ion of lcd elements to blink. this applies to the static and 1:2 multiplex drive modes and can be implemented without any communication overheads. by means of the output bank selector, the displayed ram banks are exchanged with alternate ram banks at the blink frequency. this mode can also be specified by the blink-select command (see ta b l e 1 5 ). in the 1:3 and 1:4 multiplex modes, where no alternate ram bank is available, groups of lcd elements can blink selectively by chang ing the display ram data at fixed time intervals. the entire display can blink at a frequency other than the nominal blinking frequency. this can be effectively performed by resetting and setting the display enable bit e at the required rate using the mode-set command (see ta b l e 1 0 ). 7.16 characteristics of the i 2 c-bus the i 2 c-bus is for bidirectional, two-line communication between different ics or modules. the two lines are a serial data line (sda) and a serial clock line (scl). both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. data transfer may be initiated only when the bus is not busy. table 6. blink frequencies assuming that f clk = 1.800 khz. blink mode operating mode ratio blink frequency off - blinking off 1~2.34 hz 2~1.17 hz 3~0.59 hz f blink f clk 768 -------- - = f blink f clk 1536 ----------- - = f blink f clk 3072 ----------- - =
PCA85132_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 6 may 2010 21 of 53 nxp semiconductors PCA85132 lcd driver for low multiplex rates by connecting pin sdaack to pin sda on the PCA85132, the sda line becomes fully i 2 c-bus compatible. in cog app lications where the track resistance from the sdaack pin to the system sda line can be significant, possibly a voltage divider is generated by the bus pull-up resistor and the indium tin oxide (ito) track resistance. as a consequence it may be possible that the ac knowledge generated by the PCA85132 can?t be interpreted as logic 0 by the master. in cog applications where the acknowledge cycle is required, it is therefore necessary to mi nimize the track resistance from the sdaack pin to the system sda line to guarantee a valid low level. by separating the acknowledge output from the serial data line (having the sdaack open circuit) design efforts to generate a valid acknowledge level can be avoided. however, in that case the i 2 c-bus master has to be set up in such a way that it ignores the acknowledge cycle. 2 the following definition assumes sda and sdaac k are connected and refers to the pair as sda. 7.16.1 bit transfer one data bit is transferred during each clock pulse. the data on the sda line must remain stable during the high period of the clock pulse as changes in the data line at this time will be interpreted as a control signal (see figure 12 ). 7.16.1.1 start and stop conditions both data and clock lines remain high when the bus is not busy. a high-to-low change of the data line, while the clock is high is defined as the start condition (s). a low-to-high change of the data line while th e clock is high is defined as the stop condition (p). the start and st op conditions are shown in figure 13 . 2. for further information, please consider the nxp application note: ref. 1 ? an10170 ? . fig 12. bit transfer mba60 7 data line stable; data valid change of data allowed sda scl fig 13. definition of start and stop conditions mbc622 sda scl p stop condition sda scl s start condition
PCA85132_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 6 may 2010 22 of 53 nxp semiconductors PCA85132 lcd driver for low multiplex rates 7.16.2 system configuration a device generating a message is a transmit ter; a device receiving a message is the receiver. the device that controls the message is the master and the devices which are controlled by the master are the slaves. the system configuration is shown in figure 14 . 7.16.3 acknowledge the number of data bytes transferred between the start and stop conditions from transmitter to receiver is unlim ited. each byte of eight bits is followed by an acknowledge cycle. ? a slave receiver which is addressed must generate an acknowledge after the reception of each byte. ? also a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. ? the device that acknowledges must pull-down the sda line during the acknowledge clock pulse, so that the sda line is st able low during the high period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). ? a master receiver must signal an end of da ta to the transmitter by not generating an acknowledge on the last byte that has been cl ocked out of the slave. in this event the transmitter must leave the data line high to enable the master to generate a stop condition. acknowledgement on the i 2 c-bus is shown in figure 15 . fig 14. system configuration mga807 sda scl master transmitter/ receiver master transmitter slave transmitter/ receiver slave receiver master transmitter/ receiver fig 15. acknowledgement on the i 2 c-bus mbc6 02 s start condition 9 8 2 1 clock pulse for acknowledgement not acknowledge acknowledge data output by transmitter data output by receiver scl from master
PCA85132_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 6 may 2010 23 of 53 nxp semiconductors PCA85132 lcd driver for low multiplex rates 7.16.4 i 2 c-bus controller the PCA85132 acts as an i 2 c-bus slave receiver. it does not initiate i 2 c-bus transfers or transmit data to an i 2 c-bus master receiver. the only data output from the PCA85132 are the acknowledge signals from the selected de vices. device selection depends on the i 2 c-bus slave address, on the transferred command data, and on the hardware subaddress. in single device applications, the hardware s ubaddress inputs a0 and a1 are normally tied to v ss which defines the hardware subaddress 0. in multiple device applications a0 and a1 are tied to v ss or v dd in accordance with a binary coding scheme such that no two devices with a common i 2 c-bus slave address have the same hardware subaddress. 7.16.5 input filters to enhance noise immunity in electrically ad verse environments, rc low-pass filters are provided on the sda and scl lines. 7.16.6 i 2 c-bus protocol two i 2 c-bus slave addresses (0111 000 and 0111 001) are reserved for the PCA85132.the entire i 2 c-bus slave address byte is shown in ta b l e 7 . the PCA85132 is a write-only device and will not respond to a read access, therefore bit 0 should always be logic 0. bit 1 of the slav e address byte, that a PCA85132 will respond to, is defined by the level tied to its sa0 input (v ss for logic 0 and v dd for logic 1). having two reserved slave addresses allows the following on the same i 2 c-bus: ? up to 8 PCA85132 on the same i 2 c-bus for very large lcd applications ? the use of two types of lcd multiplex on the same i 2 c-bus the i 2 c-bus protocol is shown in figure 16 . the sequence is initiated with a start condition (s) from the i 2 c-bus master which is followed by one of two possible PCA85132 slave addresses available. all PCA85132 with the corresponding sa0 level acknowledge in parallel to the slave address, but all PCA85132 with the alternative sa0 level ignore the whole i 2 c-bus transfer. table 7. i 2 c slave address byte slave address bit 7 6 5 4 3 2 1 0 msb lsb 011100sa0r/w
PCA85132_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 6 may 2010 24 of 53 nxp semiconductors PCA85132 lcd driver for low multiplex rates after acknowledgement, a contro l byte follows which defines if the next byte is ram or command information. the control byte also de fines if the next byte is a control byte or further ram or command data. in this way it is possible to configure the device and then fill t he display ram with little overhead. the command bytes and control bytes are also acknowledged by all addressed PCA85132 connected to the bus. the display bytes are stored in the display ram at the address specified by the data pointer and the subaddress counter; see section 7.11 and section 7.12 . fig 16. i 2 c-bus protocol examples a) transmit two bytes of ram data mgl75 2 s a 0 s 01110 0 0 control byte slave address ram/command byte ram data m s b l s b a a p r/w = 0 s a 0 s 01110 0 01 0 a a a p ram data a b) transmit two command bytes command s a 0 s 01110 0 10 0 a a a p command a a c) transmit one command byte and two ram date bytes command s a 0 s 01110 0 10 00 01 0 a a a p ram data a ram data a a c o r s table 8. control byte description bit symbol value description 7co continue bit 0 last control byte 1 control bytes continue 6rs register selection 0 command register 1 data register 5 to 0 - not relevant fig 17. control byte format mgl753 not relevant co 76 543210 rs msb lsb
PCA85132_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 6 may 2010 25 of 53 nxp semiconductors PCA85132 lcd driver for low multiplex rates the acknowledgement after each byte is made only by the (a0 and a1) addressed PCA85132. after the last (display) byte, the i 2 c-bus master issues a stop condition (p). alternatively a start may be asserted to restart an i 2 c-bus access. 7.17 command decoder the command decoder identifies command bytes that arrive on the i 2 c-bus. the commands available to the PCA85132 are defined in table 9 . [1] power-on and reset value. [2] the possibility to disable the display allows implementat ion of blinking under exter nal control; the enable bit determines also whether the internal clock signal is available at the clk pin (see section 7.5.1 ). [1] power-on and reset value. table 9. definition of PCA85132 commands command operation code reference bit 7 6 5 4 3 2 1 0 mode-set 1 1 0 0 e b m[1:0] table 10 load-data-pointer-msb 0 0 0 0 p[7:4] table 11 load-data-pointer-lsb 0 1 0 0 p[3:0] table 12 device-select 1 1 1 0 0 0 a[1:0] table 13 bank-select 1 1 1 1 1 0 i o table 14 blink-select 1 1 1 1 0 ab bf[1:0] table 15 frequency-prescaler 1 1 1 0 1 f[2:0] table 16 table 10. mode-set command bit description bit symbol value description 7 to 4 - 1100 fixed value 3e display status 0 [1] disabled (blank) [2] 1 enabled 2b lcd bias configuration 0 [1] 1 ? 3 bias 1 1 ? 2 bias 1 to 0 m[1:0] lcd drive mode selection 01 static; bp0 10 1:2 multiplex; bp0, bp1 11 1:3 multiplex; bp0, bp1, bp2 00 [1] 1:4 multiplex; bp0, bp1, bp2, bp3 table 11. load-data-pointer-msb command bit description bit symbol value description 7 to 4 - 0000 fixed value 3 to 0 p[7:4] 0000 [1] to 1001 p7 to p4 defines the first 4 (most significant) bits of the data pointer that indicates one of the 160 display ram addresses
PCA85132_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 6 may 2010 26 of 53 nxp semiconductors PCA85132 lcd driver for low multiplex rates [1] power-on and reset value. [1] power-on and reset value. [1] the bank-select command has no effect in 1:3 and 1:4 multiplex drive modes. [2] power-on and reset value. [1] power-on and reset value. [2] normal blinking is assumed when the lcd multiplex drive modes 1:3 or 1:4 are selected. [3] alternate ram bank blinking does not apply in 1:3 and 1:4 multiplex drive modes. table 12. load-data-pointer-lsb command bit description bit symbol value description 7 to 4 - 0100 fixed value 3 to 0 p[3:0] 0000 [1] to 1111 p3 to p0 defines the last 4 (l east significant) bits of the data pointer that indicate s one of the 160 display ram addresses table 13. device-select command bit description bit symbol value description 7 to 2 - 111000 fixed value 1 to 0 a[1:0] 00 [1] to 11 two bits of immediate data, bits a0 to a1, are transferred to the subaddress counter to define one of four hardware subaddresses (see ta b l e 2 0 ) table 14. bank-select command bit description bit symbol value description static 1:2 multiplex [1] 7 to 2 - 111110 fixed value 1i input bank selection ; storage of arriving display data 0 [2] ram bit 0 ram bits 0 and 1 1 ram bit 2 ram bits 2 and 3 0o output bank selection ; retrieval of lcd display data 0 [2] ram bit 0 ram bits 0 and 1 1 ram bit 2 ram bits 2 and 3 table 15. blink-select command bit description bit symbol value description 7 to 3 - 11110 fixed value 2ab blink mode selection 0 [1] normal blinking [2] 1 alternate ram bank blinking [3] 1 to 0 bf[1:0] blink frequency selection 00 [1] off 01 1 10 2 11 3
PCA85132_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 6 may 2010 27 of 53 nxp semiconductors PCA85132 lcd driver for low multiplex rates [1] nominal frame frequency calculated for an internal operating frequency of 1.800 khz. [2] power-on and reset value. 7.18 display controller the display controller executes the command s identified by the command decoder. it contains the status registers of the pca8 5132 and co-ordinates their effects. the controller is also responsible for loading display data into the display ram as required by the filling order. table 16. frame-frequency prescaler bit symbol value description nominal frame frequency [1] equation 7 to 4 - 11101 fixed value 3 to 0 f[2:0] defines the division factor for the frame frequency f fr 000 60 hz 001 65 hz 010 70 hz 011 [2] 75 hz 100 80 hz 101 85 hz 110 90 hz 111 75 hz f fr 64 80 ----- - f clk 24 ------- - = f fr 64 74 ----- - f clk 24 ------- - = f fr 64 68 ----- - f clk 24 ------- - = f fr f clk 24 ------- - = f fr 64 60 ----- - f clk 24 ------- - = f fr 64 56 ----- - f clk 24 ------- - = f fr 64 53 ----- - f clk 24 ------- - = f fr f clk 24 ------- - =
PCA85132_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 6 may 2010 28 of 53 nxp semiconductors PCA85132 lcd driver for low multiplex rates 8. internal circuitry fig 18. device protection diagram v dd v dd v ss v ss 013aaa221 v ss sdaack, scl, sda, t3, v lcd sync, t1, t2, a0, a1, osc, clk, sa0 v lcd v ss s0 to s159, bp0 to bp3
PCA85132_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 6 may 2010 29 of 53 nxp semiconductors PCA85132 lcd driver for low multiplex rates 9. limiting values [1] stresses above these values listed ma y cause permanent damage to the device. [2] pass level; human body model (hbm) according to ref. 5 ? jesd22-a114 ? . [3] pass level; machine model (mm), according to ref. 6 ? jesd22-a115 ? . [4] pass level; latch-up testing, according to ref. 7 ? jesd78 ? at maximum ambient temperature (t amb(max) =95 c). [5] according to the nxp store and transport requirements (see ref. 9 ? nx3-00092 ? ) the devices have to be stored at a temperature of +8 c to +45 c and a humidity of 25 % to 75 %. for long term storage products deviant conditions are described in that document. caution static voltages across the liquid crystal display can build up when the lcd supply voltage (v lcd ) is on while the ic supply voltage (v dd ) is off, or vice versa. this may cause unwanted display artifacts. to av oid such artifacts, v lcd and v dd must be applied or removed together. table 17. limiting values in accordance with the absolute maximum rating system (iec 60134). [1] symbol parameter conditions min max unit v dd supply voltage ? 0.5 +6.5 v i dd supply current ? 50 +50 ma v lcd lcd supply voltage ? 0.5 +9.0 v i dd(lcd) lcd supply current ? 50 +50 ma v i input voltage on pins clk, sync , sa0, osc, sda, scl, a0, a1, t1, t2, and t3 ? 0.5 +6.5 v i i input current ? 10 +10 ma v o output voltage on pins s0 to s159 and bp0 to bp3 ? 0.5 +9.0 v on pins sdaack, clk, sync ? 0.5 +6.5 v i o output current ? 10 +10 ma i ss ground supply current ? 50 +50 ma p tot total power dissipation - 400 mw p/out power dissipation per output - 100 mw v esd electrostatic discharge voltage hbm [2] - 4500 v mm [3] - 250 v i lu latch-up current [4] - 200 ma t stg storage temperature [5] ? 65 +150 c t oper operating temperature ? 40 +95 c
PCA85132_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 6 may 2010 30 of 53 nxp semiconductors PCA85132 lcd driver for low multiplex rates 10. static characteristics table 18. static characteristics v dd = 1.8 v to 5.5 v; v ss = 0 v; v lcd = 1.8 v to 8.0 v; t amb = ? 40 c to +95 c; unless otherwise specified. symbol parameter conditions min typ max unit supplies v dd supply voltage 1.8 - 5.5 v v lcd lcd supply voltage 1.8 - 8.0 v i dd supply current f clk(ext) = 1.800 khz [1] [2] [3] --20 a with internal oscillator running [1] [3] --60 a i dd(lcd) lcd supply current f clk(ext) = 1.800 khz [1] [2] [4] --70 a with internal oscillator running [1] [4] --70 a logic v i input voltage on pins sda and scl ? 0.5 - +5.5 v all other input pins ? 0.5 - v dd +0.5 v v ih high-level input voltage on pins clk, sync , osc, a0, a1, sa0, scl, and sda 0.7v dd --v v il low-level input voltage on pins clk, sync , osc, a0, a1, sa0, scl, and sda --0.3v dd v v o output voltage on pins clk and sync ? 0.5 - v dd +0.5 v on pin sdaack ? 0.5 - +5.5 v v oh high-level output voltage on pin sync , clk 0.8v dd -v dd v v ol low-level output voltage on pin sync , clk, sdaack v ss -0.2v dd v i oh high-level output current output source current; v oh =4.6v; v dd = 5 v; on pin clk 1.5 - - ma i ol low-level output current output sink current; on pins clk and sync v ol =0.4v; v dd =5v 1.5 - - ma on pin sdaack v dd 2 v; v ol =0.2v dd 3- - ma 2 v < v dd < 3 v; v ol =0.4v 3 - - ma v dd 3v; v ol =0.4v 6 - - ma v por power-on reset voltage 1.0 1.3 1.6 v i l leakage current v i =v dd or v ss ; on pin osc, clk, a0, a1, sa0, sda, and scl ? 1- +1 a
PCA85132_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 6 may 2010 31 of 53 nxp semiconductors PCA85132 lcd driver for low multiplex rates [1] lcd outputs are open-circuit; inputs at v ss or v dd ; i 2 c-bus inactive; v lcd = 8.0 v, v dd = 5.0 v and ram written with all logic 1. [2] external clock with 50 % duty factor. [3] for typical values, see figure 19 [4] for typical values, see figure 20 [5] variation between any 2 backplanes on a given voltage level; static measured. [6] variation between any 2 segments on a gi ven voltage level; static measured. lcd outputs v o output voltage variation on pins bp0 to bp3 and s0 to s159 [5] [6] ? 30 - +30 mv r o output resistance v lcd = 5 v on pins bp0 to bp3 - 1.5 5 k on pins s0 to s159 - 2.0 5 k table 18. static characteristics ?continued v dd = 1.8 v to 5.5 v; v ss = 0 v; v lcd = 1.8 v to 8.0 v; t amb = ? 40 c to +95 c; unless otherwise specified. symbol parameter conditions min typ max unit t amb =30 c; 1:4 multiplex; v lcd = 8 v; all ram written with logic 1; no display connected. fig 19. i dd with respect to v dd v dd (v) 1 6 5 34 2 001aal014 12 4 8 16 20 i dd ( a) 0 i dd external i dd internal
PCA85132_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 6 may 2010 32 of 53 nxp semiconductors PCA85132 lcd driver for low multiplex rates t amb =30 c; 1:4 multiplex; all ram written with logic 1; no display connected; external clock with f clk = 1.800 khz or f clk(ext) = 1.800 khz. fig 20. i dd(lcd) with respect to v lcd v lcd (v) 1 9 57 3 001aal111 20 10 30 40 i dd(lcd) ( a) 0
PCA85132_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 6 may 2010 33 of 53 nxp semiconductors PCA85132 lcd driver for low multiplex rates 11. dynamic characteristics [1] typical output duty factor: 50 % measured at the clk output pin. [2] for the respective frame frequency f fr see table 16 . [3] for the characteristics of v dd at a fixed temperature or of the temperature at a fixed v dd , see figure 21 and figure 22 . [4] for f clk(ext) > 4 khz it is recommended to use an ex ternal pull-up resistor between pin sync and pin v dd . the value of the resistor should be between 100 k and 1 m . [5] all timing values are valid within the operating supply voltage and ambient temperature range and are referenced to v il and v ih with an input voltage swing of v ss to v dd . table 19. dynamic characteristics v dd = 1.8 v to 5.5 v; v ss = 0 v; v lcd = 1.8 v to 8.0 v; t amb = ? 40 c to +95 c; unless otherwise specified. symbol parameter conditions min typ max unit f clk clock frequency on pin clk; v dd =5v 0.5 v [1] [2] [3] 1600 1800 2060 hz f clk(ext) external clock frequency [4] 700 - 5000 hz t clk(h) high-level clock time external clock source used 100 - - s t clk(l) low-level clock time external clock source used 100 - - s f fr frame frequency variation v dd =5v 0.5 v f fr = 75 hz; t amb =30 c ? 3.9 - +3.9 % f fr = 70.3 hz; t amb =95 c ? 5.2 - +5.2 % f fr = 80 hz; t amb = ? 40 c ? 6.3 - +7.3 % t pd(sync_n) sync propagation delay - 30 - ns t sync_nl sync low time 100 - - s t pd(drv) driver propagation delay v lcd = 5 v - 10 - s timing characteristics: i 2 c-bus [5] f scl scl clock frequency - - 400 khz t buf bus free time between a stop and start condition 1.3 - - s t hd;sta hold time (repeated) start condition 0.6 - - s t su;sta set-up time for a repeated start condition 0.6 - - s t vd;ack data valid acknowledge time - - 0.9 s t low low period of the scl clock 1.3 - - s t high high period of the scl clock 0.6 - - s t f fall time of both sda and scl signals - - 0.3 s t r rise time of both sda and scl signals - - 0.3 s c b capacitive load for each bus line - - 400 pf t su;dat data set-up time 200 - - ns t hd;dat data hold time 0 - - ns t su;sto set-up time for stop condition 0.6 - - s t sp pulse width of spikes that must be suppressed by the input filter --50ns
PCA85132_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 6 may 2010 34 of 53 nxp semiconductors PCA85132 lcd driver for low multiplex rates t amb = 30 c. fig 21. typical clock frequency (f clk ) with respect to voltage condition: v dd = 5 v 0.5 v; frame frequency prescaler = 011; 75 hz typical. the frame frequency (f fr ) is calculated from the clock frequency (f clk ) according to the equations described in table 16 . fig 22. frame frequency variation v dd (v) 1 6 5 34 2 001aak109 1740 1780 1820 1860 f clk (hz) 1700 001aak110 temperature ( c) ? 60 100 60 ? 20 ? 40 20 40 80 0 75.0 80.0 70.0 85.0 90.0 f fr (hz) 65.0 3.9 % 3.9 % 7.3 % 6.3 % max typ min 5.2 % 5.2 %
PCA85132_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 6 may 2010 35 of 53 nxp semiconductors PCA85132 lcd driver for low multiplex rates fig 23. driver timing waveforms 001aah8 48 t pd(drv) t sync_nl t pd(sync_n) clk sync bp0 to bp3, and s0 to s159 t clk(h) t clk(l) 1 / f clk 0.7 v dd 0.3 v dd 0.7 v dd 0.3 v dd 0.5 v (v dd = 5 v) 0.5 v fig 24. i 2 c-bus timing wavefo rms when sda and sdaack are connected 013aaa110 t f 70 % 30 % sda t f 70 % 30 % s t r 70 % 30 % 70 % 30 % t hd;dat scl 1 / f scl 1 st clock cycle 70 % 30 % 70 % 30 % t r t vd;ack cont. cont. sda scl t su;sta t hd;sta sr t sp t su;sto t buf p s t high 9 th clock t hd;sta t low 70 % 30 % t vd;ack 9 th clock t su;dat
PCA85132_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 6 may 2010 36 of 53 nxp semiconductors PCA85132 lcd driver for low multiplex rates 12. application information 12.1 pull-up resistor sizing on i 2 c-bus 12.1.1 max value of pull-up resistor the bus capacitance (c b ) is the total capacitance of wir e, connections, and pins. this capacitance on pin sda limits the maximum value of the pull-up resistor (r pu ) due to the specified rise time. according to the i 2 c-bus specification the rise time (t r ) is defined between the v dd related input threshold of v il =0.3v dd and v ih =0.7v dd . the value for t r(max) is 300 ns. t r will be calculated with equation 6 : (6) whereas t1 and t2 are the time since the charging started. the values for t1 and t2 are derivatives of the functions v(t1) and v(t2): (7) (8) with the results of (9) (10) (11) r pu(max) is a function of the rise time (t r ) and the bus capacitance (c b ) and will be calculated with equation 12 : (12) 12.1.2 min value of pull-up resistor the supply voltage limits the minimum value of resistor r pu due to the specified minimum sink current (see value of i ol on pin sdaack in table 18 ). r pu(min) as a function of v dd is calculated with equation 13 : (13) the designer now has the minimum and maximum value of r pu . the values for r pu(max) and r pu(min) are shown in figure 25 and figure 26 . t r t2 t1 ? = vt1 () 0.3v dd v dd 1e -t1 r pu c b ? ? () == vt2 () 0.7v dd v dd 1e -t2 r pu c b ? ? () == t1 r ? pu c b ln 0.7 () = t2 r ? pu c b ln 0.3 () = t r r ? pu c b ln 0.3 () r pu c b ln 0.7 () + = r pu max () t r 0.8473c b ---------------------- - 300 10 9 ? 0.8473c b ------------------------- - = = r pu min () v dd v ol ? i ol -------------------------- =
PCA85132_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 6 may 2010 37 of 53 nxp semiconductors PCA85132 lcd driver for low multiplex rates 12.2 sda and sdaa ck configuration the serial data line (sda) and the i 2 c-bus acknowledge line (sdaack) are split. both lines can be connected together to facilitate a single line sda. fig 25. values for r pu(max) fig 26. values for r pu(min) c b (pf) 20 500 340 180 100 420 260 60 380 220 140 460 300 001aak441 2 4 6 0 1 3 5 r pu(max) (k ) v dd (v) 1 6 5 34 2 1.5 5.5 3.5 4.5 2.5 001aak440 2 4 6 1 3 5 r pu(min) (k ) 0 fig 27. sda, sdaack configurations 013aaa111 sda two wire mode sdaack sda single wire mode sdaack
PCA85132_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 6 may 2010 38 of 53 nxp semiconductors PCA85132 lcd driver for low multiplex rates 12.3 cascaded operation in large display configurations, up to 8 p ca85132 can be distinguished on the same i 2 c-bus by using the 2-bit hardware subaddress (a0 and a1) and the programmable i 2 c-bus slave address (sa0). when cascaded PCA85132 are synchronized, they can share the backplane signals from one of the devices in the cascade. such an arrangement is cost-effective in large lcd applications since the backplane outputs of only one device need to be through-plated to the backplane electrodes of the display. the other PCA85132 of the cascade contribute additional segment outputs but their backpl ane outputs are left open-circuit (see figure 28 ). for display sizes that are not multiple of 640 elements, a mixed cascaded system can be considered containing only devices like PCA85132 and pca85133. depending on the application, one must take care of the software co mmands compatibility and pin connection compatibility. the sync line is provided to maintain the corr ect synchronization between all cascaded PCA85132. this synchronization is guaranteed after the power-on reset (por). the only time that sync is likely to be needed is if synchron ization is accidentally lost (e.g. by noise in adverse electrical environments, or by the definition of a multiplex mode when PCA85132 with different sa0 levels are cascaded). sync is organized as an input/output pin; the output selection being realized as an open-drain driver with an internal pull-up resistor. a PCA85132 asserts the sync line at the onset of its last active backplane signal and monitors the sync line at all other times. should synchronization in the cascade be lost, it will be restored by the first PCA85132 to assert sync . the timing relationship between the backplane waveforms and the sync signal for the various drive modes of the PCA85132 are shown in figure 30 . when using an external clock signal with high frequencies (f clk(ext) > 4 khz) it is recommended to have an external pull-up resistor between pin sync and pin v dd (see ta b l e 1 9 ). this resistor should be present even when no cascading configuration is used! when using it in a cascaded configuration, care must be taken not to route the sync signal to close to noisy signals. the contact resistance between the sync pads of cascaded devices must be controlled. if the resistance is too high, the device will not be able to synchronize properly. this is particularly applicable to cog applications. table 21 shows the limiting values for contact resistance. table 20. addressing cascaded PCA85132 cluster bit sa0 pin a1 pin a0 device 10000 011 102 113 21004 015 106 117
PCA85132_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 6 may 2010 39 of 53 nxp semiconductors PCA85132 lcd driver for low multiplex rates in the cascaded applications, the osc pi n of the PCA85132 with subaddress 0 is connected to v ss so that this device uses its internal clock to generate a clock signal at the clk pin. the other PCA85132 devices are having the osc pin connected to v dd , meaning that these devices are ready to receiv e external clock, the signal being provided by the device with subaddress 0. in the case that the master is providing the clock signal to the slave devices, care must be taken that the sending of disp lay enable or disable will be re ceived by both , the master and the slaves at the same time. when the di splay is disabled the output from pin clk is disabled too. the disconnectio n of the clock may result in a dc component for the display. alternatively, the schematic can be also cons tructed such that all the devices have osc pin connected to v dd and thus an external clk being provided for the system (all devices connected to the same external clk). a configuration where sync is connected but all PCA85132 are using the internal clock (osc pin tied to v ss ) is not recommended and may lead to display artifacts! table 21. sync contact resistance number of devices maximum contact resistance 2 6000 3 to 5 2200 6 to 8 1200
PCA85132_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 6 may 2010 40 of 53 nxp semiconductors PCA85132 lcd driver for low multiplex rates (1) is master (osc connected to v ss ). (2) is slave (osc connected to v dd ). fig 28. cascaded configuration with two pca85 132 using the internal clock of the master host micro- processor/ micro- controller sda scl clk osc sync 160 segment drives 4 backplanes segment drives lcd panel (up to 2560 elements) PCA85132 a0 a1 sa0 v dd v lcd dd v lcd v 013aaa06 2 sda scl sync clk osc bp0 to bp3 (open-circuit) a0 a1 sa0 v ss v ss v ss v dd v lcd PCA85132 bp0 to bp3 r t r 2c b (2) (1) 160/80/40
PCA85132_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 6 may 2010 41 of 53 nxp semiconductors PCA85132 lcd driver for low multiplex rates (1) is master (osc connected to v ss ). (2) is slave (osc connected to v dd ). fig 29. cascaded configuration with one PCA85132 and one pca85133 using the internal clock of the master host micro- processor/ micro- controller sda scl clk osc sync 160 segment drives 4 backplanes segment drives lcd panel (up to 2560 elements) PCA85132 a0 a1 sa0 v dd v lcd dd v lcd v 013aaa06 3 sda scl sync clk osc bp0 to bp3 (open-circuit) a0 a1 sa0 v ss v ss v ss v dd v lcd pca85133 bp0 to bp3 r t r 2c b (2) (1) 80/40 a2
PCA85132_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 6 may 2010 42 of 53 nxp semiconductors PCA85132 lcd driver for low multiplex rates fig 30. synchronization of the cascade for the various PCA85132 drive modes 001aaj498 t fr = 1 f fr bp0 (a) static drive mode (b) 1:2 multiplex drive mode (c) 1:3 multiplex drive mode (d) 1:4 multiplex drive mode bp1 (1/2 bias) bp1 (1/3 bias) bp2 (1/3 bias) bp3 (1/3 bias) sync sync sync sync
PCA85132_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 6 may 2010 43 of 53 nxp semiconductors PCA85132 lcd driver for low multiplex rates 13. bare die outline fig 31. bare die outline of PCA85132 marking code: pc85132/232-1 references outline version european projection issue date iec jedec jeita PCA85132u PCA85132_do unit mm max nom min 0.018 0.015 0.012 0.380 6.5 1.16 0.054 0.2025 a 1 (1) dimensions note 1. dimension not drawn to scale. b are die; 197 bumps; 6.5 x 1.16 x 0.40 mm PCA85132 u a 2 (1) b (1) 0.0338 d 0.40 a (1) ee (1) e 1 (1) l (1) 0.090 0 1 2 mm scale detail y b e l e 1 x detail x a 2 a a 1 y 197 167 c1 s1 60 166 61 0 0 d e +y +x 09-08-18 09-10-12 1
PCA85132_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 6 may 2010 44 of 53 nxp semiconductors PCA85132 lcd driver for low multiplex rates table 22. bump locations all x/y coordinates represent the position of the ce nter of each bump with respect to the center (x/y = 0) of the chip; see figure 31 . symbol bump x ( m) y ( m) symbol bump x ( m) y ( m) sdaack 1 ? 1165.3 ? 481.5 s68 100 750.2 481.5 sdaack 2 ? 1111.3 ? 481.5 s69 101 696.2 481.5 sdaack 3 ? 1057.3 ? 481.5 s70 102 642.2 481.5 sda 4 ? 854.8 ? 481.5 s71 103 588.2 481.5 sda 5 ? 800.8 ? 481.5 s72 104 534.2 481.5 sda 6 ? 746.8 ? 481.5 s73 105 480.2 481.5 scl 7 ? 575.8 ? 481.5 s74 106 426.2 481.5 scl 8 ? 521.8 ? 481.5 s75 107 372.2 481.5 scl 9 ? 467.8 ? 481.5 s76 108 318.2 481.5 clk 10 ? 316.2 ? 481.5 s77 109 264.2 481.5 v dd 11 ? 204.1 ? 481.5 s78 110 210.2 481.5 v dd 12 ? 150.1 ? 481.5 s79 111 156.2 481.5 v dd 13 ? 96.1 ? 481.5 bp0 112 86.8 481.5 sync 14 6.9 ? 481.5 bp2 113 32.8 481.5 osc 15 119.4 ? 481.5 bp1 114 ? 21.2 481.5 t1 16 203.1 ? 481.5 bp3 115 ? 75.2 481.5 t2 17 286.8 ? 481.5 s80 116 ? 190.7 481.5 t3 18 389.9 ? 481.5 s81 117 ? 244.7 481.5 t3 19 443.9 ? 481.5 s82 118 ? 298.7 481.5 t3 20 497.9 ? 481.5 s83 119 ? 352.7 481.5 a0 21 640.5 ? 481.5 s84 120 ? 406.7 481.5 a1 22 724.2 ? 481.5 s85 121 ? 460.7 481.5 sa0 23 807.9 ? 481.5 s86 122 ? 514.7 481.5 v ss 24 893.0 ? 481.5 s87 123 ? 568.7 481.5 v ss 25 947.0 ? 481.5 s88 124 ? 622.7 481.5 v ss 26 1001.0 ? 481.5 s89 125 ? 676.7 481.5 v lcd 27 1107.2 ? 481.5 s90 126 ? 730.7 481.5 v lcd 28 1161.2 ? 481.5 s91 127 ? 784.7 481.5 v lcd 29 1215.2 ? 481.5 s92 128 ? 838.7 481.5 bp2 30 1303.4 ? 481.5 s93 129 ? 892.7 481.5 bp0 31 1357.4 ? 481.5 s94 130 ? 946.7 481.5 s0 32 1411.4 ? 481.5 s95 131 ? 1000.7 481.5 s1 33 1465.4 ? 481.5 s96 132 ? 1054.7 481.5 s2 34 1519.4 ? 481.5 s97 133 ? 1108.7 481.5 s3 35 1573.4 ? 481.5 s98 134 ? 1224.2 481.5 s4 36 1627.4 ? 481.5 s99 135 ? 1278.2 481.5 s5 37 1681.4 ? 481.5 s100 136 ? 1332.2 481.5 s6 38 1735.4 ? 481.5 s101 137 ? 1386.2 481.5 s7 39 1789.4 ? 481.5 s102 138 ? 1440.2 481.5
PCA85132_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 6 may 2010 45 of 53 nxp semiconductors PCA85132 lcd driver for low multiplex rates s8 40 1843.4 ? 481.5 s103 139 ? 1494.2 481.5 s9 41 1897.4 ? 481.5 s104 140 ? 1548.2 481.5 s10 42 1951.4 ? 481.5 s105 141 ? 1602.2 481.5 s11 43 2005.4 ? 481.5 s106 142 ? 1656.2 481.5 s12 44 2059.4 ? 481.5 s107 143 ? 1710.2 481.5 s13 45 2113.4 ? 481.5 s108 144 ? 1764.2 481.5 s14 46 2167.4 ? 481.5 s109 145 ? 1818.2 481.5 s15 47 2221.4 ? 481.5 s110 146 ? 1872.2 481.5 s16 48 2363.9 ? 481.5 s111 147 ? 1926.2 481.5 s17 49 2417.9 ? 481.5 s112 148 ? 1980.2 481.5 s18 50 2471.9 ? 481.5 s113 149 ? 2034.2 481.5 s19 51 2525.9 ? 481.5 s114 150 ? 2088.2 481.5 s20 52 2579.9 ? 481.5 s115 151 ? 2142.2 481.5 s21 53 2633.9 ? 481.5 s116 152 ? 2284.7 481.5 s22 54 2687.9 ? 481.5 s117 153 ? 2338.7 481.5 s23 55 2741.9 ? 481.5 s118 154 ? 2392.7 481.5 s24 56 2795.9 ? 481.5 s119 155 ? 2446.7 481.5 s25 57 2849.9 ? 481.5 s120 156 ? 2500.7 481.5 s26 58 2903.9 ? 481.5 s121 157 ? 2554.7 481.5 s27 59 2957.9 ? 481.5 s122 158 ? 2608.7 481.5 s28 60 3011.9 ? 481.5 s123 159 ? 2662.7 481.5 s29 61 3067.7 481.5 s124 160 ? 2716.7 481.5 s30 62 3013.7 481.5 s125 161 ? 2770.7 481.5 s31 63 2959.7 481.5 s126 162 ? 2824.7 481.5 s32 64 2905.7 481.5 s127 163 ? 2878.7 481.5 s33 65 2851.7 481.5 s128 164 ? 2932.7 481.5 s34 66 2797.7 481.5 s129 165 ? 2986.7 481.5 s35 67 2743.7 481.5 s130 166 ? 3040.7 481.5 s36 68 2689.7 481.5 s131 167 ? 3025.2 ? 481.5 s37 69 2635.7 481.5 s132 168 ? 2971.2 ? 481.5 s38 70 2520.2 481.5 s133 169 ? 2917.2 ? 481.5 s39 71 2466.2 481.5 s134 170 ? 2863.2 ? 481.5 s40 72 2412.2 481.5 s135 171 ? 2809.2 ? 481.5 s41 73 2358.2 481.5 s136 172 ? 2755.2 ? 481.5 s42 74 2304.2 481.5 s137 173 ? 2701.2 ? 481.5 s43 75 2250.2 481.5 s138 174 ? 2647.2 ? 481.5 s44 76 2196.2 481.5 s139 175 ? 2593.2 ? 481.5 s45 77 2142.2 481.5 s140 176 ? 2539.2 ? 481.5 s46 78 2088.2 481.5 s141 177 ? 2485.2 ? 481.5 table 22. bump locations ?continued all x/y coordinates represent the position of the ce nter of each bump with respect to the center (x/y = 0) of the chip; see figure 31 . symbol bump x ( m) y ( m) symbol bump x ( m) y ( m)
PCA85132_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 6 may 2010 46 of 53 nxp semiconductors PCA85132 lcd driver for low multiplex rates the dummy pins are connected to the segments shown (see ta b l e 2 3 ) but are not tested. the alignment marks are shown in table 24 . s47 79 2034.2 481.5 s142 178 ? 2431.2 ? 481.5 s48 80 1891.7 481.5 s143 179 ? 2377.2 ? 481.5 s49 81 1837.7 481.5 s144 180 ? 2234.7 ? 481.5 s50 82 1783.7 481.5 s145 181 ? 2180.7 ? 481.5 s51 83 1729.7 481.5 s146 182 ? 2126.7 ? 481.5 s52 84 1675.7 481.5 s147 183 ? 2072.7 ? 481.5 s53 85 1621.7 481.5 s148 184 ? 2018.7 ? 481.5 s54 86 1567.7 481.5 s149 185 ? 1964.7 ? 481.5 s55 87 1513.7 481.5 s150 186 ? 1910.7 ? 481.5 s56 88 1459.7 481.5 s151 187 ? 1856.7 ? 481.5 s57 89 1405.7 481.5 s152 188 ? 1802.7 ? 481.5 s58 90 1351.7 481.5 s153 189 ? 1748.7 ? 481.5 s59 91 1297.7 481.5 s154 190 ? 1694.7 ? 481.5 s60 92 1243.7 481.5 s155 191 ? 1640.7 ? 481.5 s61 93 1189.7 481.5 s156 192 ? 1586.7 ? 481.5 s62 94 1135.7 481.5 s157 193 ? 1532.7 ? 481.5 s63 95 1081.7 481.5 s158 194 ? 1478.7 ? 481.5 s64 96 1027.7 481.5 s159 195 ? 1424.7 ? 481.5 s65 97 973.7 481.5 bp3 196 ? 1370.7 ? 481.5 s66 98 858.2 481.5 bp1 197 ? 1316.7 ? 481.5 s67 99 804.2 481.5 table 23. dummy bumps all x/y coordinates represent the position of the ce nter of each bump with respect to the center (x/y = 0) of the chip; see figure 31 . symbol connected to pin x ( m) y ( m) d1 s131 ? 3079.2 ? 481.5 d2 s28 3065.9 ? 481.5 d3 s29 3121.7 481.5 d4 s130 ? 3094.7 481.5 table 24. alignment marking all x/y coordinates represent the position of the ref point (see figure 32 ) with respect to the center (x/y = 0) of the chip; see figure 31 . symbol size ( m) x ( m) y ( m) s1 121.5 121.5 ? 2733.75 ? 47.25 c1 121.5 121.5 2603.7 ? 47.25 table 22. bump locations ?continued all x/y coordinates represent the position of the ce nter of each bump with respect to the center (x/y = 0) of the chip; see figure 31 . symbol bump x ( m) y ( m) symbol bump x ( m) y ( m)
PCA85132_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 6 may 2010 47 of 53 nxp semiconductors PCA85132 lcd driver for low multiplex rates [1] pressure of diamond head: 10 g to 50 g. fig 32. alignment marks table 25. gold bump hardness type number min max unit [1] PCA85132u/2da/q1 60 120 hv PCA85132u/2db/q1 35 80 hv 001aah84 9 ref ref c1 s1
PCA85132_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 6 may 2010 48 of 53 nxp semiconductors PCA85132 lcd driver for low multiplex rates 14. packing information table 26. tray dimensions (see figure 33 ) symbol description value a pocket pitch in x direction 8.8 mm b pocket pitch in y direction 3.6 mm c pocket width in x direction 6.65 mm d pocket width in y direction 1.31 mm e tray width in x direction 50.8 mm f tray width in y direction 50.8 mm x number of pockets, x direction 5 y number of pockets, y direction 12 fig 33. tray details 001aah890 ac d b e f y x
PCA85132_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 6 may 2010 49 of 53 nxp semiconductors PCA85132 lcd driver for low multiplex rates 15. abbreviations fig 34. tray alignment 001aaj643 marking code table 27. abbreviations acronym description aec automotive electronics council cmos complementary metal-oxide semiconductor cog chip-on-glass dc direct current hbm human body model i 2 c inter-integrated circuit ito indium tin oxide lcd liquid crystal display lsb least significant bit mm machine model msb most significant bit por power-on reset rc resistance and capacitance ram random access memory rms root mean square scl serial clock line sda serial data line
PCA85132_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 6 may 2010 50 of 53 nxp semiconductors PCA85132 lcd driver for low multiplex rates 16. references [1] an10170 ? design guidelines for cog modules with nxp monochrome lcd drivers [2] an10706 ? handling bare die [3] iec 60134 ? rating systems for electronic tu bes and valves and analogous semiconductor devices [4] iec 61340-5 ? protection of electronic devices from electrostatic phenomena [5] jesd22-a114 ? electrostatic discharge (esd) sensitivity testing human body model (hbm) [6] jesd22-a115 ? electrostatic discharge (esd) se nsitivity testing machine model (mm) [7] jesd78 ? ic latch-up test [8] jesd625-a ? requirements for handling elec trostatic-discharge-sensitive (esds) devices [9] nx3-00092 ? nxp store and transport requirements [10] um10204 ? i 2 c-bus specification and user manual 17. revision history table 28. revision history document id release date data sheet status change notice supersedes PCA85132_1 20100506 product data sheet - -
PCA85132_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 6 may 2010 51 of 53 nxp semiconductors PCA85132 lcd driver for low multiplex rates 18. legal information 18.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 18.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 18.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interrupt ion, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use in automotive applications ? this nxp semiconductors product has been qua lified for use in automotive applications. the product is not desi gned, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be ex pected to result in personal injury, death or severe property or environmental dam age. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or customer product design. it is customer?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as fo r the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this docu ment contains the product specification.
PCA85132_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 6 may 2010 52 of 53 nxp semiconductors PCA85132 lcd driver for low multiplex rates export control ? this document as well as the item(s) described herein may be subject to export control regu lations. export might require a prior authorization from national authorities. bare die ? all die are tested on compliance with their related technical specifications as stated in this data sheet up to the point of wafer sawing and are handled in accordance with the nxp semiconductors storage and transportation conditions. if there are da ta sheet limits not guaranteed, these will be separately indicated in the data sheet. there are no post-packing tests performed on individual die or wafers. nxp semiconductors has no control of third party procedures in the sawing, handling, packing or assembly of the die. accordingly, nxp semiconductors assumes no liability for device functionality or performance of the die or systems after third party sawing, handling, packing or assembly of the die. it is the responsibility of the customer to test and qualify their application in which the die is used. all die sales are conditioned upon and subject to the customer entering into a written die sale agreement with nxp semiconductors through its legal department. 18.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. i 2 c-bus ? logo is a trademark of nxp b.v. 19. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com
nxp semiconductors PCA85132 lcd driver for low multiplex rates ? nxp b.v. 2010. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 6 may 2010 document identifier: PCA85132_1 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 20. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 4 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 functional description . . . . . . . . . . . . . . . . . . . 6 7.1 power-on reset (por) . . . . . . . . . . . . . . . . . . 7 7.2 lcd bias generator . . . . . . . . . . . . . . . . . . . . . 7 7.3 lcd voltage selector . . . . . . . . . . . . . . . . . . . . 8 7.4 lcd drive mode waveforms . . . . . . . . . . . . . . 10 7.4.1 static drive mode . . . . . . . . . . . . . . . . . . . . . . 10 7.4.2 1:2 multiplex drive mode. . . . . . . . . . . . . . . . . 11 7.4.3 1:3 multiplex drive mode. . . . . . . . . . . . . . . . . 13 7.4.4 1:4 multiplex drive mode. . . . . . . . . . . . . . . . . 14 7.5 oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.5.1 internal clock . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.5.2 external clock . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.6 timing and frame frequency . . . . . . . . . . . . . . 15 7.7 display register . . . . . . . . . . . . . . . . . . . . . . . . 15 7.8 segment outputs. . . . . . . . . . . . . . . . . . . . . . . 16 7.9 backplane outputs . . . . . . . . . . . . . . . . . . . . . 16 7.10 display ram . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.11 data pointer . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.12 subaddress counter . . . . . . . . . . . . . . . . . . . . 19 7.13 output bank selector . . . . . . . . . . . . . . . . . . . 19 7.14 input bank selector . . . . . . . . . . . . . . . . . . . . . 20 7.15 blinker. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.16 characteristics of the i 2 c-bus. . . . . . . . . . . . . 20 7.16.1 bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.16.1.1 start and stop conditions . . . . . . . . . . . . . 21 7.16.2 system configuration . . . . . . . . . . . . . . . . . . . 22 7.16.3 acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.16.4 i 2 c-bus controller . . . . . . . . . . . . . . . . . . . . . . 23 7.16.5 input filters . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.16.6 i 2 c-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 23 7.17 command decoder . . . . . . . . . . . . . . . . . . . . . 25 7.18 display controller . . . . . . . . . . . . . . . . . . . . . . 27 8 internal circuitry. . . . . . . . . . . . . . . . . . . . . . . . 28 9 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 29 10 static characteristics. . . . . . . . . . . . . . . . . . . . 30 11 dynamic characteristics . . . . . . . . . . . . . . . . . 33 12 application information. . . . . . . . . . . . . . . . . . 36 12.1 pull-up resistor sizing on i 2 c-bus . . . . . . . . . . 36 12.1.1 max value of pull-up resistor . . . . . . . . . . . . . 36 12.1.2 min value of pull-up resist or . . . . . . . . . . . . . . 36 12.2 sda and sdaack configuration . . . . . . . . . . 37 12.3 cascaded operation. . . . . . . . . . . . . . . . . . . . 38 13 bare die outline . . . . . . . . . . . . . . . . . . . . . . . . 43 14 packing information . . . . . . . . . . . . . . . . . . . . 48 15 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 49 16 references. . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 17 revision history . . . . . . . . . . . . . . . . . . . . . . . 50 18 legal information . . . . . . . . . . . . . . . . . . . . . . 51 18.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 51 18.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 18.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 51 18.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 52 19 contact information . . . . . . . . . . . . . . . . . . . . 52 20 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

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