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AU5790 single wire can transceiver product data supersedes data of 2001 jan 31 ic18 data handbook 2001 may 18 integrated circuits
philips semiconductors product data AU5790 single wire can transceiver 2 2001 may 18 853-2237 26343 features ? supports in-vehicle class b multiplexing via a single bus line with ground return ? 33 kbps can bus speed with loading as per j2411 ? 83 kbps high-speed transmission mode ? low rfi due to output waveshaping ? direct battery operation with protection against load dump, jump start and transients ? bus terminal protected against short-circuits and transients in the automotive environment ? built-in loss of ground protection ? thermal overload protection ? supports communication between control units even when network in low-power state ? 70 m a typical power consumption in sleep mode ? 8- and 14-pin small outline packages ? 8 kv esd protection on bus and battery pins description the AU5790 is a line transceiver, primarily intended for in-vehicle multiplex applications. the device provides an interface between a can data link controller and a single wire physical bus line. the achievable bus speed is primarily a function of the network time constant and bit timing, e.g., up to 33.3 kbps with a network including 32 bus nodes. the AU5790 provides advanced sleep/wake-up functions to minimize power consumption when a vehicle is parked, while offering the desired control functions of the network at the same time. fast transfer of larger blocks of data is supported using the high-speed data transmission mode. quick reference data symbol parameter conditions min. typ. max. unit v bat operating supply voltage 5.3 13 27 v t amb operating ambient temperature range 40 +125 c v batld battery voltage load dump; 1s +40 v v canhn bus output voltage 3.65 4.55 v v t bus input threshold 1.8 2.2 v t trn bus output delay, rising edge 3 6.3 m s t tfn bus output delay, falling edge 3 9 m s t dn bus input delay 0.3 1 m s i bats sleep mode supply current 70 100 m a ordering information description temperature range order code dwg # so8: 8-pin plastic small outline package 40 c to +125 c AU5790d sot961 so14: 14-pin plastic small outline package 40 c to +125 c AU5790d14 sot1081
philips semiconductors product data AU5790 single wire can transceiver 2001 may 18 3 block diagram sl01199 gnd txd mode control bat temp. protection output buffer voltage reference AU5790 8 rxd bus receiver nstb battery (+12v) canh 1 3 4 5 6 7 loss of protection ground en (mode 1) (mode 0) r t rth (load) (bus) figure 1. block diagram
philips semiconductors product data AU5790 single wire can transceiver 2001 may 18 4 so8 pin configuration sl01198 1 2 3 4 8 7 6 so8 5 nstb (mode 0) en (mode 1) rxd gnd txd canh (bus) bat rth (load) AU5790 so8 pin description sym- bol pin description txd 1 transmit data input: high = transmitter passive; low = transmitter active nstb (mode 0) 2 stand-by control: high = normal and high-speed mode; low = sleep and wake-up mode en (mode 1) 3 enable control: high = normal and wake-up mode; low = sleep and high-speed mode rxd 4 receive data output: low = active bus condition detected; float/high = passive bus condition detected bat 5 battery supply input (12 v nom.) rth (load) 6 switched ground pin: pulls the load to ground, except in case the module ground is disconnected canh (bus) 7 bus line transmit input/output gnd 8 ground so14 pin configuration sl01251 1 2 3 4 14 13 12 so14 11 nstb (mode 0) en (mode 1) rxd gnd txd n.c. AU5790 5 6 7 10 9 8 n.c. gnd canh (bus) bat rth (load) gnd n.c. gnd so14 pin description sym- bol pin description gnd 1 ground txd 2 transmit data input: high = transmitter passive; low = transmitter active nstb (mode 0) 3 stand-by control: high = normal and high-speed mode; low = sleep and wake-up mode en (mode 1) 4 enable control: high = normal and wake-up mode; low = sleep and high-speed mode rxd 5 receive data output: low = active bus condition detected; float/high = passive bus condition detected n.c. 6 no connection gnd 7 ground gnd 8 ground n.c. 9 no connection bat 10 battery supply input (12 v nom.) rth (load) 11 switched ground pin: pulls the load to ground, except in case the module ground is disconnected canh (bus) 12 bus line transmit input/output n.c. 13 no connection gnd 14 ground
philips semiconductors product data AU5790 single wire can transceiver 2001 may 18 5 functional description the AU5790 is an integrated line transceiver ic that interfaces a can protocol controller to the vehicle's multiplexed bus line. it is primarily intended for automotive aclass bo multiplexing applications in passenger cars using a single wire bus line with ground return. the achievable bit rate is primarily a function of the network time constant and the bit timing parameters. for example, the maximum bus speed is 33 kpbs with bus loading as specified in j2411 for a full 32 node bus, while 41.6 kbps at is possible with modified bus loading. the AU5790 also supports low-power sleep mode to help meet ignition-off current draw requirements. the protocol controller feeds the transmit data stream to the transceiver's txd input. the AU5790 transceiver converts the txd data input to a bus signal with controlled slew rate and waveshaping to minimize emissions. the bus output signal is transmitted via the canh in/output, connected to the physical bus line. if txd is low, then a typical voltage of 4 v is output at the canh pin. if txd is high then the canh output is pulled passive low via the local bus load resistance r t . to provide protection against a disconnection of the module ground, the resistor r t is connected to the rth pin of the AU5790. by providing this switched ground pin, no current can flow from the floating module ground to the bus. the bus receiver detects the data stream on the bus line. the data signal is output at the rxd pin being connected to a can controller. the AU5790 provides appropriate filtering to ensure low susceptibility against electromagnetic interference. further enhancement is possible with applying an external capacitor between canh and ground potential. the device features low bus output leakage current at power supply failure situations. if the nstb and en control inputs are pulled low or floating, the AU5790 enters a low-power or asleepo mode. this mode is dedicated to minimizing ignition-off current drain, to enhance system efficiency. in sleep mode, the bus transmit function is disabled, e.g. the canh output is inactive even when txd is pulled low. an internal network active detector monitors the bus for any occurrence of signal edges on the bus line. if such edges are detected, this will be signalled to the can controller via the rxd output. normal transmission mode will be entered again upon a high level being applied to the nstb and en control inputs. these signals are typically being provided by a controller device. sleeping bus nodes will generally ignore normal communication on the bus. they should be activated using the dedicated wake-up mode. when nstb is low and en is high the AU5790 enters wake-up mode i.e. it sends data with an increased signal level. this will result in an activation of other bus nodes being attached to the network. the AU5790 also provides a high-speed transmission mode supporting bit rates up to 100 kbps. if the nstb input is pulled high and the en input is low, then the internal waveshaping function is disabled, i.e. the bus driver is turned on and off as fast as possible to support high-speed transmission of data. consequently, the emc performance is degraded in this mode compared to the normal transmission mode. in high-speed transmission mode the AU5790 supports the same bus signal level as specified for the canh output in normal mode. the AU5790 features special robustness at its bat and canh pins. hence the device is well suited for applications in the automotive environment. the bat input is protected against 40 v load dump and jump start condition. the canh output is protected against wiring fault conditions, e.g., short circuit to ground or battery voltage, as well as typical automotive transients. in addition, an over-temperature shutdown function with hysteresis is incorporated protecting the device under system fault conditions. in case of the chip temperature reaching the trip point, the AU5790 will latch-off the transmit function. the transmit function is available again after a small decrease of the chip temperature. the AU5790 contains a power-on reset circuit. for v bat < 2.5 v, the canh output drive will be turned off, the output will be passive, and rxd will be high. for 2.5 v < v bat < 5.3 v, the canh output drive may operate normally or be turned off. table 1. control input summary nstb en txd description canh rxd 0 0 don't care sleep mode 0 v float (high) 0 1 tx-data wake-up transmission mode 0 v, 12 v bus state 1 1 0 tx-data high-speed transmission mode 0 v, 4 v bus state 1 1 1 tx-data normal transmission mode 0 v, 4 v bus state 1 note: 1. rxd outputs the bus state. if the bus level is below the receiver threshold (i.e., all transmitters passive), then rxd will b e floating (i.e., high, considering external pull-up resistance). otherwise, if the bus level is above the receiver threshold (i.e., at least one trans mitter is active), then rxd will be low.
philips semiconductors product data AU5790 single wire can transceiver 2001 may 18 6 absolute maximum ratings according to the iec 134 absolute maximum system: operation is not guaranteed under these conditions; all voltages are referenc ed to pin 8 (gnd); positive currents flow into the ic, unless otherwise specified. symbol parameter conditions min. max. unit v bat supply voltage steady state 0.3 +27 v v batld short-term supply voltage load dump; iso7637/1 test pulse 5 (sae j1113, test pulse 5), t < 1s +40 v v battr2 transient supply voltage iso 7637/1 test pulse 2 (sae j1113, test pulse 2), with series diode and bypass cap of 100 nf between bat and gnd pins, note 2. +100 v v battr3 transient supply voltage iso 7637/1 pulses 3a and 3b (sae j1113 test pulse 3a and 3b), note 2. 150 +100 v v canh_1 canh voltage v bat > 2 v 10 +18 v v canh_0 canh voltage v bat < 2 v 16 +18 v v canhtr1 transient bus voltage iso 7637/1 test pulse 1, notes 1 and 2 100 v v canhtr2 transient bus voltage iso 7637/1 test pulse 2, notes 1 and 2 +100 v v canhtr3 transient bus voltage iso 7637/1 test pulses 3a, 3b, notes 1 and 2 150 +100 v v rth1 pin rth voltage v bat > 2 v, voltage applied to pin rth via a 2 k w series resistor 10 +18 v v rth0 pin rth voltage v bat < 2 v, voltage applied to pin rth via a 2 k w series resistor 16 +18 v v i dc voltage on pins txd, en, rxd, nstb 0.3 +7 v esd bahb esd capability of pin bat direct contact discharge, r=1.5 k w , c=100 pf 8 +8 kv esd chhb esd capability of pin canh direct contact discharge, r=1.5 k w , c=100 pf 8 +8 kv esd rthb esd capability of pin rth direct contact discharge, r=1.5 k w + 3 k w , c=100 pf 8 +8 kv esd lghb esd capability of pins txd, nstb, en, rxd, and rth direct contact discharge, r=1.5 k w , c=100 pf 2 +2 kv r tmin bus load resistance r t being connected to pin rth 2 k w t amb operating ambient temperature 40 +125 c t stg storage temperature 40 +150 c t vj junction temperature 40 +150 c notes: 1. test pulses are coupled to canh through a series capacitance of 1 nf. 2. rise time for test pulse 1: t r < 1 m s; pulse 2: t r < 100 ns; pulses 3a/3b: t r < 5 ns.
philips semiconductors product data AU5790 single wire can transceiver 2001 may 18 7 dc characteristics 40 c < t amb < +125 c; 5.5 v < v bat < 16 v; 0.3 v < v txd < 5.5 v; 0.3 v < v nstb < 5.5 v; 0.3 v < v en < 5.5 v; 0.3 v < v rxd < 5.5 v; 1 v < v canh < +16 v; bus load resistor at pin rth: 2 k w < r t < 9.2 k w ; total bus load resistance 270 w < r l < 9.2 k w ; c l < 13.7 nf; 1 m s < r l * c l < 4 m s; rxd pull-up resistor 2.2 k w < r d < 3.0 k w ; rxd: loaded with c lr < 30pf to gnd; all voltages are referenced to pin 8 (gnd); positive currents flow into the ic; typical values reflect the approximate average value at v bat = 13 v and t amb = 25 c, unless otherwise specified. symbol parameter conditions min. typ. max. unit pin bat v bat operating supply voltage note 1 5.3 13 27 v v batl low battery state part functional or in undervoltage lockout state 2.5 5.3 v v batlo supply undervoltage lockout state txd = 1 or 0; check canh and rxd are floating 2.5 v i batpn passive state supply current in normal mode nstb = 5 v, en = 5 v, txd = 5 v 2 ma i batpw passive state supply current in wake-up mode nstb = 0 v, en = 5 v, txd = 5 v, note 2 3 ma i batph passive state supply current in high speed mode nstb = 5 v, en = 0 v, txd = 5 v, note 2 4 ma i batn active state supply current in normal mode nstb = 5 v, en = 5 v, txd = 0 v, r l = 270 w, t amb = 125 c 35 ma t amb = 25 c, 40 c 40 ma i batw active state supply current in wake-up mode nstb = 0 v, en = 5 v, txd = 0 v, r l = 270 w , note 2, t amb = 125 c 70 ma t amb = 25 c, 40 c, note 2 90 ma i bath active state supply current in high speed mode nstb = 5 v, en = 0 v, txd = 0 v, r l = 100 w , note 2, t amb = 125 c 70 ma t amb = 25 c, 40 c, note 2 85 ma i bats sleep mode supply current nstb = 0 v, en = 0 v, txd = 5 v, rxd = 5 v, 1 v < v canh < +1 v, 5.5 v < v bat < 14 v 40 c < t j < 125 c 70 100 m a pin canh v canhn bus output voltage in normal mode nstb = 5 v, en = 5 v, r l > 270 w ; 5.5 v < v bat < 27 v 3.65 4.1 4.55 v v canhw bus output voltage in wake-up mode nstb = 0 v, en = 5 v, r l > 270 w ; 11.3 v < v bat < 16 v 9.80 min (v bat , 13) v v canhwl bus output voltage in wake-up mode, low battery nstb = 0 v, en = 5 v, r l > 270 w ; 5.5 v < v bat < 11.3 v v bat 1.45 v bat v v canhh bus output voltage in high-speed transmission mode nstb = 5 v, en = 0 v, r l > 100 w ; 8 v < v bat < 16 v 3.65 4.55 v i canhrr recessive state output current, bus recessive recessive state or sleep mode, v canh = 1 v; 0 v < v bat < 27 v 10 10 m a i canhrd recessive state output current, bus dominant recessive state or sleep mode, v canh = 10 v; 0 v < v bat < 16 v 20 100 m a i canhdd dominant state output current, bus dominant txd = 0 v, normal mode, high-speed mode and sleep mode; v canh = 10 v; 0 v < v bat < 16 v 20 100 m a i canh_n bus short circuit current, normal mode v canh = 1 v, txd = 0 v; nstb = 5 v; en = 5 v 30 150 ma i canhw bus short circuit current, wake-up mode v canh = 1 v, txd = 0 v; nstb = 0 v; en = 5 v 60 190 ma
philips semiconductors product data AU5790 single wire can transceiver 2001 may 18 8 symbol unit max. typ. min. conditions parameter pin canh (continued) i canhh bus short circuit current in high-speed mode v canh = 1 v, txd = 0 v; nstb = 5 v; en = 0 v; 8 v < v bat < 16 v 50 190 ma i canlg bus leakage current at loss of ground (i_can_lg = i_canh + i_rth) 0 v < v bat < 16 v; see figure 3 in the test circuits section 50 50 m a t sd thermal shutdown note 2 155 190 c t hys thermal shutdown hysteresis note 2 5 15 c v t bus input threshold 5.8 v < v bat < 27 v, all modes except sleep mode 1.8 2.2 v v tl bus input threshold, low battery 5.5 v < v bat < 5.8 v, all modes except sleep mode 1.5 2.2 v v ts bus input threshold in sleep mode nstb = 0 v, en = 0 v, v bat > 11.3 v 6.15 8.1 v v tsl bus input threshold in sleep mode, low battery nstb = 0 v, en = 0 v, 5.5 v < v bat < 11.3 v v bat 4.3 v bat 3.25 v pin rth v rth1 voltage on switched ground pin i rth = 1 ma 0.1 v v rth2 voltage on switched ground pin i rth = 6 ma 1 v pins nstb, en v ih high level input voltage 5.5 v < v bat < 27 v 3 v v il low level input voltage 5.5 v < v bat < 27 v 1 v i i input current v i = 1 v and v i = 5 v 15 50 m a pin txd v itxd txd input threshold 5.5 v < v bat < 27 v 1 3 v i iltxd txd low level input current in normal mode nstb = 5 v, en = 5 v, v txd = 0 v 50 180 m a i ihtxd txd high level input current in sleep mode nstb = 0 v, en = 0 v, v txd = 5 v 5 10 m a pin rxd v olrxd rxd low level output voltage i rxd = 2.2 ma; v canh = 10 v, all modes 0.45 v i olrxd rxd low level output current v rxd = 5 v; v canh = 10 v 3 35 ma i ohrxd rxd high level leakage v rxd = 5 v; v canh = 0 v, all modes 10 +10 m a notes: 1. operation at battery voltages down to 5.3 volts is guaranteed by design. operation higher than 18 volts (18 v < v bat < 27 v) for up to two minutes is permitted if the thermal design of the board prevents reaching the thermal protection temperature limit, t sd , otherwise the device will self protect. typically these requirements will be encountered during jump start operation at t amb 85 c and v bat < 27 v. refer to the athermal characteristicso section of this data sheet, or application note an2005 for guidance. 2. this parameter is characterized but not subject to production test.
philips semiconductors product data AU5790 single wire can transceiver 2001 may 18 9 dynamic (ac) characteristics for 33 kbps operation 40 c < t amb < +125 c; 5.5 v < v bat < 16 v; 0.3 v < v txd < 5.5 v; 0.3 v < v nstb < 5.5 v; 0.3 v < v en < 5.5 v; 0.3 v < v rxd < 5.5 v; 1 v < v canh < +16 v; bus load resistor at pin rth: 2 k w < r t < 9.2 k w ; total bus load resistance 270 w < r l < 9.2 k w ; c l < 13.7 nf; 1 m s < r l * c l < 4 m s; rxd pull-up resistor 2.2 k w < r d < 3.0 k w ; rxd: loaded with c lr < 30pf to gnd; all voltages are referenced to pin 8 (gnd); positive currents flow into the ic; typical values reflect the approximate average value at v bat = 13 v and t amb = 25 c, unless otherwise specified. symbol parameter conditions min. typ. max. unit pin canh v dbamn canh harmonic content in normal mode nstb = 5 v, en = 5 v; r l = 270 w , c l = 15 nf; f txd = 20 khz, 50% duty cycle; 8 v < v bat < 16 v; 0.53 mhz < f < 1.7 mhz, note 2 70 db m v v dbamw canh harmonic content in wake-up mode nstb = 5 v, en = 0 v; r l = 270 w , c l = 15 nf; f txd = 20 khz, 50% duty cycle; 8 v < v bat < 16 v; 0.53 mhz < f < 1.7 mhz, note 2 80 db m v pins nstb, en t nh normal mode to high-speed mode delay 30 m s t hn high-speed mode to normal mode delay 30 m s t wn wake-up mode to normal mode delay 8 v < v bat < 16 v 30 m s t ns normal mode to sleep mode delay 500 m s t sn sleep mode to normal mode delay 50 m s pin txd t trn transmit delay in normal mode, bus rising edge nstb = 5 v, en = 5 v; r l = 270 w , c l = 15 nf; 5.5 v < v bat < 27 v; measured from the falling edge on txd to v canh = 3.0 v 3 6.3 m s t tfn transmit delay in normal mode, bus falling edge nstb = 5 v, en = 5 v; r l = 270 w , c l = 15 nf; 5.5 v < v bat < 27 v; measured from the rising edge on txd to v canh = 1.0 v 3 9 m s t trw transmit delay in wake-up mode, bus rising edge to normal levels nstb = 0 v, en = 5 v; r l = 270 w , c l = 15 nf; 5.5 v < v bat < 27 v; measured from the falling edge on txd to v canh = 3.0 v 3 6.3 m s t trw-s transmit delay in wake-up mode, bus rising edge to wake-up level nstb = 0 v, en = 5 v; r l = 270 w , c l = 15 nf; 11.3 v < v bat < 27 v; measured from the falling edge on txd to v canh = 8.9 v 3 18 m s t tfw-3.6 transmit delay in wake-up mode, bus falling edge with 3.6 m s time constant nstb = 0 v, en = 5 v; r l = 270 w , c l = 13.3 nf; 5.5 v < v bat < 27 v; measured from the rising edge on txd to v canh = 1 v, note 2 3 12.7 m s t tfw-4.0 transmit delay in wake-up mode, bus falling edge with 4.0 m s time constant nstb = 0 v, en = 5 v; r l = 270 w , c l = 15 nf; 5.5 v < v bat < 27 v; measured from the rising edge on txd to v canh = 1 v 3 13.7 m s
philips semiconductors product data AU5790 single wire can transceiver 2001 may 18 10 symbol unit max. typ. min. conditions parameter pin txd (continued) t trhs transmit delay in high-speed mode, bus rising edge nstb = 5 v, en = 0 v; r l = 100 w , c l = 15 nf; 8 v < v bat < 16 v; measured from the falling edge on txd to v canh = 3.0 v 0.1 1.5 m s t tfhs transmit delay in high-speed mode, bus falling edge nstb = 5 v, en = 0 v; r l = 100 w , c l = 15 nf; 8 v < v bat < 16 v; measured from the rising edge on txd to v canh = 1.0 v 0.2 3 m s pin rxd t dn receive delay in normal mode, bus rising and falling edge nstb = 5 v, en = 5 v; 5.5 v < v bat < 27 v; canh to rxd time measured from v canh = 2.0 v to v rxd = 2.5 v 0.3 1 m s t dw receive delay in wake-up mode, bus rising and falling edge nstb = 0 v, en = 5 v; 5.5 v < v bat < 27 v; canh to rxd time measured from v canh = 2.0 v to v rxd = 2.5 v 0.3 1 m s t dhs receive delay in high-speed mode, bus rising and falling edge nstb = 5 v, en = 0 v; 8 v < v bat < 16 v; canh to rxd time measured from v canh = 2.0 v to v rxd = 2.5 v 0.3 1 m s t ds receive delay in sleep mode, bus rising edge nstb = 0 v, en = 0 v; canh to rxd time, measured from v canh = min {(v bat 3.78 v), 7.13 v} to v rxd = 2.5 v 10 70 m s notes: 1. operation at battery voltages down to 5.3 volts is guaranteed by design. operation higher than 18 volts (18 v < v bat < 27 v) for up to two minutes is permitted if the thermal design of the board prevents reaching the thermal protection temperature limit, t sd , otherwise the device will self protect. typically these requirements will be encountered during jump start operation at t amb 85 c and v bat < 27 v. refer to the athermal characteristicso section of this data sheet, or application note an2005 for guidance. 2. this parameter is characterized but not subject to production test.
philips semiconductors product data AU5790 single wire can transceiver 2001 may 18 11 sl01255 txd 50% canh 3 v 2 v 1 v rxd 50% t tr t tf t d t d note: 1. when AU5790 is in normal, high-speed, or wake-up mode, the transmit delay in rising edge t tr may be expressed as t trn , t trhs , or t trw , respectively; the transmit delay in falling edge t tf may be expressed as t tfn , t tfhs , or t tfw , respectively; and the receive delay t d as t dn , t dhs , or t dw , respectively. figure 2. timing diagrams: pin txd, canh, and rxd
philips semiconductors product data AU5790 single wire can transceiver 2001 may 18 12 test circuits AU5790 txd nstb en rxd gnd canh rth bat 2.4 k w 5.1v 9.1 k w 1.5 k 1 m f s3 v bat i_can_lg sl01234 s1 s2 figure 3. loss of ground test circuit notes: opening s3 simulates loss of module ground. check i_can_lg with the following switch positions to simulate loss of ground in all modes: 1. s1 = open = s2 2. s1 = open, s2 = closed 3. s1 = closed, s2 = open 4. s1 = closed = s2
philips semiconductors product data AU5790 single wire can transceiver 2001 may 18 13 application information the information in this section is not part of the ic specification, but is presented for information purposes only. additional information on single wire can networks, application circuits, and thermal management are included in application note an2005. sl01200 can bus line tx0 rx0 txd rxd bat AU5790 transceiver en nstb canh +12v port gnd port +5v 2.4 to 2.7k w r d c l 9.1k w , 1% can controller (e.g. sja1000) note 1 tx0 should be configured to push-pull operation, active low; e.g., output control register = 1e hex. note 2 recommended range for the load resistor is 3k < r t < 11k. 220 pf 47 m h r t rth 10% 100 nf 1n5060 or equiv. l 1 to 4.7 m f figure 4. application circuit example for the AU5790 AU5790 transceivers may require additional pcb surface at ground pin(s) as heat conductor(s) in order to meet thermal requireme nts. see thermal characteristics section for details. table 2. maximum can bit rate mode maximum bit rate at 0.35% clock accuracy normal transmission 33.3 kbps high-speed transmission 83.3 kbps sample point as % of bit time 85% bus time constant, normal mode 1.0 to 4.0 m s
philips semiconductors product data AU5790 single wire can transceiver 2001 may 18 14 thermal characteristics the AU5790 provides protection from thermal overload. when the ic junction temperature reaches the threshold ( 155 c), the AU5790 will disable the transmitter drivers, reducing power dissipation to protect the device. the transmit function will become available again after the junction temperature drops. the thermal shutdown hysteresis is about 5 c. in order to avoid this transmit function shutdown, care must be taken to not overheat the ic during application. the relationships between junction temperature, ambient temperature, dissipated power, and thermal resistance can be expressed as: t j =t a + p d * q ja where: t j is junction temperature ( c); t a is ambient temperature ( c); p d is dissipated power (w); q ja is thermal resistance ( c/w). thermal resistance thermal resistance is the ability of a packaged ic to dissipate heat to its environment. in semiconductor applications, it is highly dependant on the ic package, pcbs, and airflow. thermal resistance also varies slightly with input power, the difference between ambient and junction temperatures, and soldering material. figures 5 and 6 show the thermal resistance as the function of the ic package and the pcb configuration, assuming no airflow. sl01249 0 50 100 150 200 0 50 100 150 200 250 thermal resistance (c/w) cu area on fused pins (mm2) very low conductance board low conductance board high conductance board figure 5. so-8 thermal resistance vs. pcb configuration, note 1, 2, 3 sl01250 0 50 100 150 0 100 200 300 400 500 thermal resistance (c/w) cu area on fused pins (mm2) very low conductance board low conductance board high conductance board figure 6. so-14 thermal resistance vs. pcb configuration, note 1, 2, 3
philips semiconductors product data AU5790 single wire can transceiver 2001 may 18 15 table 3 shows the maximum power dissipation of an AU5790 without tripping the thermal overload protection, for specified combin ations of package, board configuration, and ambient temperature. table 3. maximum power dissipation q ja p tot power dissipation max. additional foil area for thermal resistance t a = 85 c t a = 125 c board type additional foil area for heat dissipation k/w mw mw so-8 on high conductance board normal traces 103 631 243 c on d uc t ance b oar d 225 sq. mm of copper foil attached to pin 8. 82 793 305 so-8 on low conductance board normal traces 163 399 153 c on d uc t ance b oar d 225 sq. mm of copper attached to pin 8. 119 546 210 so-8 on very low conductance board normal traces 194 335 129 c on d uc t ance b oar d 225 sq. mm of copper attached to pin 8. 135 481 185 so-14 on high conductance board normal traces 63 1032 397 c on d uc t ance b oar d 105 sq. mm of copper attached to each of pins 1, 7, 8, & 14. 50 1300 500 so-14 on low conductance board normal traces 103 631 243 c on d uc t ance b oar d 105 sq. mm of copper attached to each of pins 1, 7, 8, & 14. 70 929 357 so-14 on very low conductance board normal traces 126 516 198 c on d uc t ance b oar d 105 sq. mm of copper attached to each of pins 1, 7, 8, & 14. 82 793 305 notes: 1. the high conductance board is based on modeling done to eia/jedec standard jesd51-7. the board emulated contains two one ounc e thick copper ground planes, and top surface copper conductor traces of two ounce (0.071 mm thickness of copper). 2. the low conductance board is based on modeling done to eia/jedec standard eia/jesd51-3. the board does not contain any ground planes, and the top surface copper conductor traces of two ounce (0.071 mm thickness of copper). 3. the very low conductance board is based on the eia/jesd51-3, however the thickness of the surface conductors has been reduced to 0.035 mm (also referred to as 1.0 ounce copper). 4. the above mentioned jedec specifications are available from: http://www.jedec.org/
philips semiconductors product data AU5790 single wire can transceiver 2001 may 18 16 power dissipation power dissipation of an ic is the major factor determining junction temperature. AU5790 power dissipation in active and passive states are different. the average power dissipation is: p tot = p int *dy + p pnint * (1-dy) where: p tot is total dissipation power; p int is dissipation power in an active state; p pnint is dissipation power in a passive state; dy is duty cycle, which is the percentage of time that txd is in an active state during any given time duration. at passive state there is no current going into the load. so all of the supply current is dissipated inside the ic. p pnint = v bat * i batpn where: v bat is the battery voltage; i batpn is the passive state supply current in normal mode. in an active state, part of the supply current goes to the load, and only part of the supply current dissipates inside the ic, causing an incremental increase in junction temperature. p int = p batan p loadn where: p batan is active state battery supply power in normal mode; p batan = v bat * i batan p loadn is load power consumption in normal mode. p loadn = v canhn * i loadn where: i batan is active state supply current in normal mode; v canhn is bus output voltage in normal mode; i loadn is current going through load in normal mode. i load = v canhn /r load i batn = i load + i int where: i int is an active state current dissipated within the ic in normal mode. i int will decrease slightly when the node number decreases. to simplify this analysis, we will assume i int is fixed. i int = i batn (32 nodes) i load (32 nodes) i batn (32 nodes) may be found in the dc characteristics table. a power dissipation example follows. the assumed values are chosen from specification and typical applications . assumptions: v bat = 13.4 v r t = 9.1 k w 32 nodes i batpn = 2 ma i batn (32 nodes) = 35 ma v canhn = 4.55 v duty cycle = 50% computations: r load = 9.1 k w / 32 = 284.4 w p pnint = 13.4 v 2 ma = 26.8 mw i load = 4.55 v / 284.4 w = 16ma p loadn = 4.55 v 16 ma = 72.8 mw i int = 35 ma - 16 ma = 19 ma p batan = 13.4 v 35 ma = 469 mw p int = 469 mw - 72.8 mw = 396.2 mw p tot = 396.2 mw 50% + 26.8 mw (1-50%) = 211.5 mw additional examples with various node counts are shown in table 4. table 4. representative power dissipation analyses nodes r load ( w ) v bat (v) i batpn (ma) p pnint (mw) v canhn (v) i load (ma) i batn (ma) i int (ma) p int (mw) dcycle p tot (mw) 2 4550 13.4 2 26.8 4.55 1 20 19 263.5 0.5 145.1 10 910 13.4 2 26.8 4.55 5 24 19 298.9 0.5 162.8 20 455 13.4 2 26.8 4.55 10 29 19 343.1 0.5 184.9 32 284.4 13.4 2 26.8 4.55 16 35 19 396.2 0.5 211.5 2 4550 26.5 2 53 4.55 1 20 19 525.5 0.5 289.2 10 910 26.5 2 53 4.55 5 24 19 613.3 0.5 333.1 20 455 26.5 2 53 4.55 10 29 19 723 0.5 388 32 284.4 26.5 2 53 4.55 16 35 19 854.7 0.5 453.8 by knowing the maximum power dissipation, and the operation ambient temperature, the required thermal resistance without trippi ng the thermal protection can be calculated, as shown in figure 7. then from figure 5 or 6, a suitable pcb can be selected.
philips semiconductors product data AU5790 single wire can transceiver 2001 may 18 17 sl01256 0 50 100 150 200 250 300 350 400 450 500 50 60 70 80 90 100 110 120 130 thermal resistance (c/w) ptot = 453.8 mw (vbat = 26.5 v, 32 nodes) ptot = 333.1 mw (vbat = 26.5 v, 10 nodes) ptot = 211.5 mw (vbat = 13.4 v, 32 nodes) ambient temperature ( c) figure 7. required thermal resistance vs. ambient temperature and power dissipation
philips semiconductors product data AU5790 single wire can transceiver 2001 may 18 18 so8: plastic small outline package; 8 leads; body width 3.9 mm sot96-1
philips semiconductors product data AU5790 single wire can transceiver 2001 may 18 19 so14: plastic small outline package; 14 leads; body width 3.9 mm sot108-1
philips semiconductors product data AU5790 single wire can transceiver 2001 may 18 20 definitions short-form specification e the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition e limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the dev ice at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limi ting values for extended periods may affect device reliability. application information e applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. disclaimers life support e these products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use i n such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes e philips semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. philips semiconductors ass umes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or m ask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right in fringement, unless otherwise specified. philips semiconductors 811 east arques avenue p.o. box 3409 sunnyvale, california 940883409 telephone 800-234-7381 ? copyright philips electronics north america corporation 2001 all rights reserved. printed in u.s.a. date of release: 05-01 document order number: 9397 750 08401

data sheet status [1] objective data preliminary data product data product status [2] development qualification production definitions this data sheet contains data from the objective specification for product development. philips semiconductors reserves the right to change the specification in any manner without notice. this data sheet contains data from the preliminary specification. supplementary data will be published at a later date. philips semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. this data sheet contains data from the product specification. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. changes will be communicated according to the customer product/process change notification (cpcn) procedure snw-sq-650a. data sheet status [1] please consult the most recently issued datasheet before initiating or completing a design. [2] the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the l atest information is available on the internet at url http://www.semiconductors.philips.com.

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